Key issues and controversial topics are debated by leaders from the IC industry. CICC panel discussions are well known for their lively and thought-provoking discussions. The Q&A sessions provide the audience the opportunity to weigh in on the important issues.
2020 CICC Panels
2022 CICC Panels
Monday, April 25, 2022
9:30 am-11:00 am PDT
Opensource Systems, Circuits, and Design: Is it the Future?
Session Chair: Mondira Pant, Intel, USA & Jing Li, University of Pennsylvania, USA
Co-Organizers: Shaolan Li, Georgia Tech, USA & Charles Augustine, Intel, USA
Mike Shuo-Wei Chen, Professor, University of Southern California, USA
Bio: Mike Chen received B.S. degree from National Taiwan University in 1998 and Ph.D. degree from University of California, Berkeley in 2006. As a graduate student researcher, he proposed and demonstrated the asynchronous SAR ADC architecture, which has been adopted today for low-power high-speed analog-to-digital conversion products in industry. At USC, he leads an analog mixed-signal circuit group, spanning over data converters, AI/ML computing, RF frequency synthesizers, power amplifiers, wireless/wireline transceiver designs, analog design automation, non-uniformly sampled circuits and systems. He and his team spend most of their time in exploring unconventional circuit architectures and design methodology. He has served or is serving as TPC and AE for various SSCS sponsored conferences and journal, and Distinguished Lecturer for SSCS.
Position Statement: Open source platform for circuit design community has already started, mostly from the digital side of the world, but more limited from the analog side. Open source environment enables fast exchange in ideas/recipes and hence can accelerate the circuit advancement/design time. In addition, it provides a unique education opportunity and expands the outreach. Of course, more steps need to take place before reaching a true open sharing eco-system, such as security, validation, and change of our minds.
Boris Murmann, Professor of Electrical Engineering, Stanford University, USA
Bio: Boris Murmann joined Stanford in 2004 after completing his Ph.D. degree in electrical engineering at the University of California, Berkeley in 2003. Dr. Murmann’s research interests are in mixed-signal integrated circuit design, with special emphasis on sensor interfaces, data converters, high-speed communication, and machine learning. He has served as an Associate Editor of the IEEE Journal of Solid-State Circuits, an AdCom member and Distinguished Lecturer of the IEEE Solid-State Circuits Society (SSCS), the Data Converter Subcommittee Chair and Technical Program Chair of the IEEE International Solid-State Circuits Conference (ISSCC), as well as the Technical Program Co-Chair of the tinyML Research Symposium. He currently chairs the IEEE SSCS future directions committee (SSCD), which established the SSCS’ open source “PICO” design contest.
Position Statement: Establishing a well-oiled open-source IC design ecosystem will be crucial for attracting talent into our field. The current generation of techies thrives on open sharing and collaboration in real time and across the globe. While not all aspects of the chip industry can be open-source, I foresee a growing open-source footprint also in the commercial IP space, for instance in crowdsourcing for legacy technologies, where differentiation is not in the IP itself, but how it is used to build systems.
David C. Kehlet, Research Scientist, Intel Corporation, USA
Bio: David Kehlet is a researcher at Intel working on pathfinding for programmable logic technology. David is currently developing chiplets and interfaces to enable a new model of electronic system development. Earlier at Intel, David was Vice President of IP Engineering, developing communications protocols, signal processing, and memory interfaces on Intel’s programmable logic devices.
Recently David represented Intel regarding chiplet technologies to the US Government, to industry and to Intel customers and partners. David earned BS and MS Electrical Engineering degrees from Stanford University and holds 18 patents.
Position Statement: Open source hardware IP is an accelerator of silicon design, especially as heterogeneous integration and chiplets are becoming more prevalent. Open source allows a designer to focus energy on their differentiating technology, while reusing open source IP for necessary but common technology such as die-to-die communication.
Pierre-Emmanuel Gaillardon, Associate Professor, University of Utah – CTO, RapidSilicon – Co-chairman, OSFPGA, USA
Bio: Pierre-Emmanuel Gaillardon is an Associate Professor and the Associate Chair for Academics and Strategic Initiatives in the Electrical and Computer Engineering (ECE) department The University of Utah, Salt Lake City, UT. He holds a Ph.D. degree in Electrical Engineering from CEA-LETI, France. Prof. Gaillardon is the recipient of NSF CAREER award, the IEEE CEDA Pederson Award, the DARPA Young Faculty Award, the IEEE CEDA Ernest S. Kuh Early Career Award and the ACM SIGDA Outstanding New Faculty Award. He recently co-founded, with semiconductor veteran and open-source hardware promoter Naveed Sherwani, the Open-Source FPGA foundation, whose goal is to democratize open-source FPGA technologies (including hardware fabrics and tooling), as well as RapidSilicon, an AI-enabled application-specific FPGA provider, whose key technology relies upon the open-source OpenFPGA framework.
Position Statement: Open-source Hardware (and supporting EDA) is a key towards more efficient innovation, where no engineering effort is wasted on developing base mundane technology layers and where resources are spent towards developing technological breakthroughs. Pushing the concept of re-use beyond the traditional IP model, it enables global democracy of silicon and knowledge sharing, enabling security, 24/7 bug fixes, customization opportunities and training opportunity all over the world.
Krste Asanović, Professor EECS, University of California, Berkeley / Chief Architect and Co-Founder, SiFive, USA
Bio: Krste Asanović is a Professor in the EECS Department at the University of California, Berkeley. He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005. He returned to join the faculty at Berkeley in 2007, where he co-founded the Berkeley Parallel Computing Laboratory (“Par Lab”), led the ASPIRE Lab, and co-led the ADEPT Lab. His main research areas are computer architecture, VLSI design, parallel programming and operating system design. He is currently Co-Director of the new Berkeley SLICE Lab (SpeciaLIzed Computing Ecosystems) and is also an Associate Director at the Berkeley Wireless Research Center. He leads the free RISC-V ISA project at Berkeley, is Chairman of the RISC-V Foundation, and is Chief Architect and co-founder of SiFive Inc. He is an ACM Fellow and an IEEE Fellow.
Position Statement: Open-source has always been an important driver of innovation in the hardware ecosystem since at least the 1970’s SPICE tape distributions, though recent decades witnessed a regression into the dark ages of proprietary tools and architectures. The new wave of open-source hardware standards, tools, and IP will drive the design productivity improvements needed to make future highly integrated product-specific chips an economic reality.
Monday, April 25, 2022
1:00 pm-2:30 pm PDT
Automatic Circuit Generation and AI-Driven Design: Future of Circuit Design?
Session Chair: Xin Zhang, IBM, USA & Jong Seok Park, Intel, USA
Co-Organizers: Patrick Mercier, University of California San Diego, USA & Kaushik Sengupta, Princeton University, USA
This panel session discusses future of analog/mixed signal circuit designs including analytical expression-based designs, programmatic approaches, and AI/ML-driven designs.
Elad Alon, CEO and co-founder of Blue Cheetah Analog Design, USA
Bio: Elad Alon is the CEO and co-founder of Blue Cheetah Analog Design, which is leveraging a decade of research and development on generator-based design methodologies to rapidly deliver tailored A/MS designs to meet our customers’ diverse needs. Elad is an Adjunct Professor at UC Berkeley in the EECS Department, where he was a Full Professor until Jul. 2021. He has served as an advisor or consultant to many semiconductor and electronics companies, including Lion Semiconductor (acquired by Cirrus Logic), Ayar Labs, Intel, Xilinx, Cadence, Wilocity (acquired by Qualcomm), and Cadence. He has been recognized with multiple best-paper as well as teaching awards and was elevated to the rank of IEEE Fellow in 2020.
Position Statement: While our industry is currently at a nexus of multiple unprecedented drivers for increased demand, the supply of qualified circuit designers – and especially custom/analog circuit designers – is by no stretch of imagination keeping pace. Given the fact that software and coding are much more natural affinities for the current and future generations of engineering students, programmatic approaches to IC design will (and at least in some subfields, arguably already have) emerge as our primary tool to drive improved efficiency. For analog/mixed-signal designs in particular, since it avoids the “keep adding constraints to guard against optimizer ignorance” modality that plague many approaches to analog automation, codification of human design knowledge in the form of circuit generators will be the most attractive approach for the most critical activities (layout, verification, and modeling) in that space.
David Z. Pan, Professor, The University of Texas at Austin, USA
Bio: David Z. Pan is Silicon Laboratories Endowed Chair Professor at the Department of Electrical and Computer Engineering, The University of Texas at Austin. His research interests include electronic design automation, synergistic AI and IC co-optimizations, design for manufacturing, hardware security, and design/CAD for analog/mixed-signal and emerging technologies. He has published over 420 refereed journal/conference papers and 8 US patents. He has served in many editorial boards and conference committees, including various leadership roles such as ICCAD 2019 General Chair and ISPD 2008 General Chair. He has received many awards, including 20 Best Paper Awards (from TCAD, DAC, ICCAD, DATE, ASP-DAC, ISPD, HOST, SRC, IBM, etc.), SRC Technical Excellence Award, DAC Top 10 Author Award in Fifth Decade, ASP-DAC Frequently Cited Author Award, ACM/SIGDA Outstanding New Faculty Award, NSF CAREER Award, IBM Faculty Award (4 times), and many international CAD contest awards. He has held various advisory, consulting, or visiting positions in academia and industry, such as MIT and Google. He has graduated 40 PhD students and postdocs who have won many awards, including ACM Student Research Competition Grand Finals 1st Place (twice, 2018 and 2021), and Outstanding PhD Dissertation Awards four times from ACM/SIGDA and EDAA. He is a Fellow of ACM, IEEE, and SPIE.
Position Statement: Modern AI advancement with domain-specific customizations can play key roles to improve IC design productivity and quality. Typical AI for IC application scenarios include breaking barriers between conventional design steps with better predictions and flows, providing better optimizations and accelerations within individual IC design steps, and so on. AI and agile/automated designs have recently shown great success on both digital and analog/mixed-signal ICs. However, there are still many challenges, such as data availability, model transferability, optimality, security, etc. This panel will have a lively discussion on this topic.
Hui Fu, Senior Principal Engineer, Intel Corporation, USA
Bio: Hui Fu is senior principal technologist in Design Enablement of Technology development group at Intel. His focus for design enablement is to leverage automation and AI/ML capabilities to accelerate DTCO (design technology co-optimization), to optimize design rules for new technology node, and to improve PDK (product design kit) quality. Prior to his current role, Hui was the design director of wireless baseband development and led intel’s last 4 generations wireless modem SOC development. Hui had multiple R&D leadership positions with intel, Infineon and Siemens in Germany, Singapore, China, and US.
Position Statement: Analog circuit design and layout is one of few fields in IC design that still significantly behind in term of automation and leveraging AI/ML for optimization. There are recent academic/industry progresses in generator technology (e.g: BAG), AMS layout synthesis and APR (e,g: MAGICAL/ALIGN) to enable AI/ML driven circuit optimization. However, an organized industry effort is required to tap the huge potential in the AMS optimization for power, performance, area and cost (PPAC).
Asad Abidi, Professor, University of California, Los Angeles, USA
Bio: Asad Abidi received the BSc degree in Electrical Engineering from Imperial College, London in 1976, and the PhD from the University of California, Berkeley in 1982. He worked at Bell Laboratories, Murray Hill until 1985, and then joined the faculty of the University of California, Los Angeles where he is Distinguished Chancellor’s Professor of Electrical Engineering. With his students he has developed many of the radio circuits and architectures that enable today’s mobile devices.
Professor Abidi has received the 2008 IEEE Donald O. Pederson Award in Solid-State Circuits and the 2012 Best Paper Award from the IEEE Journal of Solid-State Circuits. He was elected Fellow of IEEE in 1996, Member of the US National Academy of Engineering, and Fellow of TWAS, the world academy of sciences.
Position Statement: It is said that analog design is difficult to automate because of very complex, ad hoc tradeoffs known only to experts. But this overlooks the power of deep analysis that captures tradeoffs in simple expressions based on how the circuit operates. The expressions are qualitatively different for every type of circuit. But when discovered, they can lead to provably optimum circuit designs in remarkably short times. I see this as the only feasible path to design automation.
Taylor Hogan, Distinguished Engineer, Cadence Design Systems, USA
Bio: Taylor Hogan holds a BS degree in Computer Science and a MS degree in Electrical Engineering. Taylor holds several patents in the area of constraint driven optimization of multi substrate designs. He has been working in Electronic Design Automation for over 30 years. His research interest includes genetic optimization, machine learning, and functional programming. Taylor is a Distinguished Engineer at Cadence
Position Statement: AI driven circuit design and layout will ultimately beat human designs. This is no different from Alpha Go beating the best Go players. As long as there are crisp multi objective goals, the computer will find better solutions. Alas this does spell doom for the EE, they will be allowed time to engage in more rewarding problems.
Tuesday, April 26, 2022
2:00 pm-3:30 pm PDT
Is Photonics Going to Save Wireline?
Session Chair: Armin Tajalli, University of Utah, USA & Zhipeng Li, AMD, USA
Co-Organizers: Xi Chen, Nvidia, USA, Mozhgan Mansuri, Intel, USA, Tod Dickson, IBM, USA & Mayank Raj, Xilinx, USA
Data-heavy applications, such as machine learning and 5G, will further drive the demand for high-speed wireline links. Can electrical signaling keep up its power and cost efficiency with the increased frequency-dependent copper losses and channel equalization complexity? Or photonics is the way forward for wireline communications.
Ganesh Balamurugan, PE in Silicon Photonics Circuit Research, Intel, USA
Bio: Ganesh Balamurugan received the B.Tech degree in electronics and communication engineering from Indian Institute of Technology, Madras in 1996, M.S degree in Electrical and Computer Engineering from the University of Texas at Austin, and Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign in 2004. Since 2004, he has been with Intel Corporation working on high-speed wireline communications. His research interests include energy-efficient electrical and optical link design, silicon photonics-based communication circuits and system level optimization of electro-optical links. He is currently a principal engineer at Intel Labs.
Position Statement: All-electrical off-package wireline communication has scaled at a phenomenal cadence for over 2 decades, predictably delivering ~2X BW improvement every 3-4 years. If by ‘Is photonics going to save wireline?’, we mean ‘Can photonics continue this extraordinary scaling trend for the next 10 years?’, the answer is (a qualified) yes. Thanks to recent advances on multiple fronts – silicon photonics, CMOS SerDes, and IC packaging – the technical feasibility of co-packaged optical I/O has been proven through industry demos. Several challenges remain for high-volume proliferation – but none appear insurmountable.
Tony Chan Carusone, Professor, University of Toronto, Canada
Bio: Tony Chan Carusone has been a faculty member at the University of Toronto since completing his Ph.D. there in 2002. He has co-authored eight award-winning papers on chip-to-chip and optical communication circuits, ADCs, and clock generation. He has also been a consultant to industry since 1997. He is currently the Chief Technology Officer of Alphawave IP in Toronto, Canada.
Dr. Chan Carusone was a Distinguished Lecturer for the IEEE Solid-State Circuits Society 2015-2017 and served on the Technical Program Committee of the International Solid-State Circuits Conference from 2015-2021. He co-authored the latest editions of the classic textbooks “Analog Integrated Circuit Design” along with D. Johns and K. Martin, and “Microelectronic Circuits” along with A. Sedra and K.C. Smith. He has served as Editor-in-Chief of the IEEE Transactions on Circuits and Systems II: Express Briefs, an Associate Editor for the IEEE Journal of Solid-State Circuits, and is now Editor-in-Chief of the IEEE Solid-State Circuits Letters. He is a Fellow of the IEEE.
Position Statement: Improved electrical links will be a key enabler for photonics. The power, performance, and area of DSP-based transceivers for both electrical and optical links continue to benefit from architectural improvements and technology scaling. When and where the power and price of optical links decrease enough to offer benefits, they will be combined with electrical links to meet I/O bandwidth demands beyond 200Gbps/lane.
Tom Gray, Senior Director of Circuit Research, Nvidia, USA
Bio: C. Thomas Gray received the B.S. degree in computer science and mathematics from the Mississippi College, Clinton, MS, USA, and the M.S. and Ph.D. degrees in computer engineering from North Carolina State University, Raleigh, NC, USA. From 1993 to 1998, he was an Advisory Engineer at IBM, Research Triangle Park, NC, working in transceiver design for communication systems. From 1998 to 2004, he was a Senior Staff Design Engineer with the Analog/Mixed Signal Design Group, Cadence Design Systems, Cary, NC, USA, working on SerDes system architecture. From 2004 to 2010, he was Consultant Design Engineer and Technical Lead of SerDes architecture and design with Artisan/ARM, Cary. In 2010, he joined Nethra Imaging, Cary, as a System Architect. His work experience includes digital signal processing design and CMOS implementation of DSP blocks, as well as high-speed serial-link communication systems, architectures, and implementation. In 2011, he joined NVIDIA, Durham, NC where he is currently the Sr. Director of Circuits Research leading activities related to high-speed electrical and photonic signaling, security circuits, low-energy and resilient memories, circuits for deep learning, variation tolerant clocking, and power delivery.
Position Statement: The need for connectivity within and among high performance computing systems continues to accelerate with no end in sight. However, scaling of traditional electrical connectivity at the rack, card, and module level is hitting rapidly hitting a wall in terms of bandwidth density, energy efficiency, and reach above 200Gbps/lane. Any continued scaling of electrical bandwidth is likely thwarted by unacceptable reduced reach and high power. Traditional optics provides bandwidth and reach but at high system power. Silicon photonics provides a promising answer – particularly microring-based dense wave division multiplexed systems. Tiny ring-based photonics structures require low electrical power to drive and receive. Lower per channel bit rate allows for operation at a more optimal rate for advanced CMOS technologies. Tightly co-packaging optical engines with processor and switch die eliminate reach constraints. However, challenges remain in advanced multi-die packaging technology, mainstream high volume foundry support for photonics, and ultra-short reach electrical interfaces to host die.
Di Liang, Alibaba, USA
Bio: Di Liang is currently a Director-level Senior Staff Engineer in the Alibaba Group – North America. Prior that, he was a Distinguished Technologist at Hewlett Packard Labs in Hewlett Packard Enterprise where he led the advanced R&D of silicon and compound semiconductor integrated photonics for high-performance computing and emerging applications. He has authored and coauthored over 250 journal and conference papers, 1 edited book, 7 book chapters, and was granted by 49 patents with another 55+ pending. He is a Fellow of Optica (former OSA), a senior member of IEEE, and associated editor of Optica: Photonics Research and IEEE: Journal of Quantum Electronics.
Position Statement: Telecom and now datacom-proven photonic interconnect technology is extending its application territory where reach, bandwidth, power, and latency are all being demanded. Photonic integration is driving its cost down and further enhancing the performance to enable next-gen wireline communications.
Chen Sun, Chief Scientist Ayar Labs, USA
Position Statement: For over a decade, photonics has always been considered a solution for the “next-generation” of wireline communications. For “next-gen” to finally become “current-gen,” photonics must show that it can leverage the existing trillion-dollar electronics ecosystem and adopt the core principle tenets of what originally made CMOS so successful.
Wednesday April 27, 2022
9:00 am-10:30 am PDT
Can Quantum Computing Solve Real World Problems?
Session Chair: Sudipto Chakraborty, IBM, USA & Swaroop Ghosh, Penn State University, USA
Co-Organizers: Jaydeep Kulkarni, The University of Texas at Austin, USA & Charles Augustine, Intel, USA
This panel will discuss real world applications of quantum computing. It consists of distinguished speakers from academia, industry, research organizations, and startups. It’ll provide practical insights of the diverse technical aspects that need to be solved in order to make quantum computing a success to solve real world problems.
Scott Aaronson, Professor of Computer Science, The University of Texas at Austin, USA
Bio: Scott Aaronson is David J. Bruton Centennial Professor of Computer Science at the University of Texas at Austin. He received his bachelor’s from Cornell University and his PhD from UC Berkeley. Before coming to UT Austin, he spent nine years as a professor in Electrical Engineering and Computer Science at MIT. Aaronson’s research in theoretical computer science has focused mainly on the
capabilities and limits of quantum computers. His first book, Quantum Computing Since Democritus, was published in 2013 by Cambridge University Press. He’s received the National Science Foundation’s Alan T. Waterman Award, the United States PECASE Award, the Tomassoni-Chisesi Prize in Physics, and the ACM Prize in Computing, and is a Fellow of the ACM.
Position Statement: Quantum computing should indeed provide advantages for certain very specific real-world problems, including (of course) breaking currently-used public-key crypto, the simulation of quantum physics and chemistry, and eventually Grover speedups for optimization and machine learning. Whether quantum computing will have real-world advantages beyond that list is an extremely interesting and difficult question to which, despite a lot of confident hype, we’re still figuring out the answer.
Anne Matsuura, Ph.D. Director of Quantum Applications & Architecture, Intel Labs, USA
Bio: Dr. Anne Matsuura is the Director of Quantum Applications & Architecture at Intel Labs. Previously, she held positions as the Chief Scientist of the Optical Society (OSA) and the Chief Executive of the European Theoretical Spectroscopy Facility (ETSF). She has been a strategic investor in technology start-ups at In-Q-Tel and a funder of basic science at the Air Force Office of Scientific Research. Anne was the recipient of a Fulbright Scholarship to Japan and is an elected fellow of the OSA. She also is a member of the Board of Directors of Science Counts, a non-profit with the mission of enhancing the public’s perception of science. Anne received her Ph.D. in physics from Stanford University.
Position Statement: Quantum computers promise the ability both to execute certain algorithms exponentially faster than with classical computers and to solve problems that are intractable for classical computers. However, millions of qubits are likely necessary to achieve this promise. At Intel Labs, we are using a workload-driven co-design approach on today’s small qubit systems to better understand how to develop the architecture for practical large-scale commercial quantum machines of the future.
Margaret Martonosi, Assistant Director, Computer and Information Science & Engineering, National Science Foundation, USA
Bio: Margaret Martonosi is the US National Science Foundation’s (NSF) Assistant Director for Computer and information Science and Engineering (CISE). While at NSF, Dr. Martonosi is on leave from Princeton University where she is the Hugh Trumbull Adams ’35 Professor of Computer Science. Dr. Martonosi’s research interests are in computer architecture and hardware-software interface issues in both classical and quantum computing systems. Dr. Martonosi is a member of the National Academy of Engineering and the American Academy of Arts and Sciences. She is a Fellow of the Association for Computing Machinery (ACM) and the Institute of Electrical and Electronics Engineers (IEEE)
Position Statement: Quantum computing holds great promise both for its potential to make some useful problems tractable sooner than other approaches, and also for its potential to offer results and insights applicable to other scenarios and computational models. The notion of “useful” or “better” or “success” will not be a single clear moment, but rather a set of progress milestones. Some of these milestones (e.g. cryogenic circuity, improved control, …) may also be useful for high-end computing in non-quantum settings as well.
Oliver Dial, IBM Fellow, Quantum Hardware Research, USA
Bio: Dr. Dial received his PhD from MIT in 2007 for research in two-dimensional electron and hole systems. He then entered the field of quantum computing as a post-doc at Harvard, demonstrating the first two-qubit gate between semiconductor singlet-triplet qubits and performing pioneering charge noise spectroscopy in these systems. He joined IBM in 2012 with a focus on qubit coherence, gate operations, and high-performance multiqubit systems and in 2021 was named an IBM Fellow for his contributions to quantum computing hardware.
Position Statement: Quantum can’t solve real world problems just yet but can create value! Quantum advantage (a quantum computer solving an “interesting” problem better than a classical computer) is just around the corner. Thus, we can still create value with quantum computers as users around the world explore domain specific algorithms and solutions to be ready when we get there.
Bogdan Staszewski, Chief Scientific Officer, Equal1 Labs, Ireland
Bio: Robert Bogdan Staszewski received his Bachelors, Masters and PhD degrees in electrical engineering from the University of Texas at Dallas, in 1991, 1992, and 2002, respectively. From 1991 to 1995, he was with Alcatel Network Systems in Texas. He joined Texas Instruments Incorporated in 1995. In 1999, he co-started the Digital RF Processor Group. He was appointed as a CTO of the DRP Group from 2007 to 2009. In 2009, he joined the Delft University of Technology, Delft, The Netherlands, where he currently holds a guest appointment of Full Professor. Since 2014, he has been a Full Professor with the University College Dublin, Dublin, Ireland. He is a Chief Scientific Officer of Equal1 Labs, a startup company with offices in Silicon Valley and Dublin, Ireland, aiming to build a first practical quantum computer. He has authored or coauthored seven books, over 150 journal and 200 conference publications, and holds 200 issued U.S. patents.
Position Statement: The first quantum computers to be of practical use must have millions of qubits. This is far away from the current state of the art. We believe that only advanced CMOS technology with its full integration capability of quantum dots and its interface circuitry can offer a realistic chance.