2020 CICC Panels

2023 CICC Panels

Key issues and controversial topics are debated by leaders from the IC industry. CICC panel discussions are well known for their lively and thought-provoking discussions. The Q&A sessions provide the audience the opportunity to weigh in on the important issues.

Panel Sessions

Tuesday, April 25

1:45 pm-3:15 pm

It’s 2023. Where are our self-driving cars?

Description: The development of self-driving cars is heavily reliant on the progress made in integrated circuits (ICs) technology. As we move further into 2023, the question on everyone’s mind is: where are our self-driving cars and what role do ICs play in making them a reality?

The panel aims to discuss the specific hardware advancements in ICs that have contributed to the development of self-driving cars. The discussion will cover the technological advancements in sensors, processors, memory, and communication that are essential for the development of autonomous vehicles.

The panelists will delve into the challenges facing the hardware industry in creating ICs that can meet the demands of self-driving cars. They will explore the need for high-performance and low-power consumption ICs that can handle the complex data processing required for autonomous driving.

Some of the questions that could be discussed include:

  • How have advancements in ICs contributed to the development of self-driving cars?
  • What are the specific hardware challenges that need to be addressed to make self-driving cars a reality?
  • How can we optimize ICs to minimize power consumption and maximize performance for self-driving cars?
  • What role will new IC architectures play in the development of self-driving cars?
  • How will the hardware industry need to evolve to meet the demands of self-driving cars?
  • Which are the safety aspect of the ICs that need to contribute to the self driving world?

Overall, the panel aims to provide a comprehensive overview of the specific hardware advancements required for the development of self-driving cars. The discussion will be of interest to anyone interested in the integration of circuits and the future of autonomous driving.



Brian Ginsburg, Texas Instruments, USA


Bio: Brian Ginsburg received his S.B., M.Eng., and Ph.D. degrees from the Massachusetts Institute of Technology.   He joined Texas Instruments, Dallas, Texas in 2007 working in its wireless and radar businesses. Now, he is a Distinguished Member of Technical Staff and director of RF and mm-wave research within TI’s Kilby Labs. He has served on the technical program committees for the International Solid-State Circuits Symposium and the Symposium on VLSI Technology and Circuits.






Daesik Park, Motional, USA

Bio: Daesik Park received his B.S., M.S. and Ph.D. degrees from the Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) in 2002, 2004 and 2009, respectively. His graduate research was on low-power SoC design. From 2009 to 2022, he was with Samsung Electronics System LSI, where he designed LTE-A (3GPP Rel.12) modems which were extensively used in Galaxy S7/S7 Edge/S6/S6 Edge/Note 5, etc. Also, he served as a project manager (PM) in charge of Wi-Fi/Bluetooth/GNSS. Since 2022, he has been with Motional as a principal PM, an autonomous vehicle company, where he is in charge of High-Performance Computing (HPC).


Position statement:  ICs are essential for self-driving cars. However, for Automotive ICs, higher performance and lower power consumption is essential.


Frank Praemassing, Infineon Technologies, USA


Bio: Frank Praemassing has been Mixed Signal Architect at Infineon Technologies AG since 2013. His focus is on system resources for ATV MCU’s, which include power and clock-management, standby controllers, and system mode management. Praemassing is a current member of the ISSCC Power Management Subcommittee. Praemassing was born in Adenau, Germany, in 1972. He holds a Diploma in Electrical Engineering from the Bochum University and PhD from University Duisburg-Essen. He joined Infineon Technologies AG in 2003. Praemassing firmly believes that the car of the future will be allelectric and autonomous, user-centric, fully connected and cybersecured.





Manisha Gambhir, Marvell Semiconductor, USA

Bio: Manisha Gambhir is a Distinguished Engineer and a technology architect at Marvell Semiconductors, where she leads development of complex mixed-signal Integrated-Circuits with advanced nanometric technologies such as ADC based analog front-ends and high speed SerDes solutions. At Marvell, she also drives development of automotive grade IP and SerDes meeting stringent grade and qualification requirements. She leads cross functional teams and projects spanning geographies and delivering key solutions for Marvell’s leading products in Storage, Networking, and Automotive space.

She received her PhD and MS degree from Texas A&M University in Electrical Engineering and holds several US patents in field of circuit design and architectures. She is also passionate about mentoring and coaching budding engineers and serves as a liaison for key university collaborations incubated through Marvell.

Wednesday, April 26

9:00 am-10:30 am

Improving ASIC Productivity

Wednesday, April 26

1:00 pm- 2:30 pm

CHIPS Act and Future of Semiconductor Innovation

While the CHIPS Act in the U.S. has garnered much attention for its efforts to revitalize U.S. semiconductor manufacturing, it has also allocated roughly $11B towards advanced semiconductor research and development. As a result, the broader semiconductor community including industry and universities are now tasked to collaborate and build an ecosystem for enabling not only the development of future materials and devices but also rapid prototyping of novel systems. The latter is of particular interest to the solid-state circuits design community, as it opens the door to disruptive innovation at the circuits and systems level. This panel will address future directions in circuits and systems research as enabled by the CHIPS act. What parts are needed to enable this ecosystem and who should develop them? How does heterogenous integration play a role in this ecosystem, and what packaging technologies are required? How do we ensure that rapid prototypes developed in research activities are sufficiently robust to transition to production-level manufacturing? Will universities have sufficient access to advanced CMOS technology nodes to adequately contribute to this ecosystem? What outcomes should we expect in the next 10 years?




Tony Chan Carusone, Chief Technology Officer, Alphawave Semi Professor, University of Toronto, Canada


Bio: Dr. Tony Chan Carusone has taught and researched integrated circuits and systems in academia and industry for over 20 years. He has been a faculty member at the University of Toronto since completing his Ph.D. there in 2002.  He and his graduate students have received eight best-paper awards at leading conferences for their work on chip-to-chip and optical communication circuits, analog-to-digital conversion, and precise clock generation.  He has also been a consultant to industry since 1997, and in 2022 became the Chief Technology Officer of Alphawave Semi in Toronto, Canada.



Dr. Chan Carusone was a Distinguished Lecturer for the IEEE Solid-State Circuits Society 2015-2017 and served on the Technical Program Committee of the International Solid-State Circuits Conference from 2015-2021.  He has co-authored the latest editions of the classic textbooks “Analog Integrated Circuit Design” along with D. Johns and K. Martin, and “Microelectronic Circuits” along with A. Sedra and K.C. Smith. He was Editor-in-Chief of the IEEE Transactions on Circuits and Systems II: Express Briefs in 2009, an Associate Editor for the IEEE Journal of Solid-State Circuits 2010-2017 and is now Editor-in-Chief of the IEEE Solid-State Circuits Letters.  He is a Fellow of the IEEE.


Position Statement: Fostering the democratized chiplet ecosystem emerging in the US and its trading partners is the best way for the CHIPS Act to pave the way for continued technology leadership.  A flexible supply chain for advanced packaging and a secure platform for the increasingly complex EDA tools will be key ingredients.  Finally, whereas cutting-edge fab will support the industry’s development of strategic compute and communication chips, streamlined access to lower-cost N-1 and older nodes can fuel Universities’ key role in developing a world-class workforce.

Arnett Brown, Senior Lead EngineerBooz Allen Hamilton, USA
Bio: Arnett Brown III is a hardware engineer working with the DARPA Microsystems Technology Office (MTO) since 2011 as a technical adviser. He has supported several programs in hardware security and Electronic Design Automation, as well as programs under the DARPA MTO Electronics Resurgence Initiative (ERI).
Prior to joining Booz Allen Hamilton, Mr. Brown was a custom circuit design engineer for IBM in Research Triangle Park, North Carolina, where he contributed to the development of the POWER7, XBOX 360 and Cell Broadband Engine microprocessors. Prior to IBM, he developed custom circuits and design methodologies for Lockheed Martin Space Electronics and Communications (now a part of BAE Systems).
Mr. Brown holds a Master of Science degree in Electrical Engineering from the Georgia Institute of Technology, and a Bachelor of Science degree from Hampton University. He is a Senior Member of the IEEE and holds three patents in the area of Electronic Design Automation.


  1. Jan Vardaman, President and Founder, TechSearch International, Inc., USA


Bio: E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987.  She is the co-author of How to Make IC Packages (by Nikkan Kogyo Shinbunsha), a columnist with Printed Circuit Design & Fab/Circuits Assembly, and the author of numerous publications on emerging trends in semiconductor packaging and assembly.  She served on the NSF-sponsored World Technology Evaluation Center (WTEC) study team involved in investigating electronics manufacturing in Asia and on the U.S. mission to study manufacturing in China.  She is a senior member of IEEE EPS and is an IEEE EPS Distinguished Lecturer.  She received the IMAPS GBC Partnership award in 2012, the Daniel C. Hughes, Jr. Memorial Award in 2018, the Sidney J. Stein International Award in 2019, and she is an IMAPS Fellow.  She is a member of MEPTEC, SMTA, and SEMI.  Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.


Position Statement: The semiconductor industry has entered a new era in which economics dictates a new method of advanced chip design.  This means a movement away from monolithic silicon and the adoption of chiplets, bringing new opportunities and challenges.  Some designs will use side-by-side arrangements but in others, a 3D connection with hybrid bonding will be needed to achieve the I/O density.  In this new era, co-design of silicon and package is a must and designers must embrace a new way of thinking, including system-level architecture.  Research activities need to address the new reality.  Universities will need to take a new approach to design.  Some portion of the IC will need be designed in older nodes and a much smaller portion in advanced nodes, the package will provide the link between the chiplets and understanding package tradeoffs is essential.  Successfully moving from research to manufacturing will require universities to leverage cross disciplines, drawing from electrical, material science, and mechanical design with a system perspective.  Closer cooperation between industry and university researchers is necessary.



Jim Wieser, Directory, Technology and University Research, Texas Instruments, USA


Bio: Jim serves Texas Instruments as Director of Technology and University Research within the CTO Office at Texas Instruments. In this role he identifies and drives strategic technology initiatives, research strategy and aligns university research to the needs of the company. His semiconductor experience spans over 40 years in the areas of design, product development management and technologist.  He is an IEEE Life Senior Member and SRC Executive Technical Advisory Board member for TI.   Jim has been an active member of the SRC-SIA Decadal Plan for Semiconductors committee, chairing the analog focus area workshop and report.  He is also currently active in leading Analog and Mixed Signal efforts towards an NSTC proposal.




Jim received his BSEE and MSEE from University of Michigan and joined National Semiconductor starting his career in the semiconductor industry. He began as a circuit designer in the pioneering days of analog CMOS, including switched capacitor filters and data converters. Jim developed circuits and managed design of telecom products, including voice band codecs, modems, ISDN and ADSL. Jim spent two years as Director/VP of Analog/Mixed Signal Methodology refining the analog design flow to address National’s SoC product strategy. Later he led the development of 10/100 and Gigabit Ethernet Phys and MACs in the Networking division as Design Director. In 2002 Jim was promoted to Chief Technologist of the Interface Division and was later promoted to Chief Technologist for the Product Group covering four product divisions.   He later joined the CTO office to drive strategic technology and university research.  Jim holds 21 patents in the area of analog circuits and system design.


Position Statement: The CHIPS Act is an opportunity to motivate the microelectronics ecosystem to increase focus on innovation and manufacturing within the U.S.  We must remember it is only a “catalyst” and, if successful, will lead to a sustained microelectronics/semiconductor leadership position for the U.S.   This will not be without key challenges as it needs to accelerate research to commercialization by providing nationwide access to technologies including process/fab, packaging and knowledge across a traditionally very competitive environment (industry and academia).  Workforce development is a key element require for sustained leadership and necessitates increased awareness, training and true engagement to build excitement and impact in what is nearly an invisible industry (i.e. it is behind the scenes of apps and communications).  We can only succeed by working together.


Wednesday, April 26

9:00 am-10:30 am

Improving ASIC Productivity – Is Software-Like Design the Answer? How Architecture and EDA Are Shifting the Focus of Design for Digital ASIC Designers

Session Chair: Yingyan (Celine) Lin, Georgia Tech, USA


Brucek Khailany, NVIDIA, USA

Bio: Brucek Khailany joined NVIDIA in 2009 and is the Senior Director of the ASIC and VLSI Research group. He leads research into innovative design methodologies for IC development, ML and GPU assisted EDA, and energy efficient DL accelerators.  Over 13 years at NVIDIA, he has contributed to many projects in research and product groups spanning computer architecture and VLSI design. Prior to NVIDIA, Dr. Khailany was a Co-Founder and Principal Architect at Stream Processors, Inc where he led R&D related to parallel processor architectures. He received his PhD in Electrical Engineering from Stanford University and BSE degrees in Electrical and Computer Engineering from the University of Michigan.


Position Statement:

In the post-Moore’s law era, the capabilities we can put into new SoCs are increasingly limited by the engineering effort associated with ASIC design and especially verification.  As new workloads require more performance and energy efficiency from further specialization, we expect demands on ASIC productivity improvements to continue to increase.  To address this challenge, new tools and automation are critical.  Two promising approaches for improving ASIC design and verification productivity are the use of high-level hardware languages for hardware design and machine learning methods.  High-level hardware languages and high-level synthesis tools enable designers to write code at a more abstract level, make it easier to exploit modularity and reuse in hardware design, and simplify debugging.  Meanwhile, machine learning based classifiers can help with automate time-consuming tasks such as debugging and verification coverage closure.  Finally, generative Transformer-based large language models fine-tuned on hardware datasets can help improve ASIC design and verification productivity by automating code generation and debugging.

Sabya Das, Group Director, Software R&D at Synopsys Inc, USA

Bio: Sabya Das has over 25 years of experience in the EDA software industry for FPGA and ASIC design. He has worked in the development of EDA tool-chains across the entire flow including the domains of Logic Synthesis, Physical Synthesis, Timing, and Power Optimization, Placement, Routing, and DFM.

For the last 15 years, he has been managing multi-site teams for developing EDA software. Successfully built teams from the ground up. Currently, leading multiple R&D teams in the Synopsys Zebu Emulation Platform. Sabya’s team is located in the R&D sites in San Francisco Bay Area, China, Taiwan, and India.

He co-authored about 20 technical publications in IEEE/ACM journals and conferences and co-authored about 30 patents.

In addition, Sabya has been actively involved in the research community. Have been serving as technical program sub-committee chair, track-chair, and session chair in different conferences/symposia, like DAC, ICCAD, ICCD, FPGA, FPL, ISPD, and IWLS. Also, he has organized invited sessions in DAC/ICCAD and have been a contest co-chair in ICCAD.

Chuck Alpert, Cadence Design Systems, USA

Bio: Charles Alpert received a BS and BA degree from Stanford University in 1991 and his Ph.D. in Computer Science from UCLA in 1996.  From then until 2014, he worked at IBM Research in Austin, Texas.  After that he joined Cadence Design Systems, where he has had many roles including leading the R&D groups for early global routing, clock optimization, and synthesis. His latest role is running Cadence’s flagship AI product, Cerebrus.


Charles has been heavily involved with the academic community, having published over 100 journal and conference papers and he has received over 100 patents.  He has severed as Associate editor of IEEE Transactions on Computer-Aided Design and as chair of the 2016 Design Automation Conference. He is an IEEE fellow.

Mehdi Saligane, University of Michigan, USA

Bio: Mehdi Saligane is a Research Scientist and Intermittent Lecturer in the Electrical Engineering and Computer Science department at the University of Michigan, Ann Arbor. He received his B.S. in Electrical Engineering and Computer Science from Ecole Polytechnique in Grenoble, France, in 2009, his M.S. in Electrical Engineering and Computer Science from the University of Grenoble, France, in 2011, and his Ph.D. degree in Electrical Engineering from the University of Aix-Marseille in 2016. His current research interests are in low-power and energy-efficient IC design, with a recent focus on open-source EDA and analog and mixed-signal IC design automation.

He is the recipient of the Google Cloud Research Innovators Award and the Google Research Faculty Award in 2023 and 2021, respectively.  Dr. Saligane currently serves as chair of the Analog Working Group, as a member of the Technical Steering Committee at CHIPS Alliance, and as a technical member of SSCS’ open source ecosystem. He is also the co-founder and organizer of the SSCS Code-a-Chip Notebook Competition at ISSCC and the SSCS Chipathon Design Contest.

Position Statement: Given the critical role of the semiconductor industry in national security, economic growth, and overall well-being, it is crucial to address the challenges faced by traditional chip design ecosystems. High design costs, limited access to fabrication, hard-to-use tools, and inadequate design support are among the obstacles that hinder the overall IC design productivity. Custom circuits typically rely on manual design due to their unique requirements, whereas digital flow has seen widespread automation. This lack of automation leads to long design cycles and costs. As such, adopting innovative and agile practices such as automation, reusability, reproducibility, and open collaboration is essential to expedite chip-building efforts and pave the way to improve productivity in the semiconductor industry.

Jaydeep Kulkarni, The University of Texas at Austin, USA

Bio: Jaydeep Kulkarni is an assistant professor and holds the Fellow of Silicon Laboratories Endowed Chair in Electrical Engineering and Fellow of AMD Chair in Computer Engineering in the Department of Electrical and Computer Engineering at The University of Texas at Austin.


He received the Ph.D. degree from Purdue University in 2009. During 2009-2017, he worked as a Senior Staff Research Scientist at Intel Labs in Hillsboro, OR.

He has filed 35 patents, published 2 book chapters, and over 100 papers in referred journals and conferences. His research is focused machine learning hardware accelerators, in-memory computing, emerging nano-devices, heterogeneous and 3D integrated circuits, hardware security, and cryogenic computing. Dr. Kulkarni currently is a fellow of Silicon Labs Chair in electrical engineering and a fellow of AMD chair in computer engineering at UT Austin. He received 2008 Intel Foundation Ph.D. fellowship award, 2010 Purdue school of ECE outstanding doctoral dissertation award, 2015 IEEE Transactions on VLSI systems best paper award, 2015 SRC outstanding industrial liaison award, and Micron faculty awards. He has participated in technical program committees of CICC, A-SSCC, DAC, ICCAD, ISLPED, and AICAS conferences. During his tenure at Intel Labs, he served as an industrial distinguished lecturer for IEEE Circuits and Systems Society and as an industrial liaison for SRC, NSF programs. He has served as a conference general co-chair for 2018 ISLPED, and currently serving as an associate editor for IEEE Solid State Circuit Letters, and IEEE Transactions on VLSI Systems. He is a senior member of IEEE and currently serving as the chair of IEEE solid state circuits society and circuits and systems society central Texas joint chapter.


1:00 pm-2:30 pm

Where is the balance between circuit and system-level innovation in our solid-state circuit conference?

Session Chair: Mark Oude Alink, University of Twente, Netherlands


Thirty years ago, building blocks like opamps, bandgap references, LNAs, and mixers dominated our solid-state circuits conferences. Nowadays, they are the exception rather than the rule. Published chips are getting bigger and more complex. Hallway conversations include remarks from “there is hardly any useful circuit technique I could apply in my own work” to “there is no place anymore for academics” and “we are the solid-state circuit society, not the circuits & systems society”. Has transistor-level innovation run out of steam? Or is it merely our conception of what constitutes a circuit or a system?




Stefano Pietri, Technical Director IP licensing, NXP Semiconductors, USA


Bio: Stefano Pietri is Technical Director of IP Licensing and member of the Analog Mixed Signal Innovation Board at NXP semiconductors, Austin TX. Dr. Pietri completed his Ph.D. in Computer Science Engineering at the Università di Modena e Reggio Emilia in 2001. His R&D interest includes mixed signal integrated circuits with emphasis in Automotive and Consumer Microcontrollers IP’s, system architecture definition, design and productization. Dr. Pietri is Senior Member of the IEEE and Chair of the IEEE SSCS & CAS Central Texas Chapter.


Position Statement: Evolution: A gradual process in which something changes into a different and usually more complex or better form. Evolution has a cost, and in order to be sustainable, the change has to be motivated by higher performance or lower cost, preferably both. In the industry we have to maintain a 5x improvement (performance increase X cost reduction X power reduction) at each new product generation to sell our products and justify the cost of evolution. At the same time, analog scaling due to process improvement significantly slowed down around 1995, somewhere between 0.25um and 0.35 um, and for logic circuits, Dennard scaling ended around 2005 at 90nm. Therefore circuit and systems techniques have been mostly responsible to keep up the pace since then, whether is mixed signal techniques, multi-core and advanced voltage scaling. In the next few years we will see a shift toward what I call the Artificial Intelligence of Things (AIT), i.e. the ubiquitous use of AI in all the aspect of life, including systems and circuit design.



Alessandro Piovaccari, Adjunct Professor, University of Bologna, Italy & CEO/CTO, Apicio Enterprises, USA


Bio: Alessandro Piovaccari is a Visiting Fellow and Adjunct Professor at the University of Bologna. He is the VP of Conferences for the IEEE Solid-State Circuits Society, a board member CTO Council of the Global Semiconductor Alliance, and the Center for Leadership Education at the Johns-Hopkins University, an advisor for the Berkeley Skydeck and Silicon Catalyst startup incubators. He is also part of the technical advisory board of several semiconductor startups. He has more than 25 years of technical and management experience in the semiconductor industry, including CTO and Senior Vice President of Engineering atSilicon Labs. He co-architected and led the development of many wireless and IoT SoC integrated circuits, which have surpassed the 4 billion devices shipments. Most notably, the first single-chip TV tuner IC, still used by nine of the world’s top-ten TV makers, and 80 percent market share. He has been a long-time contributor for the IEEE Custom Integrated Circuits Conference (CICC), covering the role of Technical Program Chair for the year 2015 and being part of the steering committee from 2015 to 2022. Alessandro received his PhD and Laurea degrees in EECS from the University of Bologna and a Post-Grad certificate (summa cum laude) in EECS from the Johns-Hopkins University. He is a Senior Member of IEEE and Lifetime Fellow at Silicon Labs. He received an IEEE SSCS award in leadership for organizing the first virtual solid-state conference. He holds 32 US patents, including a Patent of the Year award.


Position Statement: Since the introduction of EDA tools, hierarchical design has been the key ingredient that led to design of complex SoCs. The corollary has been the public availability of massive amount of technical information and a lot of IP libraries. The easy answer is that we are now at the point that one could design a new full SoC without designing a single circuit. The real answer is that easy doesn’t imply either innovation or differentiation. My position is that the real innovation always come from the in-between layers of the design hierarchy, the co-design of system-circuit and circuit-device, and why not software-system as well.


Farhana Sheikh, Principal Engineer at Intel Corporation, USA


Bio: Dr. Farhana Sheikh is a Principal Engineer at Intel’s Programmable Solution Group’s CTO group. She has over 15 years of experience in ASIC and DSP/communications research including adaptive DSP, crypto, graphics, quantum wireless control, and 5G+ wireless. Since joining PSG, after 10+ years in Intel Labs, Farhana’s research focuses on 2-D and 3-D chiplet + FPGA integration research, with a focus on 3D heterogeneous integration for next generation wireless and sensing applications. Farhana has published over 50 papers and filed 22 patents, and has initiated the AIB-3D open-source specification for 3D chiplet heterogeneous integration. Farhana was instrumental in enabling Intel 16 for Intel’s IDM2.0 and is the co-creator of Intel’s University Shuttle Program. Outside of Intel she volunteers for IEEE Solid-State Circuits Society (SSCS) and is the SSCS Women in Circuits Committee Chair. Farhana is a co-recipient of 2020, 2019, and 2012 IEEE ISSCC Outstanding Paper Awards. In 2021, Farhana was recognized for her mentorship work with students and faculty by the Semiconductor Research Corporation (SRC) that awarded her the 2021 Mahboob Khan Outstanding Industry Liaison Award. She is IEEE SSCS Member-at-Large for 2022-2024, and IEEE SSCS Distinguished Lecturer for 2023-2025.


Position Statement: Heterogeneous integration (HI) and associated technologies forces circuit designers to consider platform or system-level metrics in addition to circuit-level metrics simultaneously, forcing innovation at multiple layers of design hierarchy.  SSCS conferences have traditionally focused on circuit-level innovation, whereas in a new era of chiplets, dielets, and multi-die interconnects, HI packaging platforms for emerging applications, innovations at both the system and circuit level need to be highlighted at SSCS conferences.


Jeffrey Walling, Professor at Virginia Tech, USA


Bio: Jeffrey Walling received his Ph.D. from University of Washington in 2008 and is currently an associate professor at Virginia Tech. He has held industrial positions at Motorola, Intel, Qualcomm and Skyworks, working from cellular handset development to RF-SoC development.


Position Statement: The definition of when a circuit changes to a system is often quite blurry; for instance, an op-amp may consist of 20 transistors, which may be similar in number for a simple receiver. We generally consider one a circuit and the other a system. Transistor circuits use only 3-4 terminals of a device and most topologies are well understood; hence continued innovation at this level is not impossible, but also is not likely.  Systems comprised of collections of smaller circuits are boundless and hence an opportunity for researchers and developers to continue to make contributions of interest, but also require different infrastructure and perhaps a different funding ecosystem if continued improvements are to be realized.


Anne-Johan Annema, Professor at University of Twente, Enschede, Netherlands

Bio: Anne-Johan Annema received the MSc. and PhD degrees in electrical engineering from the University of Twente, Enschede, The Netherlands, in 1990 and 1994, respectively. In 1995, he joined Philips Research in Eindhoven, where he worked on physics-electronics-related projects. This included self-learning electronic systems and feasibility studies of conventional (analog) electronics in (then) future IC technologies, aiming at maximizing their joint performance potential. This yielded among others concepts for low-power low-voltage circuits, work on fundamental limits on analog circuits in conjunction with process technologies, high-voltage circuits in low-voltage CMOS technologies and feasibility research of future CMOS processes for analog circuits. Since June 1 2000 he is with the IC-Design group in the department of Electrical Engineering at the University of Twente, Enschede, The Netherlands where the research focus still is in physics, analog and mixed-signal electronics, and deep-submicrometer technologies and their joint feasibility aspects. This spans research from switched mode RF power amplifiers, reference circuits, (ultra) low power circuits, optical functionality on CMOS and other circuits and systems combining physics, mathematics and electronics. A number of these research projects are done with or for industrial partners. He is also part-time consultant in industry and in 2001 he co-founded ChipDesignWorks. Anne-Johan is the recipient of a number of educational awards. From 2017 to 2020 he was program director Electrical Engineering at the University of Twente; he chairs the faculty and UT scholarship committees.

Position Statement: Nowadays published ICs are becoming more complex by the day, with a publication focus that shifted from building block innovations to bare system level performance increase that is frequently due to leveraging Moore’s law. This is interesting from an industrial point-of-view as numbers and price-performance are key for sales and marketing. In academia, working towards better/smaller transistors and interconnects gets prohibitively expensive if proof-of-the-pudding needs to be done (and it has to be done!). In academia, working towards large systems is out of reach due to the sheer (non-research) workload required. Innovations in relevant building blocks, break through topology approaches, taking into account the (evolution in) semiconductor technologies and targeting more-than-state-of-the-art performance should be and should stay a focus of research at universities. Work in academia should not be art-for-art’s-sake work, but art-for-relevant goal’s-sake. This is where we should educate, teach, challenge and raise our future designers, and where we can do exploratory work that can provide useful and enabling building blocks and knowledge. This deserves a spot in the lime-lights at conferences, next to publications of complete and large systems.