CICC 2024 Forums
Monday, April 22
9:30 am-11:30 am
AI-based Chip/Chiplet Generation
Foundation of System Design
Session Chairs: Xinfei Guo, Shanghai Jiao Tong University, China and Siddharth Joshi, Univeristy of Notre Dame, USA
Artificial intelligence (AI) and machine learning (ML) are poised to transform multiple aspects of the semiconductor industry. This session explores how AI and ML models might revolutionize integrated circuit (IC) design, from generating hardware description code using natural language instructions to applying domain-adapted language models for real-world productivity gains. Experts will help separate out myth from reality, discussing the broad applications of AI across the entire chip design process, as well as how machine learning techniques are being used to optimize both digital and analog circuits.
Bio: Siddharth Garg is the Institute Associate Professor of ECE at NYU. He got his PhD from CMU in 2009. His research is at the intersections of hardware, AI and cybersecurity. He has received the NSF CAREER Award, the AG Jordan best thesis award from CMU and several best paper awards.
Title: From Quips to Chips: Leveraging LLMs for Microelectronics Design and Specification
Abstract: Hardware description language (HDL) programming is cumbersome and error-prone. Here, we will discuss how chips can be specified in natural languages like English (“quips”). This is a tantalizing possibility with the success of large language models (LLMs) in software code generation. We will describe VeriGen, the first LLM tailored for HDL code generation using a curated dataset of open-source Verilog. We will then describe the world’s first processor designed entirely via natural language instructions.
Bio: Haoxing Ren (Mark) serves as the Director of Design Automation Research at NVIDIA, where he focuses on leveraging machine learning and GPU-accelerated tools to enhance chip design quality and productivity. He earned his PhD from the University of Texas at Austin and is a Fellow of the IEEE.
Title: ChipNeMo: Domain-adapted LLMs for Chip Design
Abstract: We trained domain-adapted LLMs (ChipNeMo) with internal design documents and source code to improve industrial chip design productivity on three selected use cases: an engineering assistant chatbot, EDA script generation, and bug summarization and analysis. I will talk about domain adaptation techniques used in ChipNeMo. We find that domain adaptation is orthogonal to retrieval augmented generation (RAG). On the engineering assistant application, our best model achieved 20% higher performance than GPT-4 with RAG.
Bio: David Pan is the Silicon Labs Endowed Chair Professor at ECE Department, UT Austin. His research includes electronic design automation, synergistic AI and IC, and emerging technologies. He has published over 480 papers and graduated 52 PhD students/postdocs. He has received many awards, including 20 Best Paper Awards and SRC Technical Excellence Award. He is a Fellow of ACM, IEEE, and SPIE.
Title: AI for Chip Design:When, Where, and How?
Abstract: AI for chip design has received tremendous interests in recent years. It touches everything that chip designers care about, from power/performance/area (PPA) to cost/turn-around-time, among others. It is everywhere, in all levels of design abstractions from architecture to RTL to layouts, for digital, analog, mixed-signal, and even RF designs. In this talk, I will cover some recent advancement on when, where, and how AI can be used for chip design and share my perspectives.
Bio: Sachin S. Sapatnekar is the Henle Chair in ECE and Distinguished McKnight University Professor at the University of Minnesota. His research interests include design automation methods for analog and digital circuits, circuit reliability, and algorithms and architectures for machine learning. He is a Fellow of the IEEE and the ACM.
Title: How ML can improve digital and analog design
Abstract: Machine learning (ML) has opened new doors for increasing the efficiency of design – ranging from methods that traditionally require manual input from expert designers to techniques that perform fast analyses and optimizations. This talk will overview the application of ML to problems in electronic design automation, covering topics such as the analysis and optimization of digital and analog systems, and even in using ML to overcome the problem of limited data available for model training.
Monday, April 22
9:30 am-11:30 am
Cutting-edge Energy Harvesting Interface Circuits & Systems
Session Chairs: Hyun-Sik Kim, KAIST, South Korea & Inhee Lee, University of Pittsburgh, USA
This forum session focuses on cutting-edge energy-harvesting (EH) interface circuits and systems. We will explore circuit designs tailored for harvesting power from photovoltaic (PV), thermoelectric generators (TEG), and kinetic energy sources. Additionally, this session will address the integration of energy combiners for multi-source EH applications and advanced ultra-low-power management techniques crucial for batteryless EH systems.
Bio: Sijun Du received the B.Eng. degree in electrical engineering from the University Pierre and Marie Curie (UPMC), Paris, France, in 2011, the M.Sc. degree in electrical and electronics engineering from Imperial College, London, U.K., in 2012, and the Ph.D. degree in electrical engineering from the University of Cambridge, Cambridge, U.K., in January 2018. He was a Post-Doctoral Researcher with the Berkeley Wireless Research Center (BWRC), Department of Electrical Engineering and Computer Sciences (EECS), University of California at Berkeley, Berkeley, CA, USA, from 2018 to 2020. In 2020, he joined the Department of Microelectronics, Delft University of Technology (TU Delft), Delft, The Netherlands, where he is currently an Assistant Professor.
His current research is focused on energy-efficient integrated circuits and systems, including power management integrated circuits (PMIC), energy harvesting, wireless power transfer, and dc/dc converters used in the Internet-of-Things (IoT) wireless sensors, wearable electronics, biomedical devices, and microrobots.
Title: Efficient and Low-cost Kinetic Energy Harvesting: Review & Recent Progress
Abstract: Internet-of-Things is bridging the physical world and the cyber world by employing many ubiquitous wireless sensors. To power these sensors, conventional power solutions using batteries are impractical due to the impossible tasks of recharging or replacing these batteries for an enormous number of autonomous sensors. To address this, harvesting energy from the environment has become a promising solution to power these ubiquitous sensors. Due to the required power level and enormous number of these sensors, the efficiency and system cost are critical factors for commercialization and real-world applications. In this talk, recent developments in kinetic energy harvesting circuits are reviewed, with a focus on techniques to improve energy extraction performance for higher efficiencies, and reduce the number of off-chip components for lower system costs.
Bio: Joseph Sankman received the B.S. degree in electrical engineering from the University of Arizona, Tucson, AZ, USA, in 2010, and the Ph.D. degree in electrical engineering from The University of Texas at Dallas, Richardson, TX, USA, in 2014, where his research included energy harvesting circuits and systems and high-performance switch-mode power converters. He joined Texas Instruments in 2015, working on linear and switch-mode battery chargers. Until 2022, he worked on ultra-low power circuits in Kilby Labs, Dallas, TX, USA. He joined Analog Devices in 2022 to work on high-performance automotive switching converters. He is the coauthor of 20 peer-reviewed IEEE conferences and journals. Dr. Sankman was awarded U.S. National Science Foundation Graduate Research Fellowship as well as Texas Instruments/Semiconductor Research Corporation Graduate Fellowship in 2011. He received the Best in Session Award at SRC TECHCON in 2012 and 2013 for his work on piezoelectric energy harvesting.
Title: Advances in Energy Harvesters and Ultra-Low Power Circuits Towards Edge Computing
Abstract: In order for edge computing to proliferate, remote sensors require long lifetime, no maintenance, and low cost. These requirements are being met by advances in energy harvesters, which assist in reducing battery size (or eliminating the battery) while extending lifetime, which enables smaller solution size, and cost-effective, maintenance-free operation. Concurrently, advances have been made in ultra-low power circuits for remote sensor systems, including nanopower LDOs and switches. This talk will cover recent developments and trends in energy harvesting and ultra-low power circuits. State-of-the-art techniques and techniques will be discussed as well as future trends.
Bio: Ping-Hsuan Hsieh received the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 2001, and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Los Angeles, Los Angeles, CA, in 2004 and 2009, respectively. From 2009 to 2011, she was with the IBM T.J. Watson Research Center, Yorktown Heights, NY. In 2011 she joined the Electrical Engineering Department of National Tsing Hua University, Hsinchu, Taiwan, where she is currently an Associate Professor. Her research interests focus on mixed-signal integrated circuit designs for high-speed electrical data communications, clocking and synchronization systems, and energy-harvesting systems.
Prof. Hsieh served in the Technical Program Committee of the IEEE International Solid-State Circuits Conference, and is currently a member of the Technical Program Committees of the IEEE Asian Solid-State Circuits Conference and the IEEE Custom Integrated Circuits Conference. She served as an Associate Editor for the IEEE INTERNET OF THINGS JOURNAL from 2014 to 2018, a Guest Editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS Special Issue in 2021, and is currently an Associate Editor for the IEEE OPEN JOURNAL OF CIRCUITS AND SYSTEMS and IEEE SOLID-STATE CIRCUITS LETTERS.
Title: Recent Developments in Interface Circuits for Piezoelectric Energy Harvesting
Abstract: Piezoelectric vibration-to-electricity conversion provides a feasible solution to self-sustainability due to its relatively high power density, wider voltage range, and the compatibility with IC technology. The drastic difference between the operating speed of integrated circuits and mechanical vibrations provides a perfect venue for performing nonlinear switching and control in the interface operation with low power, allowing orders of magnitude of improvement in power extracting ability. In this talk, an overview of the current state-of-the-art interface designs for piezoelectric energy harvesting will be presented and some of the remaining challenges will be discussed.
Bio: Po-Hung Chen received the M.S. degree from the Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, in 2007, and the Ph.D. degree in electrical engineering from The University of Tokyo, Tokyo, Japan, in 2012.
In 2011, he was a Visiting Scholar with the University of California at Berkeley, Berkeley, CA, USA, where he conducted research in fully integrated power management circuits for RISC-V processors. He is currently a Professor with the Institute of Electronics, National Yang Ming Chiao Tung University. His research focuses on power management integrated circuits, with a special emphasis on energy harvesting, battery management, battery charger, and wireless power transmission.
Title: Multi-source Energy Harvesting Integrated Circuit for Battery-free IoT Devices
Abstract: This talk introduces a cutting-edge multi-source energy harvesting integrated circuit for battery-free IoT devices. It covers the consideration in the circuit design for a single-inductor multi-source multi-output converter, with particular emphasis on efficient methodologies for extracting energy from diverse transducers. The introduction of adaptive peak-inductor-current control is highlighted as a means to manage output voltage ripple, enhancing converter efficiency over wide input and output voltage range.
Wednesday, April 24
1:45 pm-3:45 pm
Wireless Transceivers Towards Next G
Wireless Transceivers and RF/mm-Wave Circuits and Systems
Session Chairs: Taiyun Chi, Rice University, USA & Hamidreza Aghasi, University of California Irvine, USA
Five experts from academia and industry will share their visions for next-G wireless communications and sensing, delving into circuits and systems design in the emerging FR3 frequency band (7-24 GHz) and D-band (140 GHz). Attendees can anticipate enlightening discussions on the forefront of next-G wireless transceiver innovations.
Bio: Jeff Walling received his BS from University of South Florida and his MS and PhD from University of Washington, all in Electrical Engineering. He has held industrial positions at Motorola, Intel, Qualcomm and Skyworks. He is now an associate professor at Virginia Tech.
Title: Mixed-Signal Transceivers, Flexible for Future FR3 Frequencies
Abstract: It is anticipated that the spectrum between 7 and 24 GHz will play a key role in next generation wireless communications systems. However, it is unlikely that contiguous spectrum will be available due to entrenched legacy operators with costly infrastructure. RF-DACs and -ADCs are versatile and can provide a framework for efficient and flexible operation in this spectrum. In this talk, I will present several solutions that can be leveraged for operation in this contentious spectrum.
Bio: Zhiwei Xu received his Ph.D. degree from the University of California, Los Angeles. He has held industry positions with SST Communications, Conexant Systems, and NXP Semiconductors, leading development for wireless LAN, CMOS cellular transceiver, Multimedia over Cable (MoCA) system and TV tuners. He is currently a professor with Zhejiang University, researching on integrated circuits and systems for Internet-of-Things and communication applications.
Title: Design of Integrated Multibeam Phased-Array Chip
Abstract: Multibeam phased-array can be used for high-throughput wireless communications and joint sensing and communication applications. In this talk, beamformers supporting multiple co-aperture simultaneously reconfigurable beams will be introduced, which covers architecture and circuit design of the phased-array chip, as well as isolation challenges and array scalability. In addition, several interesting features of the multibeam phased-array chip will also be discussed.
Bio: Anirudh Kankuppe received M.Sc. in Microelectronics from TU Hamburg, Germany. He was a Design Engineer with Cadence, India from 2012 to 2014. His Ph.D. research was on mm-wave circuits with VUB and imec, Belgium where he currently works as a researcher with focus on mm-wave radar, receivers, and wireline ADCs.
Title: Integrated Wireless Communication and Radar Transceivers in the D-band
Abstract: This talk will focus on wireless communication and radar operating in the D-band. We will present 28nm CMOS chips for high-resolution FMCW radar and a 22nm FD-SOI front-end module chip for high-data-rate wireless communication. In addition, a projection is made to augment CMOS functionality with InP chips in order to generate more transmit power with a higher efficiency than a CMOS-only implementation. Finally, some aspects of heterogeneous integration of CMOS and InP with antennas are discussed.
Bio: José Luis González Jiménez is a fellow and research director at CEA-Leti in Grenoble, France, and an invited lecturer at Unviersité Grenoble-Alpes. He is leading mmW IC design activities at the systems integration Laboratory. His research interests include mmW and subTHz circuits and systems for communications, radar, and other applications.
Title: High-Speed D-band Point-to-Point Communications with High-Gain Antennas
Abstract: In this talk, the recent works developed at CEA-Leti based on CMOS multi-channel transceivers and high-gain transmit array antennas for high-data rate point-to-point links will be presented. A channel aggregation approach has been selected in order to attain a good trade-off between large RF bandwidth and reasonable digital baseband interfaces sampling frequency. High-gain electromagnetic lenses based on transmit arrays are used to compensate for the large path loss at D-band.
Bio: Wooram Lee is an Associate Professor in the Department of Electrical Engineering at Penn State University, USA. From 2015 to 2020, he was a Research Staff Member at the IBM T. J. Watson Research Center, where he was involved with the development of high-performance mmWave phased array circuits and systems.
Title: RFIC design innovation for silicon-based D-band phased arrays
Abstract: D-band spectrum has attracted considerable interest to accommodate the explosive growth in wireless data capacity and emerging sensing applications. To overcome severe path loss and limited transistor performance at such high frequencies, the use of a large-scale phased array transceiver is essential. I will present RFIC design innovations to accelerate the development of a D-band phased array, including a passive phase shifter for calibration-free, precise phase control, a compact and low-power phased array transceiver, and low-noise bidirectional amplifier.
Wednesday, April 24
1:45 pm-3:45 pm
Circuits and Packaging Techniques for Next-gen Wireline Communications
Wireline and Optical Communications Circuits and Systems
Session Chairs: Shenggao (Victor) Li, TSMC, USA & Henry Park, MediaTek, USA
Bio: Jeff Tsai is a department manager in TSMC’s Design-Technology-Platform organization in Hsinchu, Taiwan, where he leads the team responsible for advance connectivity solutions. In 2009 to 2019, he led the team to develop SerDes with speed up to 112Gbps. In 2015 to 2022, his team gradually moves to chiplet interconnect design to enable TSMC 3DFabric technologies. In past years, he has more than 8 VLSI/CICC/JSSC/Hot-chip papers in SerDes and chiplet interconnect domains
Title: High-speed Interconnects for 2.5D/3D Advance Packages
Abstract: System-in-Package solutions, where multiple chiplets are integrated by 2.5D/3D package technologies, have become more and more popular. To be economically viable, they require carefully co-optimizing system demand and package technology as well as the interconnects that enable communication between chiplets. This forum talk covers advanced package technologies and new capabilities they enabled. Circuit techniques used for 2.5D and 3D stacking will be introduced, including mitigation of inter-symbol-interferences, cross-chiplet timing closure, shielding against crosstalks, and integrity of power delivery networks.
Bio: Hyo Gyuem Rhew has been with Samsung since 2020, where he is the Vice President of SerDes and Security Solution group. Hyo Gyuem Rhew received the B.S. degree (summa cum laude) from Seoul National University, Seoul, Korea, in 2006, and the M.S. and Ph.D. degrees from University of Michigan, Ann Arbor, MI, in 2009 and 2012, respectively, all in electrical engineering. From 2012 to 2020, he was with Broadcom, Irvine, CA, USA, where he built various types of high-speed wireline transceivers. His research interests include high-speed wireline transceiver designs for copper, optical, backplane, and die-to-die applications, and high-speed data converters. Dr. Rhew currently serves in the technical program committee of IEEE ISSCC.
Title: Advancements in D2D Interface Technologies: Paving the Way for the New Era of System Integration
Abstract: Various die-to-die (D2D) interface standards have emerged to suffice ever-increasing demand for system performance as well as yield and development cost even as the pace of technology scaling has slowed down. Recently the industry has established a few promising standard specifications for D2D interfaces including Universal Chiplet Interconnect Express (UCIe) and other candidates. High-Bandwidth Memory (HBM) is another break-through technology to keep up with the escalating performance requirements from high-performance computing (HPC) and artificial intelligence (AI) systems. In this talk, I will discuss the recent trends in the development of D2D standards and HBM interfaces, and the recently published D2D and HBM interface design works from my group.
Bio: Jeff Hutchins works in the CTO’s Office at RANOVUS focused on next-generation energy efficient optical interconnect solutions utilizing silicon photonics. He is the OIF’s vice chair of the Energy Efficient Interfaces track at the OIF as well as a board member and has led a variety of standards efforts.
Title: Development of a co-packaged Application Specific IC with optical engine chiplets
Abstract: The development of a co-packaged Application Specific IC consisting of an ASIC interfaced with eight 8x 100G optical engine chiplets is presented. The design methodology and important design tradeoffs are covered. Finally, a promising approach towards a generalized non-linear optical engine modeling is proposed which could enable co-simulation for an optical chiplet eco-system.
Bio: Samuel Palermo received the Ph.D. degree in electrical engineering from Stanford University. In 2009, he joined the Electrical and Computer Engineering Department of Texas A&M University where he is currently a professor. His research interests include high-speed electrical and optical interconnect architectures, RF photonics, and high performance clocking circuits.
Title: Multi-Carrier ADC/DAC-Based Wireline Transceiver Architectures
Abstract: This talk provides an overview of a jitter-robust ADC/DAC-based multi-carrier transceiver architecture. Details of a receiver that supports multi-carrier signaling with three bands of baseband PAM4 and mid-band and high-band QAM16 modulation on orthogonal carriers will be presented. This is followed by discussion on a multi-carrier DAC-based transmitter that utilizes parallel baseband and polar mid-band and high-band output drivers. The talk concludes with performance comparisons with other DMT and conventional PAM-based signaling approaches.
Bio: Jens Muellrich received the Ph.D. degree in electrical engineering from the Ruhr-University in Bochum, Germany, in 2002. He worked with Multilink Technology, Micram Microlelectronic, and Keysight Technologies as circuit designer and project manager. His focus of work are mixed-signal circuits for ultra-high speed, utilizing the fastest SiGe BiCMOS technologies.
Title: Pushing Limits of Arbitrary Waveform Generation: Insights into the Custom Power behind Ultra-High-Speed AWGs
Abstract: To innovate next-generation transmission technologies, advanced research engineers rely on ever increasing levels of stimulus performance. Whether stress-testing subcomponents of (coherent) optical systems or experimenting with Terabit transmission, achieving highest speed, bandwidth, precision, and flexibility is critical. This presentation will highlight various technologies developed to realize today’s most advanced signal generation with 8-bit nominal resolution, 256 GSa/s sample rate and greater than 80 GHz usable bandwidth.