Educational Sessions

2023 CICC Educational Sessions

Educational Sessions

CICC 2023 Educational Sessions


Sunday, April 23


Educational Session 1: Crystal-Less Timing/Frequency References

Session Chairs: Mark Oude Alink, University of Twente, Netherlands and Wanghua Wu, Samsung, USA


Title: Integrated BAW-Based Frequency References

Abstract: Nearly all electronic systems require a clock. Crystal oscillators have been the most common way to generate an accurate reference frequency for the last 100 years. Despite their ubiquity, crystal oscillators have several drawbacks, including cost, large size, degraded
frequency stability at temperature extremes, and sensitivity to shock and vibration. Bulk acoustic wave resonators (BAW) have emerged as an alternative to crystals, allowing a reduction in the footprint of electronic systems and enabling exciting new applications. This presentation covers
several aspects of designing with BAW resonators, including oscillator topologies, frequency tunability and stability, and passive and active temperature compensation. System level advantages such as fast startup, higher frequency, and improved robustness will also be
discussed. The article concludes with an introduction to applications for BAW that extend beyond frequency references.

Danielle Griffith, Fellow, Texas Instruments, Dallas, TX, USA

Bio: Danielle Griffith has 25 years of experience in the semiconductor industry. She is a Fellow at Texas Instruments in Dallas, Texas, responsible for system architecture of next generation low power wireless connectivity SoCs. Her current focus areas are circuits and architectures for efficient wireless systems, low power oscillators, and MEMS circuitry. She has published a book chapter and >50 papers and holds 20 issued US patents. Danielle has given numerous conference tutorials and workshop sessions. She has been a TPC member for top IEEE conferences, including RFIC, ISSCC, and VLSI. She is a senior member of the IEEE, an associate editor of the IEEE JSSC, and a Distinguished Lecturer of the SSCS. Danielle Griffith received the Bachelors and Masters degrees in electrical engineering from the Massachusetts Institute of Technology.




Title: MEMS for High-Performance Environmentally Robust Frequency References


Abstract: MEMS-based frequency references have demonstrated remarkable advances over the last two decades in various aspects of performances and features, making them leading contenders for many applications including mobile, high-performance networking and RF, computing, aerospace, and automotive. This talk reviews device architectures that leverages small size and tight integration of MEMS resonators with CMOS chips for a new class of frequency references, including small size uW oscillators and TCXOs, oscillators with sub-100fs phase jitter, ±10ppb super-TCXOs, and miniaturized OCXOs. Other features of MEMS-based devices are their excellent ability to operate in harsh environmental conditions, including fast thermal transients and extreme mechanical shock and vibration conditions. Some recent performance data for such devices will also be shared.

Sassan Tabatabaei, Senior VP Circuits Engineering, SiTime, Sunnyvale, CA, USA

Bio: Sassan Tabatabaei joined SiTime in 2008. His current position is Senior VP of Circuits Engineering. He defined, architected, and contributed to the development of several generations of market leading SiTime products including nW and uW mobile oscillator devices, low jitter frequency references and clock generators, and precision TCXO and OCXO devices using SiTime’s highly differentiated MEMS resonators. Prior to SiTime, he held various technical executive and management positions at instrumentation and Silicon IP companies, focused on measurements, on-chip test structures and instrument design for timing and signal integrity. He holds more than 30 US patents in these areas. He received his Ph.D. in Electrical Engineering from the University of British Columbia, Vancouver, Canada, in 2000.



Title: LC-Based Frequency References in CMOS

Abstract:Frequency references are essential building blocks for many electronic systems for timing and synchronization purposes. The accuracy of frequency references must be high enough — over Process, Voltage, Temperature (PVT) variations and lifetime (PVTL) — to allow other subsystems, e.g. transmitters or analog-to-digital converters (ADCs), to reach specific performance levels. In general, higher accuracy levels allow for better system performance. To reach demanding accuracy levels, it is common in the industry to use crystal oscillators (XOs), that utilize bulky external resonators that cannot be integrated in a CMOS die. Fully integrated frequency references in standard CMOS technologies are mainly RC-based (relaxation or harmonic) oscillators and LC-based (harmonic) oscillators. LC oscillators are widely used to generate (relatively) high quality oscillation signals, in CMOS technologies. This talk starts from the very basics of LC oscillators, leading to many types of LC-oscillators that have quite similar performance when assuming ideal components. After this, the impact of a plethora of non-idealities on LC-oscillators’ performance is reviewed. These include short term effects such as thermal noise, long term effects such as temperature dependencies, ageing and systematic effects such as the impact of non-linearities and gain stage phase shifts. It will be shows that now the various different LC-oscillator implementations fundamentally display different behavior. The talk concludes with forward compensation techniques to achieve single trimmed PVTL stable frequency references.



Anne-Johan Annema, Professor at University of Twente, Enschede, Netherlands

Bio: Anne-Johan Annema received the MSc. and PhD degrees in electrical engineering from the University of Twente, Enschede, The Netherlands, in 1990 and 1994, respectively. In 1995, he joined the Semiconductor Device Architecture Department of Philips Research in Eindhoven, The Netherlands, where he worked on a number of physics-electronics-related projects. In 1997, he joined the Mixed-Signal Circuits and Systems Department at Philips NatLab, where he worked on a number of electronics-physics-related projects ranging from low-power low-voltage circuits, fundamental limits on analog circuits in conjunction with process technologies, high-voltage in baseline CMOS to feasibility research of future CMOS processes for analog circuits. His research interest is in physics, analog and mixed-signal electronics, and deep-submicrometer technologies and their joint feasibility aspects. This spans research from switched mode RF power amplifiers, reference circuits, (ultra) low power circuits, optical functionality on CMOS and other circuits and systems combining physics, mathematics and electronics. Since June 1 2000 he is with the IC-Design group in the department of Electrical Engineering at the University of Twente, Enschede, The Netherlands. He is also part-time consultant in industry and in 2001 he co-founded ChipDesignWorks. Anne-Johan holds 14 patents in circuit design and is the recipient of a number of educational awards. From 2017 to 2020 he was also program director Electrical Engineering.

Title: RC Frequency References in Standard CMOS


Fully-integrated frequency references are one of the last missing pieces in realizing complete SoCs, alleviating the need for bulky external components or additional processing & packaging steps for timing needs. However, in the confines of an integrated circuit process, realizing a time constant with high enough accuracy to replace a crystal or MEMS device proves to be a significant challenge. RC frequency references, in particular, are limited by the large and nonlinear temperature coefficients of integrated resistors. Moreover, additional inaccuracies introduced through traditional oscillator architectures require trimming and temperature compensation. Trying to address these with conventional compensation methods that generally correct only the first-order temperature coefficients results in residual inaccuracies of > ±1000 ppm. This talk will review the RC frequency reference design trends with a survey of relevant publications in the last 20 years, with state-of-the-art RC frequency reference designs breaking the ±1000 ppm level as the primary focus. The basics of closed-loop frequency-locked architectures will be introduced, and higher-order digital temperature compensation methods that achieve better than ±250 ppm inaccuracy will be presented.

Çağrı Gürleyük, Senior Member of Technical Staff, Ethernovia, Zeist, Netherlands

Bio: Çağrı Gürleyük received his B.Sc. and M.Sc. degrees from Istanbul Technical University, Turkey, in 2011 and 2015, respectively. From 2014 to 2016, he was a design engineer at Analog Devices, Istanbul, Turkey. Since 2016, he has been pursuing a Ph.D. degree at the Delft University of Technology, The Netherlands. His research focus has been fully integrated RC frequency references, generating several state-of-the-art journal and conference publications. Since 2020, he has been with Ethernovia as a Senior Member of Technical Staff in Zeist, The Netherlands, working on timing challenges of the next generation of automotive multi-gigabit ethernet.





Educational Session 2: Emerging Devices and Systems for Storage and Computing

Session Chairs: Jongseok Park, Apple Inc, USA, Jerald Yoo, National University of Singapore

Title: From in-memory computing to analog and neuromorphic computing: augmenting CMOS with emerging memory devices for greater efficiency and capabilities

Abstract: Simultaneously today, there is interest in building more efficient computing hardware for data-heavy workloads (AI, machine learning, graph analytics, etc.), as well as a drive to overhaul the von Neumann architecture toward more brain-like architectures. I will attempt to cover these two topics, with the theme that both goals center around revamping today’s memory systems. The development of emerging memory technologies, such as the so-called memristor, offers some enabling opportunities here. Memristors can improve storage density and performance, adding to the existing memory hierarchy. Beyond this, computing architectures built around novel paradigms such as in-memory, analog, or neuromorphic computing will benefit from emerging devices that can couple memory and computing operations, sometimes trading off precision for faster speed and lower energy. Topics to be covered in this session include: emerging technologies for memory systems, in-memory computing concepts, accelerator architectures for Machine Learning and A.I., mixed analog-digital circuits and systems, new memory circuits, error-correction, and a variety of computing applications.


John Paul Strachan, Aachen University, Germany

Bio: John Paul Strachan is Director of the Peter Grünberg Institute on Neuromorphic Compute Nodes (PGI-14) at Forschungszentrum Jülich and Professor at RWTH Aachen.  Previously he led the Emerging Accelerators team as a Distinguished Technologist at Hewlett Packard Labs, HPE. His institute develops novel types of hardware accelerators using emerging device technologies, with activities across circuits, architectures, materials, device physics, benchmarking and building prototype systems. Applications span machine learning, network security, and optimization. John Paul has degrees in physics and electrical engineering from MIT and a PhD in applied physics from Stanford University. He has over 50 patents and has authored or co-authored over 90 peer-reviewed papers.  He has previously worked on nanomagnetic devices for memory for which he was awarded the Falicov Award from the American Vacuum Society, and has developed sensing systems for precision agriculture in a company which he co-founded. He serves in professional societies including IEEE IEDM ExComm, the Nanotechnology Council ExComm, editorial board member for Chip, technical committee member for IEEE EDS Neuromorphic Computing, AICAS, ICRC, and IRPS.



Title: In-memory Computing: Is this a good solution for you?

Abstract: There is growing interest in processing a large volume of data from sensor-rich platforms by exploiting AI algorithms. However, traditional von Neumann architectures suffer from explicit separation between memory and computation (the “Memory Wall”), which imposes bottlenecks on the energy efficiency and throughput. An in-memory computing platform has emerged as a potential solution to address this grand challenge leading to extensive effort in both academia and industry for almost a decade. In this talk, we revisit the principle of in-memory computing technique, and study the recent trend of circuit and architecture. Both its benefit and disadvantage will be discussed in different applications through a clear comparison with the conventional AI architecture. Finally, future research directions in this domain will be discussed spanning device, circuit, architecture, algorithm, and applications to push the boundary of in-memory computing.


Mingku Kang, University of California San Diego, USA

Bio: Dr. Mingu Kang is an assistant professor of the Electrical and Computer Engineering (ECE) at the UC San Diego Jacobs School of Engineering. He received the Ph.D. degree in Electrical and Computer Engineering from the University of Illinois at Urbana–Champaign, Champaign, IL, USA, in 2017, and the B.S. and M.S. degrees in Electrical and Electronic Engineering from Yonsei University, Seoul, South Korea, in 2007 and 2009, respectively. From 2017 to 2020, He was a research staff member of the IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA, where he designs machine learning accelerator architecture, which was successfully commercialized by being embedded on IBM Z-mainframe server. From 2009 to 2012, he was with the Memory Division, Samsung Electronics, Hwaseong, South Korea, where he was involved in the circuit and architecture design of phase change memory (PRAM) for the commercialization. He is a recipient of Intel 2022 Rising Star Award, UIUC CSL best thesis award in 2018, MICRO TOP Pick Honorable Mention 2019, IEEE International Symposium on Circuits and Systems (ISCAS) “Neural System and Application” Best Paper Awards in 2016 and 2018.




Title: Memory-Centric Computing

Abstract: Computing is bottlenecked by data. Large amounts of application data overwhelm storage capability, communication capability, and computation capability of the modern machines we design today. As a result, many key applications’ performance, efficiency, and scalability are bottlenecked by data movement. In this lecture, we describe three major shortcomings of modern architectures in terms of 1) dealing with data, 2) taking advantage of the vast amounts of data, and 3) exploiting different semantic properties of application data. We argue that an intelligent architecture should be designed to handle data well. We show that handling data well requires designing architectures based on three key principles: 1) data-centric, 2) data-driven, 3) data-aware. We give several examples for how to exploit each of these principles to design a much more efficient and high-performance computing system. We especially discuss recent research that aims to fundamentally reduce memory latency and energy, and practically enable computation close to data, with at least two promising novels directions: 1) processing using memory, which exploits analog operational properties of memory chips to perform massively-parallel operations in memory, with low-cost changes, 2) processing near memory, which integrates sophisticated additional processing capability in memory controllers, the logic layer of 3D-stacked memory technologies, or memory chips to enable high memory bandwidth and low memory latency to near-memory logic. We show both types of architectures can enable orders of magnitude improvements in performance and energy consumption of many important workloads, such as graph analytics, database systems, machine learning, video processing. We discuss how to enable adoption of such fundamentally more intelligent architectures, which we believe are key to efficiency, performance, and sustainability. We conclude with some guiding principles for future computing architecture and system designs.

 Onur Mutlu, ETH Zurich, Switzerland

Bio: Onur Mutlu is a Professor of Computer Science at ETH Zurich. He is also a faculty member at Carnegie Mellon University, where he previously held the Strecker Early Career Professorship.  His current broader research interests are in computer architecture, systems, hardware security, and bioinformatics. A variety of techniques he, along with his group and collaborators, has invented over the years have influenced industry and have been employed in commercial microprocessors and memory/storage systems. He obtained his PhD and MS in ECE from the University of Texas at Austin and BS degrees in Computer Engineering and Psychology from the University of Michigan, Ann Arbor. He started the Computer Architecture Group at Microsoft Research (2006-2009), and held various product and research positions at Intel Corporation, Advanced Micro Devices, VMware, and Google.  He received the Intel Outstanding Researcher Award, IEEE High Performance Computer Architecture Test of Time Award, NVMW Persistent Impact Prize, the IEEE Computer Society Edward J. McCluskey Technical Achievement Award, ACM SIGARCH Maurice Wilkes Award, the inaugural IEEE Computer Society Young Computer Architect Award, the inaugural Intel Early Career Faculty Award, US National Science Foundation CAREER Award, Carnegie Mellon University Ladd Research Award, faculty partnership awards from various companies, and a healthy number of best paper or “Top Pick” paper recognitions at various computer systems, architecture, and security venues. He is an ACM Fellow “for contributions to computer architecture research, especially in memory systems”, IEEE Fellow for “contributions to computer architecture research and practice”, and an elected member of the Academy of Europe (Academia Europaea).



Title: Computing with p-Bits: Between a Bit and a q-Bit

Abstract: Digital computing is based on a deterministic bit with two values, 0 and 1. On the other hand, quantum computing is based on a q-bit which is a delicate superposition of 0 and 1. This talk is about something in-between namely, a p-bit which is a robust classical entity fluctuating between 0 and 1.

Feynman used the concept of a probabilistic computer as a counterpoint to the quantum computer, noting that “ .. the only difference between a probabilistic classical world and the equations of the quantum world is that .. the probabilities would have  to go negative .. ” The power of quantum computing comes from exploiting these negative (more generally complex) probabilities, which in turn requires stringent experimental conditions to protect the phase.

A probabilistic computer by contrast can be built with existing technology to operate at room temperature as we have demonstrated experimentally using unstable magnetic tunnel junctions. They lack the magic of complex probabilities but can function as hardware accelerators for many applications that use stochastic algorithms. Benchmarking examples will be presented showing 2-3 orders of magnitude acceleration using a specially designed digital probabilistic processor, and a further 2 − 3 orders of magnitude by mapping it to a clockless analog processor.


Supriyo Datta, Purdue University, USA

Bio: Supriyo Datta received his PhD from University of Illinois at Urbana-Champaign in 1979 working on surface acoustic wave devices, and has been with Purdue University since 1981. The non-equilibrium Green function (NEGF) method pioneered by his group provides the basis for the quantum simulation tools used in the semiconductor industry to design nano transistors. He was elected to the US National Academy of Engineering (NAE) for this work. His innovative theoretical proposals have inspired new fields of research including spintronics, negative capacitance electronics and most recently the concept of probabilistic bits, or p-bits. He is also known for his books and online courses designed to disseminate his research to a broad audience.





Educational Session 3: Wearable and Implantable Sensors

Session Chairs: Yaoyao Jia, University of Texas, Austin, USA and Chul Kim, KAIST, South Korea


Title: E-Tattoos – Materials, Design, Manufacturing, Functionalities, and Applications


Abstract: E-tattoos are a type of wearable technology that use flexible and stretchable electronics to conform to the soft, deformable and curvilinear surface of human skin. They can be hair-thin, skin-soft, and noninvasive, making them a promising alternative to traditional wearables like smartwatches and smart rings. Compared with traditional wearables, e-tattoos feature distributed and multimodal sensing over a human body, reduced motion artifacts, as well as imperceptible and/or long-term wear. This tutorial will cover the materials, design, manufacturing, and functionalities of emerging e-tattoos. It will also showcase their potential applications in telemedicine, mobile health, human-robot interactions and even fashion. Existing challenges and future directions will be discussed at the end. Attendees are encouraged to ask questions and share their ideas during the presentation.


Nanshu Lu, The University of Texas, Austin, USA

Biography: Dr. Nanshu Lu is Frank and Kay Reese Professor at the University of Texas at Austin. She received her B.Eng. with honors from Tsinghua University, Beijing, Ph.D. from Harvard University, and Beckman Postdoctoral Fellowship from UIUC. Her research concerns the mechanics, materials, manufacture, and human or robot integration of soft electronics. She is an ASME fellow, an IEEE Senior Member, and a Clarivate (Web of Science) highly cited researcher. She is currently an Associate Editor of Nano Letters and Journal of Applied Mechanics. She has been named MIT TR 35 and iCANX/ACS Nano Rising Star. She has received NSF CAREER Award, ONR and AFOSR Young Investigator Awards, 3M non-tenured faculty award, and the ASME Thomas J.R. Hughes Young Investigator Award. She has been selected as one of the five great innovators on campus and five world-changing women at UT-Austin.



Title: Brain Interface: High-Density Electrical Recording and Optical Modulation at Cellular Resolution


Abstract: In this talk, the evolution of Michigan neural probe technologies will be reviewed toward scaling up the number of recording sites and adding selective neural modulation capability to enable optogenetic control of neurons at cellular resolution. Modular system integration and compact 3D packaging approaches will be introduced for realizing high-density neural probe arrays for recording as well as modulating neurons at cellular resolution. Low-power circuit implementation with high area efficiency will be presented for recording of more than 1,000 channels simultaneously. Dynamic power reduction scheme will be introduced for high-density neural recording systems. Lossless compression can be achieved from spatial-temporal correlation between the local field potential (LFP) and spike signals. A Δ-modulated ΔΣ analog-to-digital converter (Δ-ΔΣ ADC) architecture can effectively reduce the dynamic range from a dedicated digital difference circuit. Statistical redundancy is further eliminated through entropy encoding without information loss. For spikes, only the essential waveforms of spikes can be extracted from the raw data by using spike detectors and reconfigurable analog memories. As for optical neuromodulation, a number of recent approaches in optogenetic probe technologies will be introduced. Among these, micro-LED optoelectrodes are promising for scaling of the number of optical modulation sites. Multiple neuro-size micro-LEDs (~10 μm) can be directly integrated on a probe shank to achieve high spatial temporal modulation of neural circuits. It was demonstrated that independent control of distinct neuron cells ~50 μm apart in the CA1 pyramidal layer of anesthetized and freely-moving mice at 60 nW light power. Recently, the number of optical stimulation sites has scaled by integrating 128 micro-LEDs along with 256 recording sites, dubbed as hectoSTAR micro-LED optoelectrode. The circuit challenges and miniaturization of system assembly will be extensively discussed along with projection of future direction in neuro-interface technologies.


Sung-Yun Park Associate Professor, Dept. of Electronics Engineering, Pusan National University, Adjunct Research Scientist, Dept. of Electrical Engineering and Computer Science, University of Michigan, USA


Bio: Sung-Yun Park received his B.S. in Electrical Engineering from Pusan National University, Busan, Korea in 2005, and his M.S. in Electrical Engineering from Korean Advanced Institute of Science and Technology (KAIST), Daejeon, Korea in 2008, where he was involved in photonics device research. From 2008 to 2010, he worked for the Fairchild Semiconductor, Bucheon, Korea, as a Member of Technical Staff for high voltage mixed signal circuit design. He continued his study in integrated circuits in Cornell University, Ithaca, NY and received the M. Eng. in Electrical and Computer Engineering in 2011, and his Ph.D. in Electrical Engineering at the University of Michigan in 2016. From 2016 to 2018, he was a research fellow, and from 2018 he was an assistant research scientist at the University of Michigan. In 2019, he joined the Department of Electronics Engineering at the Pusan National University where he is currently an associate professor. His current research interests are in low power, low noise mixed-signal integrated circuits and power management circuits for biomedical and sensor systems.



Euisik Yoon, Professor, Dept. of Electrical Engineering and Computer Science, Professor, Dept. of Biomedical Engineering, Professor, Dept. of Mechanical Engineering, Director, NSF International Program for Advancement of Neurotechnology, University of Michigan, USA


Bio: Euisik Yoon received the B.S. and M.S. degrees in electronics engineering from Seoul National University and the Ph.D. degree in electrical engineering from the University of Michigan, Ann Arbor, in 1990.

He worked for industry including the National Semiconductor Corp. in Santa Clara, CA and Silicon Graphics Inc. in Mountain View, CA before returning to academia (1990-1996). He took faculty positions at Korea Advanced Institute of Science and Technology (KAIST) in Daejon, Korea and the University of Minnesota, Minneapolis, MN, respectively. In 2008, he joined the University of Michigan, Ann Arbor, MI, where he is a Professor and the Director of NSF International Program for the Advancement of Neurotechnology (IPAN). He served as the Director of Solid-State Electronics Laboratory (2011-2015) and the Director of Lurie Nanofabrication Facility (2011-2016) at the University of Michigan.

Dr. Yoon has served on various Technical Program Committees including the IEEE International Electron Device Meeting (IEDM) (2006-2008) and the IEEE International Conference on Micro Electro Mechanical Systems (MEMS) (2006, 2008-2010, 2021). He also served on the IEEE International Solid-State Circuit Conference (ISSCC) program committee (2003-2007) and organized and co-chaired the International Conference for Advanced Neurotechnology (ICAN) (2016-2020). He served as an associate editor for IEEE Solid-State Circuit Letters (2018-2021).



Title: Skin-Interfaced Wearable Biosensors

Abstract: The rising research interest in personalized medicine promises to revolutionize traditional medical practices. This presents a tremendous opportunity for developing wearable devices toward predictive analytics and treatment. In this talk, I will introduce recent advances in developing wearable biosensors for non-invasive molecular analysis. Such wearables can autonomously access sweat across activities and continuously measure a broad spectrum of analytes including metabolites, nutrients, hormones, and drugs. Laser-engraving and inkjet printing are used to manufacture these nanomaterials-based biosensors at large scale and low cost. The clinical value of these wearable systems is evaluated through human studies toward metabolic & nutritional monitoring, disease diagnosis, mental health assessment, and drug personalization. I will also discuss the research progress onenergy harvesting from the body fluids and human motion to realize battery-free wireless wearable biosensing. These wearable technologies could open the door to a wide range of personalized monitoring, diagnostic, and therapeutic applications.


Wei Gao, California Institute of Technology, USA

Bio: Wei Gao is an Assistant Professor of Medical Engineering, Ronald and JoAnne Willens Scholar, and Heritage Medical Research Institute Investigator at the California Institute of Technology. He received his Ph.D. in Chemical Engineering at University of California, San Diego in 2014. In 2014–2017, he was a postdoctoral fellow in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley. He is an Associate Editor of Science Advances. He is a recipient of IAMBE Early Career Award, NSF Career Award, Pittsburgh Conference Achievement Award, ONR Young Investigator Award, Sloan Research Fellowship, IEEE EMBS Early Career Achievement Award, IEEE Sensor Council Technical Achievement Award, 3M Non-Tenured Faculty Award, MIT Technology Review 35 Innovators Under 35, and ACS DIC Young Investigator Award. He is a World Economic Forum Young Scientist, a member of Global Young Academy, and a Highly Cited Researcher (Web of Science). His research interests include wearable devices, biosensors, flexible electronics, micro/nanorobotics, and nanomedicine.


Title: Near-field Data Transmission for Biomedical Implants

Abstract:  Inductive links have been widely used for simultaneous wireless power and data transmission for various biomedical implants. In this tutorial, basic principles of inductive coupling, wireless power transmission, and backscattering will be first reviewed. Then, recent techniques to enhance the data rate, power transfer efficiency, power consumption and robustness in the inductive power and data transmission will be discussed. In addition, practical design considerations in the context of biomedical applications will be covered.

Sohmyung Ha, New York University, USA

Bio: Professor Sohmyung Ha received the B.S (summa cum laude) and the M.S. degrees in Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2004 and 2006, respectively.From 2006 to 2010, he worked at Samsung Electronics as a mixed-signal circuit designer for commercial multimedia devices. After this extended career in industry, he returned to academia as a Fulbright Scholar and obtained the M.S. and Ph.D. degrees in Bioengineering with the Engelson Best Ph.D. Thesis Award for Biomedical Engineering from the Department of Bioengineering, University of California, San Diego, La Jolla, CA, USA, in 2015 and 2016, respectively. Since 2016, he has been an Assistant Professor at New York University Abu Dhabi, Abu Dhabi, UAE and a Global Network Assistant Professor at New York University, New York, NY, USA.

He currently serves as an associate editor of IEEE Transactions on Biomedical Circuits and Systems and Frontiers in Electronics and served as an associate editor of Smart Health (Elsevier) from 2016 to 2021. He is a member of the Analog Signal Processing Technical Committee (ASP TC) and the Biomedical and Life Science Circuits and Systems Technical Committee (BioCAS TC) of the IEEE Circuits and Systems Society (CASS). He is also a member of the IMMD Subcommittee of the International Technical Program Committee (ITPC) of the International Solid-State Circuits Conference (ISSCC).

Educational Session 4: Millimeter Wave/ sub-THz Phased Array Systems

Session Chair: Mustafijur Rahman, Indian Institute of Technology, Delhi, India and Sudipto Chakraborty, IBM, USA


Title: Recent Advances in THz Radar Imaging: Towards Millimeter Ranging Resolution and 2D Electronic Beam Steering with 1-Degree Angular Resolution

Abstract: Future intelligent platforms require imaging radars with LiDAR-like 3D image quality, but compact size and low cost. The corresponding ranging and angular resolution targets aggressively push the limits of bandwidth, density and scale of RF electronics. In this talk, we introduce the recent research at MIT that tackles those challenges using sub-THz CMOS systems, including a high-parallelism FMCW architecture that scans across 100-GHz bandwidth for a ranging resolution of 1.5mm, and a CMOS reflectarray that integrates 98×98 elements and performs electronic 2D beam steering of a 1-degree-wide pencil beam. We will also discuss how to avoid Tx and Rx beam misalignment that is common in large-aperture systems. Demonstrations, such as standoff 3D THz imaging without any mechanical moving part will be shown as well.


Ruonan Han, Massachusetts Institute of Technology

Bio: Ruonan Han received his B.S. degree from Fudan University in 2007 and Ph.D. degree from Cornell University in 2014. He is now an associate professor at the Department of Electrical Engineering and Computer Science, MIT. His research group focuses on RF-to-photonics integrated systems for spectroscopy, metrology, imaging, quantum sensing/ processing, broadband/secure communication, etc. He serves on the Technical Program Committee of IEEE ISSCC and RFIC conferences. He and his students have won three best student paper awards (2012, 2017 and 2021) in the RFIC symposium. He was the IEEE MTT-S Distinguished Microwave Lecturer in 2020-2022, and the winner of the Intel Outstanding Researcher Award in 2019 and the National Science Foundation CAREER Award in 2017.







Title: CMOS Sub-Terahertz Wireless Communications Using High-Frequency Circuit Techniques Beyond Fmax

Abstract: The 300-GHz band, one of the sub-terahertz bands, will be used in the sixth-generation (6G) wireless communications, and data rates exceeding 100 Gb/s are expected since the continuous 44-GHz frequency band in the 300-GHz band has been identified for wireless communications. Traditionally, compound semiconductors and SiGe with extremely high-frequency characteristics have been required to realize sub-terahertz wireless communications. On the other hand, it is possible to realize transceiver circuits that exceed fmax using CMOS integrated circuits, which are advantageous for mass production. In this talk, I will first explain the background of the use of sub-terahertz communications, including the 300 GHz band, in wireless communications. Next, the different points in designing sub-terahertz circuits compared to conventional RF circuits will be discussed. Techniques for realizing sub-terahertz transceivers in CMOS integrated circuits will also be discussed. Finally, we will discuss the potential of sub-terahertz communication to achieve not only high speed but also high efficiency communication.


Minoru Fujishima, Hiroshima University, Japan

Bio: Minoru Fujishima received his PhD from the University of Tokyo in 1993. He was a visiting professor at the Catholic University of Leuven, Belgium, from 1998 to 2000, and has worked on the design and modeling of CMOS and BiCMOS circuits, nonlinear circuits, single-electron circuits, and quantum computing circuits. He is a Distinguished Lecturer of the IEEE Solid State Circuits Society, Chair of the IEEE Japan Council Chapter Operations Committee, and currently President of the Electronics Society of the Institute of Electronics, Information and Communication Engineers (IEICE). He is a Fellow of the IEICE, a Senior Member of the IEEE, and a member of the Japan Society of Applied Physics.




Title: CMOS mmWave/THz Phased-Array Transceiver Design for 6G

Abstract: The present wireless communication utilizing microwave based on the omnidirectional radiation has been studied so far. The millimeter-wave directional wireless communication based on the beamforming technique has been opening up a new research field in integrated circuit design. Wider available frequency band along with spatial co-existence and multiplexing could be supported by the millimeter-wave phased-array communication. To take more advantages of higher frequency, now wireless communication in the sub-THz and THz bands is also being considered for future 6G communications. In this presentation, theoretical background of millimeter-wave/THz phased-array communication will be introduced as well as design challenges of THz transceiver by CMOS. A 300-GHz phased-array transceiver realized by 65nm CMOS technology will be introduced. The talk concludes with a discussion on future directions of THz wireless communication, based on Shannon and Friis equations.


Kenichi Okada, Tokyo Institute of Technology

Bio: Prof. Kenichi Okada received the B.E., M.E., and Ph.D. degrees from Kyoto University, Kyoto, Japan, in 1998, 2000, and 2003, respectively. He joined Tokyo Institute of Technology in 2003, and he is now Professor. He has authored and co-authored more than 500 journal and conference papers. His current research interests include millimeter-wave/terahertz wireless transceiver, digital PLL, and ultra-low-power RF circuits. He is/was a TPC member of ISSCC, VLSI Circuits, ESSCIRC, RFIC Symposium, A-SSCC, Guest Editors and Associate Editors of JSSC and T-MTT, a Distinguished Lecturer of SSCS, and IEEE Fellow.





Title: Recent Baseband Discrete-time Delay Compensation for Large Scale Antenna Arrays

Abstract: Efficient exploitation of wide bandwidth data communication requires antenna array providing high gain across all frequency components for both transmit and receive equipment. However, traditional phased array topology exhibits frequency dependent channel characteristic, leading to performance degrading in terms of beamforming gain and directionality across a wide range of band-of-interest. True-time-delay (TTD) arrays are appealing yet insufficiently investigated alternative for both fast initial access (IA) process, wideband interference mitigation, and wideband directional data communications. In this tutorial, the mathematical relationship of delay before and after the frequency conversion will be first discussed. Second, a step-by- step design guide to compare delay-compensating analog or hybrid beamforming architecture with their digital counterpart will be provided considering antenna elements, modulation bandwidth, ADC dynamic range, and delay resolution. Lastly, array architectures and their implementations will be presented with wide fractional bandwidths and large-scale antenna arrays.

Subhanshu Gupta, Washington State University

Bio: Subhanshu Gupta received his Ph.D. from the University of Washington in 2010. Before joining the electrical engineering and computer science at Washington State University as an Assistant Professor in 2015, he worked in the radio frequency group at MaxLinear Inc. from 2011 to 2014. He is currently an Associate Professor at WSU and is a recipient of the National Science Foundation CAREER Award in 2019. Subhanshu serves as an Associate Editor for the IEEE Transactions on Circuits and Systems – I and also serves on the technical program committee of the IEEE Radio Frequency Integrated Circuits Symposium from 2022. His research interests lie in wideband transceivers, energy-efficient circuits and systems, and statistical hardware optimization for next-generation wireless communications and cryogenic interfaces.