Keynote Speakers
Monday Keynote
Monday, 20 April
8:50 am-9:40 am
David Blaauw, Kensall D. Wise Collegiate Professor of Electrical Engineering and Computer Science
University of Michigan
Bio: David Blaauw is the Kensall D. Wise Collegiate Professor in Electrical Engineering and Computer Science at the University of Michigan. He has published over 700 papers and holds 75 patents. His work has focused on digital, analog, and RF VLSI circuit design with particular emphasis on ultra-low power and high performance design for miniature sensor nodes. Before joining the University of Michigan in 2001, he worked for Motorola, Inc. in Austin, TX, where he was the manager of the High Performance Design Technology group. He received his B.S. in Physics and Computer Science from Duke University in 1986, and his Ph.D. in Computer Science from the University of Illinois, Urbana, in 1991. David was the Technical Program Chair and General Chair for the International Symposium on Low Power Electronic and Design and a member of the ISSCC analog and digital Technical Program Committees. He is an IEEE Fellow and the recipient of the 2016 SIA-SRC faculty award for lifetime research contributions to the U.S. semiconductor industry.
Title: Circuit Challenges in mm-Scale Computing
Abstract: One of the fascinating emerging areas of computing at the edge is the development of tiny, millimeter-scale sensors and robots, which are poised to open up a myriad of new application domains. Enabled by recent advances in low-power analog, digital, and RF design, mm-scale sensors and robots are rapidly becoming a reality. This application space introduces new circuit challenges that arise from the unique characteristics of the millimeter and sub-millimeter cyberphysical world. In this talk, we will survey these challenges and recent solutions, highlighting low-power circuit techniques ranging from ultra-low-power RF communication and ranging to tiny neural network processors for on-sensor intelligence. We will also discuss how system-level challenges drive these new circuit solutions and illustrate several complete and operational systems.
Tuesday Luncheon Keynote
Tuesday, 21 April
*Pre-Registration Required
11:45 am-1:30 pm
Chris Mangelsdorf
Bio: Chris Mangelsdorf (S’77 – M’84) received a B.S. in physics, magna cum laude, from Davidson College, Davidson, NC in 1977. In 1980 and 1984, he received the M.S. and Ph.D. degrees in electrical engineering at M.I.T. where he held the first Analog Devices Fellowship. He has been associated with Analog Devices since summer employment in 1980 and has been a Fellow of Analog Devices since 1998.
From 1996 to 2013, Dr. Mangelsdorf worked in Tokyo, running the Analog Devices Tokyo Design Center and then adding responsibility for the Shanghai and Beijing Design Centers with the title of Asia Technical Director. In 2013, he moved to the Analog Devices San Diego office, where he was engaged in the development of high speed A/D converters. In September 2020, Chris retired from Analog Devices and is now consulting and writing the “Shop Talk” series for IEEE Solid-State Circuits Magazine.
Dr. Mangelsdorf is a member of Phi Beta Kappa and Sigma Pi Sigma (physics) and has served on both the ISSCC Program Committee and the AdComm for the IEEE Solid-State Circuits Society. He holds 18 patents and has won the ISSCC Best Evening Session Award 10 times.
Title: “Grandpa Looks at AI”
Abstract: Starting from the fundamental principle that “all change is bad,” we critically review the technical impact of artificial intelligence. We will objectively examine the overblown hype and even-handedly assess AI’s pathetic track record. After dissecting a few carefully selected examples, we will then be in a position to render a fair and neutral judgement of “two thumbs down,” confirming -once and for all- that the AI emperor is naked.
Wednesday Keynote
Wednesday, 22 April
8:50 am-9:40 am
Brucek Khailany, Senior Director of the Accelerators and VLSI Research group, NVIDIA
Bio: Brucek Khailany joined NVIDIA in 2009 and is the Senior Director of the Accelerators and VLSI Research group. He leads research projects in energy efficient AI accelerators, innovative VLSI design methodologies, ML and GPU assisted EDA, and quantum computing. Over 16 years at NVIDIA, he has contributed to many projects in research and product groups spanning computer architecture and VLSI design. Prior to NVIDIA, Dr. Khailany was a Co-Founder and Principal Architect at Stream Processors, Inc where he led R&D related to parallel processor architectures. At Stanford University, he led the VLSI implementation of the Imagine processor, which introduced the concepts of stream processing and partitioned register organizations. He received his PhD in Electrical Engineering from Stanford University and BSE degrees in Electrical and Computer Engineering from the University of Michigan.
Title: Generative AI and Agentic AI for Chip Design
Abstract: Generative Artificial Intelligence (Generative AI), Large Language Models (LLMs), and Agentic AI are dramatically impacting the architecture, VLSI implementation, packaging, and circuit design tradeoffs of the chips used in AI hardware. They are also leading to many new opportunities for automation and productivity improvements in VLSI design methodology and EDA tools. In this talk, we will discuss the AI and hardware trends shaping our industry and highlight recent work from NVIDIA Research exploring the application of Generative AI and Agentic AI systems to digital design, verification, EDA, and custom circuit design and layout.