2020 CICC Panels

2024 CICC Panels

Key issues and controversial topics are debated by leaders from the IC industry. CICC panel discussions are well known for their lively and thought-provoking discussions. The Q&A sessions provide the audience the opportunity to weigh in on the important issues.

Panel Sessions

Monday, April 22

9:30 am-11:00 am

Cognitive Connections: Exploring Brain-Computer-Interfaces through Systems and Experiments

Emerging Technologies, Systems, and Applications

Session Chairs: Sungwon Chung, Neuralink, USA and Chul Kim, KAIST, South Korea

Recent advancement in ML/AI has spurred the development of emerging applications on brain-computer interfaces (BCIs). Along with this exciting development, we will openly discuss the challenges and opportunities in next-generation BCIs from systems and circuits perspective as well as R&D directions to address challenges in the commercialization of human BCI.


Jeffrey Herron, University of Washington, USA


Bio: Dr. Herron is an Assistant Professor in the University of Washington’s Department of Neurological Surgery with a PhD in Electrical Engineering whose research is focused on the development of human-use bi-directional neural-interfacing systems to enable or improve the treatment of neurological and psychiatric diseases, disorders, and injuries.


Position Statement: The fields of brain-computer interfaces (BCI) and neuromodulation both share a common goal of providing relief for those who suffer from neurological or psychiatric disorders, injuries, and diseases. However, the two fields have often been treated as distinct given how BCIs are focused on sensing and classifying neural activity whereas neuromodulation is focused on regulating symptoms with stimulation. However, ongoing advancements in sensory stimulation for BCI and brain-sensing enabled adaptive Deep Brain Stimulation (aDBS) illustrate that the distinction between the fields is growing increasingly irrelevant. Collaboration will be key to address the many common challenges that both fields face.

Shadi Dayeh, University of California, San Diego, USA

Bio: Shadi Dayeh is a Lebanese American Neurotechnologist who pioneered human brain recordings with multi-thousand channels since 2019 and is an ECE Prof. at UC San Diego. He is an awardee of the NIH Director’s New Innovator Award, NSF CAREER Award, ISCS Young Scientist Award and was a J.R. Oppenheimer Fellow at Los Alamos.


Position Statement: Minimally invasive electrocorticography (ECoG) platinum nanorod grids (PtNRGrids) enable decoding neurodynamics of healthy and diseased brain activity at high spatiotemporal resolution. ECoG promises stable long term BCI interfaces while recording and interrogating potentially all brain regions orchestrating cognition and function due to its large area coverage of the cortex. Recently, ECoG revealed individual functional columns associated with language processing, promising accurate BCI interfaces.                          


Roman Genov, University of Toronto, Canada    

Bio: Roman Genov received the Ph.D. degree from Johns Hopkins University, in 2003. He is currently a Professor in the Department of Electrical and Computer Engineering at the University of Toronto. Dr. Genov is a co-recipient of Jack Kilby Award for Outstanding Student Paper at ISSCC as well as a co-recipient of 6 Best Paper Awards at various other IEEE conferences and journals.                                  

Position Statement: Dr. Genov’s research interests are primarily in biomedical integrated circuits and systems for energy-constrained applications, such as implantable neural interfaces and closed-loop neuromodulation in the CNS and PNS, with many publications on these topics at the flagship International Solid-State Circuits Conference (ISSCC) and in various relevant journals.                                 




Minkyu Je, KAIST, South Korea 

Bio: Minkyu Je received the B.S., M.S., and Ph.D. degrees from KAIST, Korea. He is now an Associate Professor in the School of Electrical Engineering at KAIST, Korea. His research area is energy- and volume- constrained circuits and systems for biomedical and wireless sensing applications. He is an editor of 1 book, an author of 6 book chapters, and has more than 360 peer-reviewed international conference and journal publications. He also has more than 70 patents issued or filed. He has served on the TPC for ISSCC, SOVC, and A-SSCC. He was a Distinguished Lecturer of the CASS and now serves as an Associate Editor of TBioCAS.                          

Position Statement: To go beyond targeting patients and ultimately succeed in adoption and commercialization among the general user population, brain-computer interfaces must provide sufficient benefits and utility upon adoption while minimizing the costs and penalties associated with its use (such as device price, size, surgical expenses for internal installation, and associated risks). Given that brain-computer interfaces require various components and represent an amalgamation of advanced technologies from various fields (including integrated circuits), it is necessary to consider what technologies are needed to achieve the aforementioned goals on a field-by-field and component-by-component basis and focus on research and development to secure these specific technologies.

Mahsa Shoaran, EPFL, Switzerland                      


Mahsa Shoaran is currently an Assistant Professor in Electrical Engineering and Neuro-X at EPFL. From 2017 to 2019, she was an Assistant Professor of ECE at Cornell University, and a Postdoc at Caltech from 2015 to 2017. She received her PhD from EPFL in 2015 and her B.Sc. and M.Sc. from Sharif University of Technology. Dr. Shoaran is a recipient of the ERC Starting Grant and the Google AI Faculty Research Award in Machine Learning. Her team received the IEEE SSCS–Brain Best Paper Award in 2022. Dr. Shoaran serves on the Technical Program Committee of the ISSCC and as a TBioCAS Associate Editor.                                

Position Statement:  Implantable neural interfaces promise breakthrough therapies for treatment-resistant brain disorders. Despite significant advances in neural interface systems over the past decade, existing brain implants do not adequately meet the clinical needs for severe psychiatric illness and many other disabling neurological conditions. To bridge this gap, future-generation neural devices must leverage interdisciplinary expertise spanning AI, integrated circuits, neuroscience, neurology, microfabrication, packaging, and robotics. Intelligent AI-driven neural interfaces powered by highly integrated CMOS technologies will transform the treatment landscape for brain disorders in the future.


Monday, April 22

9:30 am-11:00 am

Will open source design be the future direction?

Data Converters

Session Chairs: Jie Gu, Northwestern University, USA and Seung-tak Ryu, KAIST, South Korea

In the field of future semiconductor design, open-source hardware presents a vision of transformative change in innovation and collaboration. Our panel will discuss its potential to disrupt traditional chip design, fostering accessibility and community-driven innovation. Join us as we discuss exciting prospects of open-source hardware innovation.


Jaeduk Han, Hanyang University, South Korea


Bio: Jaeduk Han is an Assistant Professor of Electronic Engineering at Hanyang University. He received his Ph.D. degree in Electrical Engineering and Computer Sciences from the University of California at Berkeley in 2017. His research interests include high-speed analog and mixed-signal (AMS) circuit design and automation.


Position Statement: The open-source domain notably empowers Electronic Design Automation (EDA) and solid-state device researchers to more easily construct circuits. Moreover, open-source hardware shines in facilitating design reusability and collaboration, as evidenced by our research team’s work on integrating automated layout tools with synthesis-based memory compilers, which is difficult to achieve in closed domains. Nonetheless, for open-source hardware technology to advance, several challenges must be overcome. For instance, in hardware design, synthesis, and place-and-route tools perform roles similar to compilers in the software domain. Yet, the complexity of advanced CMOS processes limits the direct application of open-source tools. Moreover, analog circuits require manual layout creation, which complicates reusability issues. To address this, our team has developed and continues to refine an automation tool for analog circuit layout design, aiming to surmount these hurdles. In summary, the trajectory of open-source hardware is promising, driven by community growth, IP sharing, and tool development. Our dedication to improving open-source hardware aims to democratize hardware design, echoing the revolutionary impact of open-source software.


Curtis Mayberry, Skyworks, USA        


Bio: Curtis Mayberry is a principal analog and RF IC Design engineer and leads the IP team at Skyworks. He holds a BS from Iowa State University and a MS from Georgia Tech. He started the Cascode-Labs organization to collaborate on open-source solutions to improve analog and RF design and verification.


Position Statement: Open-source PDKs, tools, and designs are making IC design accessible to a much larger community of engineers and will find their place in the future.  This will continue to open up IC design education and research with new opportunities to collaboratively build hands-on projects that can be easily reproduced.  It will also open up new opportunities for industrial teams to collaborate with others outside their organization. This will enable new methodologies, techniques, and applications that most organizations aren’t able to evaluate or support on their own. However, for this to reach its full potential we’ll need to adopt new ways to support a healthy community.


Rob Mains, CHIPS Alliance, USA


Bio: Rob Mains is a 40-year industry veteran, former engineering vice president of Oracle and Sun Microsystems distinguished engineer. Prior to this, Rob was a principal engineer at Magma Design Automation, and originally a senior engineer at IBM. As general manager of CHIPS Alliance, a part of the Linux Foundation, Rob is working to build the open source hardware ecosystem to create a collaborative, worry-free environment for participants to work in and build innovative products off of open source components.


Position Statement: Open source hardware design, including both IP and EDA, will be an increasing ingredient in the development of any SoC. This will be necessitated by the continuing need for increased productivity of design teams, time to market, and reduced costs. Open source in hardware has the potential to provide this level of acceleration in hardware development to help keep pace with Moore’s law. There will be challenges in making this all a reality, but it is not an impossibility.


Tim ‘mithro’ Ansell, USA


Bio: Tim ‘mithro’ Ansell is a pioneering figure in open-source silicon, known for his crucial role in democratizing chip design. Through initiatives like the SkyWater and GlobalFoundries open-source PDKs and the Open MPW program, he has significantly lowered barriers to entry, enabling innovation and access for individuals and smaller entities in semiconductor technology.


Position Statement: Open-source Process Design Kits (PDKs) are pivotal not just for democratizing Integrated Circuit (IC) design but also for meeting the urgent need for training a growing workforce in a society that demands faster and more advanced IC development. The transparency inherent in open-source projects promotes a deeper understanding of semiconductor processes, fostering education and collaboration across geographical and institutional boundaries. By enabling broader participation in the design and fabrication process, open-source PDKs ensure that advancements in semiconductor technology can keep pace with societal needs. In essence, these initiatives are about building a future where technology development is inclusive, education is accessible, and the workforce is ready to meet the challenges of tomorrow’s IC demand.

Mohamed Kassam, Efabless, USA

Bio: Mohamed Kassam is the CTO and Co-Founder of, the first semiconductor company applying open community innovation to all aspects of product development. Prior to launching efabless in 2014, Mohamed held several technical and global leadership positions within Texas Instruments’ Wireless Business Unit.

Mohamed joined TI in 2000 at the beginning of the digital telephony revolution fueled by the unprecedented integration of major phone functions on a single SoC. He led the first development of 45nm, 28nm analog & mixed-signal IP functions for wireless applications processors.

Mohamed holds a Masters degree in Electrical Engineering from the University of Waterloo, Ontario, Canada.


Position Statement: Open-source chip design tears down these barriers, empowering a global community of engineers, researchers, and enthusiasts to work together on cutting-edge solutions.

This collaborative approach accelerates the pace of innovation, driving down the cost of development and making powerful new chip technologies accessible to all.

By promoting transparency, reusability, and a shared knowledge base, open-source design reduces redundancy and streamlines development cycles. We envision a future where chip design is democratized, encouraging a new wave of creativity and problem-solving that benefits industries and individuals worldwide.

The open-source movement has the potential to revolutionize the semiconductor industry, fostering unprecedented collaboration and technological advancement.



Monday, April 22

3:00 pm-4:30 pm

Can Academia Effectively Participate in Heterogeneous Integration Research and How?
Foundation of System Design

Session Chairs: Zhengya Zhang, University of Michigan, USA and Farhana Sheikh, Intel, USA

Join this panel discussion as we explore the challenges and opportunities in conducting research on heterogeneous integration (HI). While industry currently leads the way with its advanced packaging and integration technologies and tools, academia seeks to bridge the gap and enhance collaboration. Our panelists will discuss ways for narrowing this divide, emphasizing the empowerment of academic partners in HI research, and fostering meaningful industry-academia collaborations.




Zhengya Zhang, University of Michigan, USA


Bio: Zhengya Zhang received the B.A.Sc. degree from the University of Waterloo in 2003, and the M.S. and Ph.D. degrees from UC Berkeley in 2005 and 2009, respectively. Since 2009, he has been with the Department of Electrical Engineering and Computer Science at the University of Michigan, Ann Arbor, where he is currently a full professor. His research primarily focuses on low-power and high-performance VLSI circuits and systems, with applications in computing, communications, and signal processing. Dr. Zhang was a recipient of the NSF CAREER Award, the Intel Early Career Faculty Award, the University of Michigan Neil Van Eenam Memorial Award, and the David J. Sakrison Memorial Prize from UC Berkeley. He serves as an IEEE Solid-State Circuits Society Distinguished Lecturer.


Abstract: Heterogeneous integration is an exciting and emerging field of academic research. However, it does encounter practical barriers, including limited access to advanced packaging and high-yield assembly. A closer collaboration between industry, labs, and academia is essential for academic teams to make progress in HI research.



Madhavan Swaminathan, Pennsylvania State University, USA

Bio: Madhavan Swaminathan is the Department Head of Electrical Engineering and is the William E. Leonhard Endowed Chair at Penn State University. He also serves as the Director for the Center for Heterogeneous Integration of Micro Electronic Systems (CHIMES), an SRC JUMP 2.0 Center.

Prior to joining Penn State, he was the John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE), Professor in ECE with a joint appointment in the School of Materials Science and Engineering (MSE), and Director of the 3D Systems Packaging Research Center (PRC), Georgia Tech (GT). Prior to GT, he was with IBM working on packaging for supercomputers.

He is the author of 650+ refereed technical publications and holds 31 patents. He is the primary author and co-editor of 3 books and 5 book chapters, founder and co-founder of two start-up companies, and founder of the IEEE Conference on Electrical Design of Advanced Packaging and Systems (EDAPS), a premier conference sponsored by the IEEE Electronics Packaging Society (EPS). He is a Fellow of IEEE, Fellow of the National Academy of Inventors (NAI), Fellow of Asia-Pacific Artificial Intelligence Association (AAIA), and has served as the Distinguished Lecturer for the IEEE Electromagnetic Compatibility (EMC) society. He has been recognized through many awards with the most recent one being the 2024 IEEE Rao R. Tummala Electronics Packaging Award (technical field award) for contributions to semiconductor packaging and system integration technologies that improve the performance, efficiency, and capabilities of electronic systems.

He received his MS and PhD degrees in Electrical Engineering from Syracuse University in 1989 and 1991, respectively.


Position Statement: Heterogeneous Integration (HI) is taking center stage for the continuation of Moore’s law. Without Academia fueling innovations, HI can be very short lived. An accelerated lab-to-fab model is necessary, which requires strong university-industry-government collaboration.


Surya Bhattacharya, A-Star, Singapore


Bio: Dr. Surya Bhattacharya is Director of System-in-Package at A*STAR Institute of Microelectronics (IME), Singapore.  Over the past 30 years, he has worked on CMOS scaling at fabless companies, integrated device manufacturer (IDM); and Package Scaling in Research Institute setting.  At the Institute of Microelectronics, Singapore, Surya leads the advanced packaging team to initiate and execute consortia projects to address industry’s pre-competitive challenges in advanced heterogeneous integration for system scaling.  Prior to joining IME, he was Director of Foundry Engineering at Qualcomm, where he executed technology and manufacturing ramps across multiple foundries around the world.  Prior to Qualcomm, he was a Principal Foundry Engineer at Broadcom Corporation.  He started his career at Rockwell Semiconductor Systems, Newport Beach, California, where he was Senior Manager for CMOS technology development.   Surya has a PhD in Electrical Engineering from the University of Texas at Austin, and B.Tech in Electrical Engineering from the Indian Institute of Technology, Madras


Position Statement:

-AI and HPC will drive the transition from Exa-scale compute to Zetta-scale compute systems.  Heterogeneous Integration Packaging is the industry’s only known way to achieve system scaling that is needed to support Zetta-scale compute.

-Heterogenous integration to achieve massive complex future systems will need breakthroughs and innovations in Materials-science, Electrical-engineering, Mechanical-Engineering, System-architecture, Physical-design, Design-enablement.

-IME’s experience has clearly indicated Academia’s  articipation in Heterogeneous Integration research CAN/MUST be achieved. It is CRITICAL for achieving innovations and also preparing future talent.  Research institutes provide a key platform for such participation.

Shenggao (Victor) Li, TSMC, USA


Bio:  IEEE Sr. Member 2005, Member 1997, received his PhD, MS, and BS degree from The Ohio-state University, Tsinghua University, Northwestern Polytechnical University, respectively. He is currently a director with the Mixed-signal and RF Solutions Division in TSMC, North America, with a focus on energy efficient interconnects, including chiplet and 3D-IC interconnects, such as UCIe and Lipincon physical layer, and high-speed ADCs for wireless and wireline communications. Prior to that, he was a Principal Engineer and Section Leader responsible for Intel’s PCIe Gen3.0, Gen4.0 and Gen5.0, and UPI PHY development for 5 generations of Xeon CPU products. He serves in the Technical Program Committee for Wireline in CICC 2022, 2023, 2024, and Sponsorship Chair in CICC 2023 and 2024. He is currently a co-chair in the UCIe consortium on Form-factor and Compliance Working Group. Shenggao has authored over 30+ patents, 30+ publications and was an invited speaker on 3D-IC interconnects in CICC 2022 & ISSCC 2023.                        


Position Statement:

-The industry is rapidly embracing chiplets, 3DIC, and heterogenous integration

-Prohibiting cost of designing in advanced packages, but cost will reduce with time

-Abundant problems to solve in this transition to the 3D arena: Device, material, thermal, methodology

-Market for heterogenous integration is growing: not mature, huge innovation opportunities

-New device & architectures for better energy efficiency and performance are fundamental to 3D scaling

-Academia can play a significant role on heterogenous integration – Collaboration, Divider & conquer


Wednesday, April 24

1:45 pm-3:15 pm

How can LLMs help hardware design and will it replace digital design roles in the years to come?
Digital Circuits, SoCs, and Systems

Session Chairs: Farah Yahya, Everactive, USA and Weiwei Shan, Southeast University, China


Chris Cheng, Hewlett-Packard Enterprise Company (HPE), USA


Bio: Chris Cheng is a Distinguished Technologist in HPE. He manages SI/PI and hardware ML development within the Storage Division. He developed the original GTL bus in SUN Microsystems. He was a Principal Engineer leading processor bus design in Intel. He guided 3PAR SI/PI design until it was acquired by HP.


Position Statement: Large language models with domain knowledge enhancements will fundamentally change the way we design hardware. From knowledge accumulation to co-piloting for engineers, it will help train junior engineers and reduce the workload of experienced engineers to enhance the productivity of our design task.


Xi Wang, Southeast University, China


Bio: Dr. Xi Wang obtained his Ph.D. in Computer Science from Texas Tech University in 2020. He completed his postdoctoral research at Tsinghua University at Dr. David A. Patterson’s lab. He is now an Assistant Professor at Southeast University, where he leads the development of domain-adapted LLMs for digital circuit design. He developed CyberRio, the first RISC-V processor generated by an LLM and fabricated with 130nm, won the Efabless 2023 AI Design Contest Second Prize.


Position Statement: As semiconductor designs grow increasingly complex, there emerges a pressing need for agile hardware development methodologies to match the pace of swift technological progress. This complexity is further compounded by domain-specific architecture designs, driven by emerging applications, which add significant overhead to the chip design and verification processes. In this scenario, Large Language Models (LLMs) have emerged as a promising solution, offering innovative avenues for hardware design automation. The capabilities of current models, such as GPT-4, have been demonstrated in assisting various aspects of digital circuit design, including RTL coding, debugging, optimizations, etc. These models have not only streamlined the design process but have also enhanced the accuracy and efficiency of chip development. Looking forward, the evolution of LLMs is poised to unlock even more advanced functionalities and efficiencies in semiconductor design and verification, signaling a transformative shift in how hardware is developed. Embracing this evolution, the industry can leverage the full potential of LLMs to meet the increasing demands of modern chip design.


John Rose, Cadence, USA


Bio: John Rose is a Product Engineering Director in the system verification group at Cadence. His primary product responsibilities have been in the area of logic simulation specifically with respect to metric driven verification flows. John came to EDA in 1997 after a career as an ASIC designer and verification engineer. At Cadence, John has focused on verification tools and methodologies. For the past three years, John has been focused on helping bring Cadence’s simulation based machine learning technology, Verisium SimAI, to the broader market.


Position Statement:  The design and verification complexity of modern chips has continued at an exponential rate with development windows staying roughly constant, but in the past 20 years there hasn’t been a productivity level jump to help designers and verification engineers keep pace. This has led to a higher rate of costly respins among other problems. The release of GPT-3 (and now GPT-4) has injected excitement into the industry with the promise of a new class of technologies that can aid in the design and verification of modern chips. There are many areas where LLMs or similar models can be used for generative AI applications to create RTL code, testbench code, or any other intermediate step needed to get a chip out the door. Of course, LLMs are not the only interesting types of machine learning models that will drive productivity. Neural networks using randomization data as the input layer may, for example, help verification engineers reach difficult design states where latent bugs are more likely to exist.  A big challenge for EDA companies is to bring these technologies to engineers in ways that will meet their security and compute requirements so that the LLMs, or other models, can be trained on their data without sacrificing security. The promise of a productivity level jump is undeniable; it will be up to all of us to make that promise a reality.