2022 CICC Educational Sessions
Educational Sessions are held on Sunday, 24 April 2022. Attendance to any of these sessions is included in the standard conference registration. Take this opportunity to learn about new topics from leading engineers in the field.
Educational Session 1: Analog Automation Techniques
Sunday, 24 April 2022, 9:00 am-4:45 pm PDT
Sessions Chairs: Sudipto Chakraborty, IBM Watson, USA & Bongjin Kim, University of California, Santa Barbara, USA
ES1-1: Efficient Simulation of Analog/Mixed-Signal Circuits in SystemVerilog with Auto-Generated Models
Bio: Jaeha Kim is currently Professor at Seoul National University (SNU), Seoul, Korea, and CEO and founder of Scientific Analog, Inc., Palo Alto, CA. With a flagship product called XMODEL, he is pursuing ways to make analog design and verification as efficient as digital. Prof. Kim received the B.S. degree from SNU in 1997, and the M.S. and Ph.D. degrees from Stanford University in 1999 and 2003, respectively. Prior to joining SNU, Prof. Kim was with Stanford University as Acting Assistant Professor, with Rambus, Inc. as Principal Engineer, and with Inter-university Semiconductor Research Center (ISRC) at SNU as Post-doctoral Researcher. Prof. Kim is a recipient of the Takuo Sugano award for Outstanding Far-East Paper at 2005 ISSCC and is cited as Top 100 Technology Leader of Korea by the National Academy of Engineering of Korea in 2020.
Abstract: Today’s SoC designs are neither purely digital nor purely analog; they are mixtures of both. As SPICE simulators face difficulty in handling such large circuits at the system level, modeling the analog circuits in SystemVerilog and verifying the whole system using digital verification flows such as UVM is becoming a common practice. This talk addresses ways to auto-extract models from analog circuits and run efficient simulations with them in an event-driven logic simulator like SystemVerilog. It all starts with how we express analog waveforms. Using equations instead of points, the event-driven algorithm of SystemVerilog can be extended to analog simulations, even to transistor-level circuits exchanging voltages and currents. This also opens the door to automated ways of extracting models from circuits. Using a set of model templates both at the device level and at the circuit level, the models with SPICE-accurate characteristics can be auto-generated from the circuits. These analog models running in SystemVerilog can deliver up to ~100x speed-up’s compared to running SPICE.
ES1-2: Analog and Mixed-Signal Layout Automation using Digital Place-and-Route Tools
Bio: Po-Hsuan Wei (Member, IEEE) received the B.S. degree in electrical engineering from the National Taiwan University, Taipei, Taiwan, in 2013, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, USA, in 2016 and 2021, respectively. She is currently with Nvidia Corporation, Santa Clara, CA, USA, and has previously held internship positions at Cisco Systems, Inc., San Jose, CA, USA, and Xilinx, Inc., San Jose. Her research focuses on a data-driven methodology that automates analog and mixed-signal layout generation for integrated circuits (ICs).
Abstract: Driven by the needs of mobile communications and consumer electronics, analog and mixed-signal (AMS) circuits have become ubiquitous in modern, high-volume systems on chip (SoCs). Despite this ubiquity, the AMS design and layout remain a bottleneck for many SoC developments. Whereas the digital layout flow is highly automated due to commercial digital place-and-route (PnR) tools, today’s AMS layout flow requires long manual iterations and does not leverage computing resources for data-driven optimization. This issue is further compounded by the explosion of design rules and layout-dependent effects (LDEs). The first part of this tutorial covers state-of-the-art AMS layout automation efforts, with an emphasis on their applicability to designs in FinFET CMOS, where many SoCs are developed. The second part of the tutorial presents an AMS layout generation flow that leverages digital PnR tools, amortizes setup cost with reusable primitives, and prunes layout candidates using a fast evaluation scheme. I also analyze LDEs and parasitics and investigate unique challenges and mitigation strategies associated with using digital PnR tools for AMS circuits.
ES1-3: Has the Time for Analog Design Automation Finally Come?
Bio: Dave Reed is senior director of custom design product management at Synopsys. He has been involved in IC design and design automation for more than 35 years, with a focus on analog design and layout. Prior to Synopsys Dave was co-founder and CEO of Blaze DFM, which helped engineers overcome design challenges of advanced process nodes. Dave received his BS in Electrical Engineering from Lehigh University.
Bio: Avina Verma is a R&D Group Director with Synopsys, Inc. She has over 20+ years of experience developing solutions for both digital and analog offerings. Avina currently leads Place & Route Custom Compiler teams with a vision to develop the next generation flows with a focus on solving customer problems via automation. She is passionate about technology and innovation. Her previous experience was leading Analog & Custom routing technologies at Cadence Design Systems. Avina holds a Master’s in Computer Science from Stanford University.
Abstract: The semiconductor industry is experiencing explosive growth, driven by emerging applications such as AI, 5G, IoT and automotive. To keep pace, design teams have deployed sophisticated CAD tools that can implement digital designs comprising billions of transistors. However, while digital design has been extensively automated, analog continues to require handcrafting by experts. In this talk we’ll review how analog differs from digital and how this complicates analog automation. We’ll review some approaches to analog automation that have been tried in the past – both successful and less so. And we’ll discuss the latest techniques for delivering automation in three key areas of analog design – design closure, analog layout, and analog IP process porting. These techniques include best practices that have been deployed by leading analog design teams, as well as fresh innovations in analog design tools.
ES1-4: Improving Analog/Custom Design Productivity with ML
Bio: Hongzhou Liu is a Software Engineering Group Director Cadence Design Systems. Hongzhou Liu got his PhD degree in Electrical and Computer Engineering from Carnegie Mellon University in 2004. His work focus is analog design automation. He won 2016 IEEE Donald O. Pederson best paper award and 2002 IEEE Design Automation Conference best paper award. He holds more than 15 USA patents.
Bio: Chandramouli Kashyap is a Distinguished Engineer at Cadence Design Systems. Chandra works on applying Machine Learning technologies for improving analog mixed-signal design productivity. Prior to joining Cadence, Chandra spent over 15 years at Intel on various CAD technologies. Prior to that he worked at IBM. Chandra has a PhD from University of Michigan and is a Senior Member of the IEEE. He has served on TPCs of DAC and ICCAD and as well as the Associate Editor of IEEE Trans. On CAD. He has 12 patents and a William J. McCalla Best Paper award at ICCAD.
Abstract: Numeric based circuit optimization technology exists in commercial EDA tools for analog/custom circuit designers. These optimization technologies won’t replace the analog circuit designer’s domain expertise and won’t be efficient if they are used as a push button automation solution. Appropriate constraints and setup are crucial to apply optimization and modelling technology. It is also important to select the right automation technology at the different design stages: such as initial circuit design stage, meeting all PVT corners, high sigma analysis and optimization, design migration. In the advance node, the effort of analog layout increases significantly because of complex design rule and significant impact of parasitic estimation. The advance node rule requirements limit the layout choices and open doors for layout automation for placement and routing. We will cover some layout automation methodology in advance node design.
An important design decision is to analyze when it makes sense to apply ML. We identify two areas where ML has been successfully used in EDA: parasitic estimation and circuit optimization. We review a couple of different approaches to parasitic estimation with one of them involving Graph Neural Networks. We review the GNN theory and show how it has the potential in many areas of EDA that uses graphs. We next describe a reinforcement learning technique known as actor-critic method and how it has been used in circuit sizing. We describe the intuition behind the method and show some recent results. Finally, we outline several areas like statistical modeling, place and route where ML techniques may be useful as future research directions
Educational Session 2: Design of High Power Density Voltage Regulator Circuits & Systems
Sunday, 24 April 2022, 9:00 am-4:45 pm PDT
Session Chairs: Hans Meyvaert, SoliDC, Belgium & Hyun-Sik Kim, KAIST, Korea
ES2-1: Integrated High-Input Voltage Converters for High-Density, High-Efficiency Power Delivery Solutions
Bio: Nachiket Desai received the B.Tech. degree in electronics and electrical communication engineering from IIT Kharagpur, Kharagpur, India, in 2010, and the S.M. and Ph.D. degrees in electrical engineering and computer science from the Massachusetts Institute of Technology, Cambridge, MA, USA, in 2012 and 2017, respectively. He is currently a Research Scientist with the Circuits Research Lab, Intel Labs, Hillsboro, OR, USA. His current research interests include new topologies and control techniques for integrated high-frequency dc-dc power conversion.
Abstract: Power delivery is increasingly becoming the bottleneck in scaling up the performance of compute and graphics solutions. High output power demanded from the platform power delivery solution, combined with low output voltage, can lead to a significant amount of copper loss, adversely impacting overall efficiency. Delivering power at a higher voltage is key to eliminating both the loss and density bottlenecks, but it pushes the final conversion stage inside the socket where both the available passives’ volume and thermal budget for conversion loss are at a premium. In addition, high-input voltage regulators are challenging to integrate on advanced CMOS processes where the individual device limits are trending in the opposite direction. This talk discusses a variety of approaches to bring high-input voltage regulators closer to the final load, such as fully integrated stacked converters and heterogeneous integration that can take advantage of CMOS alternatives like GaN.
ES2-2: Pushing the Boundaries of Wide-Bandgap Power Conversion: A Journey Towards Monolithic Integration
Bio: Jef Thoné received his Master of Engineering degree in Electronics at the Karel de Grote University, Antwerp, Belgium in 2002. From 2002 to 2006 he worked at Melexis Belgium as analog designer and project manager, on automotive sensor interface CMOS ASICs. From 2006 to 2011 he worked towards his Ph.D. at ESAT-MICAS, KU Leuven, on telemetry for wireless capsule endoscopy. In 2011 he and Dr. Mike Wens founded the company MinDCet, a Power IC design house based in Belgium. In his role of CTO, he lead the design of numerous high-voltage, high current and wide bandgap integrated circuits. He is co-holder of 2 granted patents on measurement systems for inductor and capacitor losses.
Abstract: The global climate change – urging for lower carbon emissions – is thrusting the current wave of electrification. The hunt for lost Joules in electrical energy generation, storage and conversion is more important than ever.In each of these steps, power stages, inductors and capacitors play a key role, transferring power with minimal losses. In the last decade, traditional MOSFET and IGBT power stages are increasingly replaced by GaN and SiC switches, as they present higher power density and lower losses for similar operating conditions. Unfortunately – driving GaN or SiC is not as forgiving as driving a MOSET or IGBT, and offers new challenges to reach return-on-investment. This tutorial treats the challenges and solutions towards maximized efficiency when driving wide-bandgap based power circuits – as well as a vision on the roadmap….
ES2-3: High Performance Power Electronics for High Performance Computing: Design with Hybrid Switched Capacitor Circuits and Magnetics
Bio: Minjie Chen received his Ph.D. degree in Electrical Engineering and Computer Science from MIT in 2015, and his B.S. degree in Electrical Engineering from Tsinghua University in 2009. He is an Assistant Professor of Electrical and Computer Engineering and Andlinger Center for Energy and the Environment at Princeton University. His research interests include high frequency power electronics, power architecture, power magnetics, and the design of high-performance power electronics for important applications. He is a recipient of three IEEE Transactions Prize Paper Awards, a COMPEL best paper award, an OCP best paper award, the NSF CAREER Award, a Siebel research award, a C3.ai research award, the D. N. Chorafas Ph.D. thesis award from MIT, and many other awards from the IEEE Power Electronics Society. He has published over 40 papers in IEEE journals and conferences and holds 6 issued patents.
Abstract: Future microprocessors consume hundreds of amperes of current at very low voltage in a small footprint. High efficiency, high power density, and high control bandwidth power electronics are needed to support future high current microprocessors. This education session presents some of the latest research and development of hybrid switched-capacitor power converters and magnetics for applications in high performance computing. Various aspects of the hybrid converter design will be discussed, including the analysis of topological benefits, the design of gate drive circuit and magnetics, the control techniques for soft-charging and soft-switching, and the current sharing and voltage balancing dynamics of the switching cells. We will introduce a series of technologies developed for 48V-1V power conversion, including 1) a family of merged-two-stage hybrid-switched-capacitor circuit with low power conversion stress; 2) miniaturized multiphase coupled inductor design for ripple reduction and fast transient; and 3) 3D vertical power delivery from motherboard to microprocessors targeting extreme current area density. A few recent 48V-1V high performance designs will be introduced and compared to showcase the challenges and opportunities.
ES2-4: Basics of Adaptive & Resilient Circuits & Integration into Future Voltage Regulators
Keith Bowman, Qualcomm, USA
Bio: Keith A. Bowman is a Principal Engineer and Manager in the Corporate Research and Development (CRD) Processor Research Team at Qualcomm Technologies, Inc. in Raleigh, NC, USA. He is responsible for researching and developing circuit technologies for enhancing the performance and energy efficiency of Qualcomm processors. He pioneered the invention, design, and test of Qualcomm’s first commercially successful circuit for mitigating the adverse effects of supply voltage droops. He received the B.S. degree from North Carolina State University in 1994 and the M.S. and Ph.D. degrees from the Georgia Institute of Technology in 1995 and 2001, respectively, all in electrical engineering. From 2001 to 2013, he worked in the Technology Computer-Aided Design (CAD) Group and the Circuit Research Lab at Intel Corporation in Hillsboro, OR, USA. In 2013, he joined Qualcomm Technologies, Inc.
Dr. Bowman has published 90+ technical papers in refereed conferences and journals, authored one book chapter, received 30 US patents, and presented 40+ tutorials on variation-tolerant circuit designs. He received the 2016 Qualcomm CRD Distinguished Contributor Award for Technical Contributions, representing CRD’s highest recognition, for the pioneering invention of the auto-calibrating adaptive clock distribution circuit, which significantly enhances processor performance, energy efficiency, and yield and is integral to the success of the Qualcomm® Snapdragon™ 820 and future processors. In 2019 and 2020, he served as an IEEE SSCS Distinguished Lecturer. He was the Technical Program Committee (TPC) Chair and the General Conference Chair for ISQED in 2012 and 2013, respectively, and for ICICDT in 2014 and 2015, respectively. Since 2017, he served on the ISSCC TPC in the Digital Circuits (DCT) Subcommittee. He is currently the ISSCC DCT Chair.
Abstract: System-on-chip (SoC) processors across all market segments, ranging from small embedded cores in an Internet of Things (IoT) device to large multicore chips in data centers, experience dynamic device and circuit parameter variations during the operational lifetime such as supply voltage droops, temperature changes, transistor aging, and workload fluctuations. These dynamic parameter variations degrade processor performance, energy efficiency, and yield. This presentation introduces these primary variation sources and then describes the negative impact of these variations on processors across a wide range of voltage and clock frequency operating conditions. To mitigate the adverse effects from dynamic variations, this presentation describes adaptive and resilient circuits while highlighting the key design trade-offs and testing implications for product deployment. A primary focus is adaptive circuit techniques to address high-frequency supply voltage droops and auto-calibrating circuits to avoid expensive tester calibration. Finally, this presentation reviews the key trade-offs between analog and digital low-dropout (LDO) voltage regulators for SoC processors as well as the opportunity to improve future LDO designs via adaptive voltage-droop mitigation circuits.
Educational Session 3: System Design with Open Source Tools
Sunday, 24 April 2022, 9:00 am-4:45 pm PDT
Session Chairs: Xinfei Guo, Shanghai Jiao Tong University, China & Silvia Zhang, University of Washington Saint Louis, USA
ES3-1: The OpenROAD Project: A Foundation for Research and Education in EDA and IC Design
Bio: Andrew B. Kahng is Distinguished Professor of CSE and ECE and holder of the endowed chair in high-performance computing at UC San Diego. He was visiting scientist at Cadence (1995-97) and founder/CTO at Blaze DFM (2004-06). He is coauthor of 3 books and over 500 journal and conference papers, holds 35 issued U.S. patents, and is a fellow of ACM and IEEE. He has served as general chair of DAC, ISPD and other conferences, and from 2000-2016 as international chair/co-chair of the ITRS Design and System Drivers working groups. He is PI of OpenROAD https://theopenroadproject.org/, a $15M U.S. DARPA project targeting open-source, autonomous (“no human in the loop”) tools for IC implementation. He also serves as PI and director of TILOS, The Institute for Learning-enabled Optimization at Scale, which is an NSF AI Research Institute that began operations in November 2021 https://tilos.ai/. Some recent talks can be seen at his lab homepage: https://vlsicad.ucsd.edu/.
Abstract: The OpenROAD Project (https://theopenroadproject.org) develops an open-source RTL-to-GDS tool that generates manufacturable layout from a given hardware description – in 24 hours, with no human in the loop. The project is part of the IDEA program within the DARPA ERI. By reducing today’s cost, expertise and schedule barriers to hardware design, OpenROAD enables access to ASIC implementation, unleashing hardware innovation. To date, well over a hundred successful tapeouts have been made with OpenROAD in commercial nodes from 12nm to 130nm. This talk will present key aspects of the OpenROAD tool, learnings from the project since its start in June 2018, and the roadmap for OpenROAD as it transitions from the DARPA IDEA program to being a self-sustaining effort. OpenROAD’s futures include (i) serving as a foundation for academic research and teaching (of both EDA and IC design); (ii) seeding the transition of open-source EDA into government and commercial usage; and (iii) driving new machine learning research that further accelerates EDA and hardware innovation. Furthermore, OpenROAD enables transparency and reproducibility of hardware and EDA research, thus accelerating the pace of discovery in these critical technology domains.
ES3-2: Why is Google Investing in Fully Open Source IC Design and What is Next?
Bio: Tim ‘mithro’ Ansell is a software engineer at Google and has been developing open source software for 20+ years.
Tim has recently started trying to shake things up in the hardware accelerator development ecosystem by removing roadblocks to having a completely open ecosystem.
In 2020 he worked with SkyWater Foundry, a domestic U.S. manufacturer of integrated circuits, to release the world’s first fully open source, manufacturable PDK for their 130nm process node and is funding a free shuttle program for open source designs.
He has also contributed to projects in the open EDA ecosystem like OpenROAD, OpenRAM, Magic and many others.
Abstract: In the middle of 2020, Google released the first fully open source, manufacturable PDK (process design kit) for SkyWater’s 130nm process technology. When combined with the growing research area of open source Electronic Design Automation (EDA) toolsets, it’s possible to fully simulate and synthesize fully open source integrated circuits down to the physical layout.
At the same time Google started funding a no-cost shuttle program allowing researchers around the world to participate in this new research area which now has over 120 designs sent for manufacturing.
This capability opens new frontiers in using high performance computing and Artificial Intelligence to optimize and improve integrated circuits from fabrication through design.
This talk will cover the who, what, why and how of this industry changing development and how it is affecting all parts of the integrated circuit creation space including new collaborations with industry, academia, and government.
ES3-3: Creating a World where a 14-year-old Designs a Chip
Bio: Mohamed Kassem is the cofounder and CTO of efabless corporation. The world’s first community-centric company applying community expertise & creativity to all aspects of semiconductor design.
The company simplifies the process of developing chips and opens it to anyone. Before launching Efabless in 2014, Mohamed held technical & global leadership positions within TI’s Wireless Business Unit. He led the first development of 45nm, 28nm analog & mixed-signal designs for wireless processors. Mohamed holds a Masters degree in Electrical Engineering from the University of Waterloo, Ontario, Canada.
Abstract: For the first time in the history of the semiconductor industry it is possible to design, verify and manufacture Systems-on-Chip (SoC)’s that have been completely developed using an open source process technology, open source building blocks and open source design automation environment.
Last year, SkyWater Technology released the first open source PDK (SKY130). For the first time in the history of the semiconductor industry, it is now possible to design, verify, and manufacture systems on chip (SoCs) that have been completely developed using an open source PDK, open source building blocks, and a variety of open source and proprietary EDA tools.
In this session Mohamed will share how the semiconductor industry is changing for good because of the open source movement – a major and irreversible one. The session will also cover several community developed SoCs and a how-to-create-your-own-ASIC while only relying on open source ecosystem with a software like approach enabling 1000x more designers that develop useful market relevant ASIC’s
ES3-4: Toward Agile, Intelligent and Open-Source Design Automation of Digital, Analog and Mixed-Signal ICs
Bio: David Z. Pan received his Ph.D. degree in Computer Science from UCLA in 2000. From 2000 to 2003, He worked at IBM Watson Research Center, developing VLSI design automation tools. He is currently Silicon Laboratories Endowed Chair in Electrical Engineering at UT Austin. His research interests include bidirectional AI and IC interactions, electronic design automation, design for manufacturing, hardware security, and CAD for emerging technologies. He has published over 420 refereed journal/conference papers and 8 US patents. He has served in many journal editorial boards and conference committees, including various leadership roles. He has received many awards, including SRC Technical Excellence Award and 20 Best Paper Awards from major VLSI/CAD venues, etc. He is a Fellow of ACM, IEEE and SPIE.
Abstract: This tutorial will present some recent results and trends toward agile, intelligent, and open-source design automation for digital/analog/mixed-signal ICs, in particular how to leverage AI with domain-specific customizations for IC design. It first shows how to leverage deep learning hardware and software to develop an open-source VLSI placement engine, DREAMPlace, which is around 40x faster than the previous state-of-the-art academic placer. DREAMPlace 2.0 and 3.0 have been further developed to tackle detailed placement and region constraints. DREAMPlace has also been applied to macro placement together with reinforcement learning. It then presents MAGICAL which leverages both machine and human intelligence to produce fully automated analog layouts from netlists to GDSII, including automatic layout constraint generation, placement, and routing. MAGICAL 1.0 has been open-sourced, and validated with a silicon-proven 40nm 1GS/s ∆Σ ADC. It will further discuss the new MAGICAL capability, OpenSAR for end-to-end SAR ADC compilation, as well as other research trends.
Educational Session 4: High Speed Link Design
Sunday, 24 April 2022, 9:00 am-4:45 pm PDT
Session Chairs: Tod Dickson, IBM Watson, USA & Xiang Gao, Zhejiang University, China
ES4-1: Architectural Considerations in 100+ Gbps Wireline Transceivers
Bio: Tony Chan Carusone has been a faculty member at the University of Toronto since completing his Ph.D. there in 2002. He has co-authored eight award-winning papers on chip-to-chip and optical communication circuits, ADCs, and clock generation. He has also been a consultant to industry since 1997. He is currently the Chief Technology Officer of Alphawave IP in Toronto, Canada.
Dr. Chan Carusone was a Distinguished Lecturer for the IEEE Solid-State Circuits Society 2015-2017 and served on the Technical Program Committee of the International Solid-State Circuits Conference from 2015-2021. He co-authored the latest editions of the classic textbooks “Analog Integrated Circuit Design” along with D. Johns and K. Martin, and “Microelectronic Circuits” along with A. Sedra and K.C. Smith. He has served as Editor-in-Chief of the IEEE Transactions on Circuits and Systems II: Express Briefs, an Associate Editor for the IEEE Journal of Solid-State Circuits, and is now Editor-in-Chief of the IEEE Solid-State Circuits Letters. He is a Fellow of the IEEE.
Abstract: Progress in computation and communication is increasingly bottlenecked by integrated circuit I/O. Different applications require very different high-speed links. Co-packaged dies communicate via mixed-signal transceivers with power consumption below 1pJ/bit. Much of the power in such within-package links is consumed by clock distribution, whose key performance specs are reviewed in the first part of this presentation. For links between packaged ICs, technology scaling favors transceivers comprising analog front-ends, data converters, and a large custom DSP. Thus, the second part of this presentation summarizes key background on DSP-based transceivers. The interactions between the analog front-end, equalization, timing recovery, and forward error correction are emphasized. Although often neglected, these interactions impact BER, and thus transceiver design, significantly.
ES4-2: Clocking for Serial Links ‒ Frequency and Jitter Requirements, Phase-Locked Loops, Clock and Data Recovery
Bio: Saurabh Saxena received his B.Tech. degree in electrical engineering and the M.Tech. degree in Microel-ectronics and VLSI design from IIT Madras, Chennai, India, in 2009. He received his Ph.D. degree in Electrical and Computer Engineering from University of Illinois at Urbana-Champaign in 2015. He is currently an Assistant Professor with the Department of Electrical Engineering, IIT Madras. His research group is developing circuits for low power, energy proportional and wide range, and full-duplex multi-Gbps serial links. The group also designs clock generators and serial links for Indian Space Research Organization. Dr. Saxena has been the recipient of Early Career Research (ECR) award and Visvesvaraya young faculty research fellowship (YFRF) awarded by GoI.
Abstract: The frequency and phase requirements of the clock for transmitting high-speed data and sampling the received signal are application-dependent. A low bit error rate and increased channel loss limit the transmitting clock’s timing jitter at multi-Gbps transmission. In multi-hop serial links with embedded clock, jitter tracking bandwidth for the sampling clock and jitter generation bandwidth for the recovered clock should be decoupled for an energy-efficient receiver. The wide range of data rates and referenceless clock recovery adds to the design complications. Multilane high-speed SERDES operate at similar data rates but require an independent phase tracking for each lane during clock and data recovery. A centralized frequency tracking and localized phase tracking for the sampling clock come with challenges of multiphase clock distribution and large power consumption in the former. This tutorial discusses jitter requirements for the transmitter side clock in the presence of channel loss, basics of clock generation in a phase-locked loop, standard analog and digital CDRs, and CDRs for a wide range of data rates and multilane receivers.
ES4-3: Equalization, Architecture, and Circuit Design for High-Speed Serial Link Receiver
Bio: Gain Kim received the B.S., M.S., and Ph.D. degrees in Electrical Engineering from the Ecole Polytechnique Federal de Lausanne (EPFL), Lausanne, Switzerland in 2013, 2015, and 2018 respectively. From 2016 to 2018, he was with IBM Research Zurich, working on ADC-based wireline receiver designs. From 2018 to 2020, he was with KAIST as a postdoctoral fellow. From Nov. 2020 to Jan. 2022 he was with Samsung Research, Seoul, South Korea, as a staff engineer working on a baseband modem for 6G wireless communications. In Jan. 2022, he joined Daegu Gyeongbuk Institute of Science & Technology (DGIST), Daegu, South Korea, where he is currently an assistant professor. His current research interests include the design of high-speed ADC, modulation techniques for ADC-based serial links, as well as multi-chip computing systems with energy-efficient interfaces.
Abstract: Ever-increasing demands on higher communication bandwidth among connected devices with limited power budgets push the serial link transceivers to their performance limit. While the channel is often time partially equalized on the transmitter side, most heavy equalizations are typically performed on the receiver side. The architecture of high-speed wireline transceivers varies depending on applications. This talk provides fundamentals of equalization techniques, an overview of various receiver architectures and key building blocks of the equalizer’s data-path such as analog front-end, continuous-time linear equalizer, decision-feedback equalizer. Modern ADC-based receivers with DSP-equalizer operating at >56Gb/s and beyond for mid-to-long-reach applications will also be discussed, including the ADC techniques and DSP architecture.
ES4-4: Transmitter Design for High-speed Serial Data Communications
Bio: Jihwan Kim received his B.S. degree in electrical and computer engineering from Hanyang University, Seoul, Korea in 2005 and the M.S. and the Ph.D. degrees from Georgia Institute of Technology, Atlanta, GA, USA in 2007 and 2011, respectively. His doctoral research focused on designing high-performance RF and mm-wave front-end integrated circuits and systems such as power amplifiers, low-noise amplifiers mixers, voltage-controlled oscillators, and a W-band direct-conversion receiver using CMOS/SiGe technologies. Since 2011, he has been with Intel’s Advanced Design in Design Enablement located at Hillsboro, OR, USA, working on designing integrated circuits and systems for ultra high-speed and low-power wireline data communications. He has contributed to develop 112/224Gb/s long-reach PAM-4 SerDes PHY focusing on designing high-performance transmitters.
Abstract: The ultra high-speed wireline transmitter is one of essential circuit systems that enable high-bandwidth serial data communication. Strong demands in high performance computing, networking and communication, and most recently AI processing require the serial IO interface to be capable of handling 100+Gb/s data-rate per lane with strict power budget. In this education session, basics of serial transmitters are introduced to help audience understand technical requirements and specific design targets of high performance and low power transmitter for serial data communication using state-of-the-art CMOS process technologies. Moreover, trends and important design techniques for 100-200Gb/s CMOS transmitters are explored, which includes feed-forward equalization (FFE) techniques, data-path and driver design, digital-to-analog converter (DAC) based architecture, output matching technique, and low-jitter clock distribution.