CICC 2024 Educational Sessions
Educational Sessions
Sunday, 21 April
9:00 am-4:45 pm
Educational Session 1: Deep Learning and Compute-in-Memory Designs and Applications
Session Chairs: Weiwei Shan Southeast University, China and Yongpan Liu, Tsinghua University, China
Naresh Shanbhag, University of Illinois at Urbana-Champaign, USA
Bio: Naresh R. Shanbhag is the Jack Kilby Professor at the University of Illinois at Urbana-Champaign. He received his Ph.D. degree from the University of Minnesota, then worked at AT&T Bell Laboratories in 1995. His research focuses on energy-efficient systems for machine learning, communications, and signal processing, spanning algorithms, VLSI architectures. He has more than 200 publications and 13 US patents.
Title: Fundamentals of In-memory Computing
Abstract: Since its inception in 2014, in-memory computing (IMC) design has become an active area of research in the integrated circuits and architecture communities. IMC addresses the energy and latency costs of memory accesses dominating AI workloads by transforming the conventional memory accesses into one that computes functions of data in the memory core. As a result, today, IMCs have attained state-of-the-art energy efficiency. This talk will provide an overview of IMCs, describe various IMC design principles and architectures, review current trends via data-driven extensive benchmarking of IMC chip prototypes, and identify future opportunities and challenges in deploying IMCs at scale in emerging applications.
Pritish Narayanan, IBM, Almaden, USA
Bio: Dr. Pritish Narayanan is Principal Research Scientist at IBM, where he has led multiple AnalogAI accelerator designs. He is an Associate Editor for IEEE Transactions on Electron Devices and an IEEE Senior Member. He has authored >100 research publications and presented several keynote, tutorial and invited talks at international conferences.
Title: Circuit and Architectural Challenges for Analog In-Memory Compute
Abstract: The recent success of Transformer-based language models has been driven by very large model sizes, tremendously increasing compute, memory and energy requirements of neural networks. Fully connected layers that dominate Transformers can be mapped to Analog non-volatile memory, implementing ‘weight-stationary’ architectures with in-place multiply-and-accumulate computations and reduced off-chip data transfer, offering significant energy benefits. I will review key challenges for analog in-memory computing, including device, circuit, architecture and algorithmic aspects highlighting IBM’s cross-layer AnalogAI research.
Mingoo Seok, Columbia University, USA
Bio: Mingoo Seok is an Associate Professor of Electrical Engineering at Columbia University. His research interest covers various aspects of VLSI hardware, including low-power variation-tolerant hardware, machine-learning hardware, and on-chip power management. He is the Solid-State Circuits Society (SSCS) distinguished lecturer.
Title: SRAM-based In-Memory Computing Hardware: Analog vs Digital and Macros to Microprocessors
Abstract: SRAM-based in-memory computing (IMC) hardware has received significant research attention for its massive energy efficiency and performance boost. In this session, we will introduce several recent macro prototypes which achieve state-of-the-art performance and energy efficiency yet leverage different computing mechanisms ranging from current-based, to charge-based, and fully digital. After this macro-level introduction, we will introduce recent microprocessor prototypes that employ IMC-based accelerators, which can perform on-chip inferences at high energy efficiency and low latency.
Hongyang Jia, Tsinghua University, China
Bio: Dr. Hongyang Jia is an assistant professor of Electronic Engineering at Tsinghua University, Beijing, China. He received his Ph.D. degree from Princeton University, Princeton, NJ, USA, in 2021. From 2021 to 2022, he was with the NVIDIA as a Research Post-doctorate. His research focuses on advanced computing concepts and their integration with emerging applications, such as robotics and security.
Title: Architecture and System Integration of In-memory Computing: Programmability, Scalability and Functionality beyond Matrix Multiplication
Abstract: Recent research on in-memory computing (IMC) circuits provides multiple memory technologies and computing schemes for building energy-efficient systems. This talk will provide an integrated view of different IMC approaches and traditional spatial architectures. Based on the architectural abstraction, we will discuss the challenges and practices of integrating IMC with processors and systems at scale. Finally, we will introduce recent prototypes focusing on functions and metrics other than matrix-vector multiply and peak energy efficiency.
Educational Session 2: Introduction to Universe of Quantum Computing and Beyond
Session Chair: Siddharth Joshi
Quantum computing is anticipated to offer groundbreaking solutions to some of today’s unsolvable problems and is projected to become operational in near future. In this session, we will introduce Quantum Computing as an implementation framework of Ising Machine, providing a perspective on Quantum Computing as a part of the broader computational universe.
We’ll then delve into the fundamental principles of quantum computing algorithms and operations. Superconducting qubit is widely used approach today to realize Quantum Computer, however, it requires cryogenic environment and the control and read-out hardware has significant challenges to overcome. We will discuss the latest implementation breakthrough and trends.
Prof. Ali Sheikholeslami, University of Toronto, Canada
Bio: Ali Sheikholeslami is a professor of Electrical and Computer Engineering at the University of Toronto, Canada, with research interest in the areas of analog and digital circuit design, high-speed signaling, and hardware annealing for accelerated optimization and sampling. He has co-authored over 100 publications and a graduate-level textbook entitled “Understanding Jitter and Phase Noise”. He is the author of a regular column series in the Solid-State Circuits Magazine entitled “Circuit Intuitions” and the organizer of a regular event for the Solid-State Circuits Society entitled “Circuit Insights”. He currently serves as the Education Chair for the ISSCC and as the Vice President of Education for the Solid-State Circuits Society.
Title: Ising Machine: An Intersection of Quantum and Classical Annealing
Abstract: An Ising machine is a computational device designed to solve optimization and sampling problems by physically implementing the Ising model, a mathematical model used in statistical mechanics to describe magnetic systems. At its core, the Ising model involves spins on a lattice that can take +1 or -1 values, with the system’s energy determined by the interactions between neighboring spins and an external magnetic field. Ising machines exploit this setup to map complex optimization problems onto the problem of finding the minimum energy configuration of a simulated or physical spin system.
Ising machines are effective in both quantum and classical annealing. In quantum annealing, they utilize quantum bits (qubits), allowing for a vast parallel exploration of possible solutions through quantum superposition and entanglement. On the classical side, they often employ parallelism in hardware and stochastic moves to mimic the behavior of spins in the Ising model. These classical systems can efficiently simulate the dynamics of large networks of spins and overcome the physical limitations of their counterparts in quantum hardware. Also, central to their operation are annealing techniques which enable a systematic energy minimization and facilitate the discovery of optimal solutions via controlled stochastic search. The versatility of Ising machines, capable of operating within both quantum and classical paradigms, makes them a powerful tool for a wide range of applications, from logistics optimization to drug discovery, materials science, and machine learning.
Prof. Hiu Yung Wong, San Jose State University, USA
Bio: Hiu Yung Wong is an Associate Professor at San Jose State University. He received his Ph.D. degree in Electrical Engineering and Computer Science from the University of California, Berkeley in 2006. From 2006 to 2009, he worked as a Technology Integration Engineer at Spansion. From 2009 to 2018, he was a TCAD Senior Staff Application Engineer at Synopsys.
He received the Curtis W. McGraw Research Award from ASEE Engineering Research Council and Silicon Valley AMDT Endowed Chair Award in 2022, the NSF CAREER award and the Newnan Brothers Award for Faculty Excellence in 2021, and Synopsys Excellence Award in 2010. He is the author of the book, “Introduction to Quantum Computing: From a Layperson to a Programmer in 30 Steps”. He is one of the founding faculty of the Master of Science in Quantum Technology at San Jose State University.
His research interests include the application of machine learning in simulation and manufacturing, cryogenic electronics, quantum computing, and wide bandgap device simulations. His works have produced 1 book, 1 book chapter, more than 100 papers, and 10 patents.
Title: Introduction to Quantum Computing: from Algorithm to Hardware
Abstract: Quantum computing is expected to change the world by providing exponential speed-up in solving some very difficult problems. In this tutorial, we will first discuss the fundamental principles of quantum computing algorithms and examples. Error correction, which is indispensable for realizing a fault-tolerant quantum computer, will be briefly covered. Then, using the superconductor-based quantum computer as an example, we will study how to implement operations in quantum computers, namely, qubit initialization, readout, and manipulations. It will be appreciated that powerful classical computers, which are used to control the qubits, are essential to the successful implementation of quantum computers. Finally, we will demonstrate how to use Qiskit-Metal and HFSS to optimize a quantum circuit in terms of the Energy Participation Ratio.
Dr. Sushil Subramanian, Intel, USA
Bio: Sushil Subramanian received the B.Tech. degree in electronics and electrical communication engineering from Indian Institute of Technology, Kharagpur, India, in 2009, and the M.S. and Ph.D. degrees in electrical engineering from the University of Southern California, Los Angeles, CA, USA, in 2017, where he worked on fast hopping frequency synthesizers and interference tolerant receivers. He is currently with Intel Labs, Intel Corporation, Hillsboro, OR, USA, where he works on integrated circuits and systems for qubit control in quantum computers.
Title: Principles and Cryo-CMOS Control of Spin Qubit based Quantum Computers
Abstract: Quantum computing offers a potential solution for problems intractable by classical computing. A large number of qubits, the fundamental units of quantum information, have to be controlled precisely for implementing practical applications, thereby posing challenging scalability requirements on all layers of the quantum computing stack. Spin qubits present a scalable solution on the device level, due to their ease of integration and better compatibility with industrial silicon manufacturing processes. Furthermore, large-scale spin qubit control requires closer integration of control electronics to qubits operating at deep-cryogenic temperatures. In this talk, we will explore spin qubit physics and operation, and discuss various methods for spin qubit control and readout. We will then introduce integrated cryo-CMOS circuits for scalable control and present details of recent advances in cryo-CMOS qubit-controller chips and SOCs.
Sudipto Chakraborty, IBM, USA
Bio: Sudipto Chakraborty (B.Tech, IIT, 1998, Ph.D, GaTech, 2002) worked at TI (2004-2016) and IBM research (2017-). He has authored or co-authored > 80 papers, 2 books, 90 US patents. He serves in the TPC of ISSCC, CICC, IMS and is an IBM master inventor and DL for CASS and SSCS.
Title: Cryo-CMOS Quantum-Classical Interfaces to Quantum Processors: from a Wild Idea to Working Silicon
Abstract: The core of a quantum processor is generally an array of qubits that need to be controlled and read out by a classical processor. This processor operates on the qubits with nanosecond latency, several millions of times per second, with tight constraints on noise and power dissipation. This is due to the extremely weak signals from the processor that require highly sensitive circuits and systems, along with very precise timing capability. We advocate the use of CMOS technologies to achieve these goals, whereas the circuits will be operated at deep-cryogenic temperatures. We believe that these circuits, collectively known as cryo-CMOS control, will make future qubit arrays scalable, enabling a faster growth in qubit count. In this session, the challenges of modeling, designing, and operating complex circuits and systems at 4K and below will be outlined, along with preliminary results achieved in the control and read-out of qubits by ad hoc integrated circuits that were optimized to operate at low power in these conditions. We will conclude with a perspective on the field and its trends.
Educational Session 3: Optical and Wireline Communication Circuit Techniques
Session Chairs: Armin Tajalli, University of Utah, USA and Sudipto Chakraborty, IBM, USA
Massive data movement turns out to be a critical aspect of the modern communication and computing industry. Most advanced applications, such as wireless 5G/6G communications, massive Multi-Input Multi-Output (MIMO) systems, complex machine learning and artificial intelligence training and inference algorithms, all required data transfer rates orders of magnitude higher than what is achievable by today’s industry. As a result, a new approach to solve the problem of data movement is required. In addition to the conventional high-bandwidth electrical and optical links, there is a new trend to combine the two approaches to achieve the desired data rate at a very low level of energy consumption. This education session will provide a comprehensive background on design aspects of both electrical and optical links, and present some recent advancements in the field. Topics such as 200 G+ electrical links (Dr. Liu), optical communication systems and silicon photonics (Dr. Raj) and a comparative study of electrical and optical links (Prof. Palermo) is part of this education session.
Cathy Liu, SerDes architect, Broadcom Inc., USA
Bio: Cathy Ye Liu, distinguished Engineer, currently heads up Broadcom SerDes architecture and modeling group. Since 2002, she has been working on high-speed transceiver solutions. Previously she has developed read channel and mobile digital TV receiver solutions. Her technical interests are signal processing, FEC, and modeling in high-speed optical and electrical transceiver solutions. She has published many journal articles and conference papers and holds 20+ US patents. Cathy has demonstrated her leadership roles in industry standard bodies and forums. Cathy currently serves as the vice president of the board director of Optical Internetworking Forum (OIF), a member of the board of advisors for the department of Electrical & Computer Engineering (ECE) of University of California at Davis, a member of Signal Integrity Journal editorial advisory board, and the co-chair of the DesignCon technical track of high speed signal processing, equalization and coding. She received DesignCon 2021 engineer of the year award. She received her B.S. degree in Electronic Engineering from Tsinghua University, China and received her M.S. and Ph.D. degrees in Electrical Engineering from University of Hawaii.
Title: The Latest High Speed Wireline SerDes Technology
Abstract: With the growth of 5G/6G system, data center and AI computing, we need faster connectivity to meet the increasing bandwidth. To meet the next-generation system bandwidth requirement, industry and standard bodies like IEEE802.3 and OIF PLL recently kicked off new projects aiming at 200+ Gbps link rate or higher. So what comes next 200+ Gbps per lane for electrical and optical interfaces and SerDes technologies? How to achieve trade-off between performance and power/latency cost? This education session will start with system requirements, needs and gaps for 200+ Gbps system, followed by challenges and solutions for SerDes architecture and implementation.
Mayank Raj, AMD, USA
Bio: Mayank Raj received the B.Tech. degree from Indian Institute of Technology (IIT), Kanpur, India, in 2008, and the M.S. and Ph.D. degrees from the California Institute of Technology (Caltech), Pasadena, CA, USA, in 2009 and 2014, respectively, all in electrical engineering.
In 2014, he joined Xilinx Inc. (now AMD), San Jose, CA, where he is a Sr. Design Manager and works on high-performance mixed-signal integrated circuits for high-speed and low-power electrical and optical interconnects.
Dr. Raj is the recipient of the 2008 Caltech Atwood Fellowship and the 2015 CICC Best Student Paper Award. He holds more than 20 U.S. patents. He was a member of the CICC technical program committee from 2017 to 2023.
Title: Design of Silicon photonics based high throughput optical transceivers.
Abstract: Emerging applications such as machine learning, high-performance computing, and cloud storage continue to push compute demands at the data center. To keep up, distributed computing architectures are increasingly adopted where the physical locations of the CPU, GPU, FPGA, memory, and storage may span over several meters. In package Si-Photonics-based optical link with wavelength division multiplexing (WDM) and non-return-to-zero (NRZ) signaling provides a power efficient, high-bandwidth, and low-latency interface between these components. In this presentation, design of a co-packaged, low-power, high-throughput, silicon photonics-based optical transceiver is presented. In the Electrical IC (EIC), we discuss the design of a high-sensitivity, high-speed receiver (RX) as well as a low-power transmitter (TX) driver. In the Photonic IC (PIC), the design of high-speed and low-loss optical modulators and filters is presented. Wavelength division multiplexing (WDM) based link architecture is described and design choices are discussed.
Gerald Pasdast, Intel USA
Bio: Gerald Pasdast is a Senior Principal Engineer in the central IP team, where he leads the development of die-to-die (D2D) IO architecture and technology. He has developed several proprietary D2D PHY’s running on both standard and advanced packages including EMIB (2.5D) and Foveros (3D chip stacking), which have been productized on server/HPC, graphics and client CPUs. Prior to that he designed off-package IO PHY IPs including GDDR5, LVDS and GTLIO as well as design of PLLs and other analog building blocks. Most recently, Gerald co-authored the Universal Chiplet Interconnect express (UCIe) specification and serves as a co-chair of the UCIe consortium Form Factor and Compliance WG. Gerald earned a bachelor’s in electrical engineering, BSEE, from San Jose State University in 1996. He has a total of 58 granted + filed patents and has co-authored 6 technical journal papers.
Title: Interconnect for the chiplet era: circuit techniques and standards
Abstract: Gordon Moore, in 1965, predicted “It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.” As more board-level functionality has moved onto System On Chip (SOC) architectures, the SOC’s themselves are now rapidly moving toward chiplet-based construction. Chiplets are individual silicon die building blocks that, when interconnected, form fully functional and complete SOCs. There are many advantages for chiplets including higher yields, lower cost, heterogeneous construction, and generational re-use for maximizing ROI. The bandwidth demand for the interconnect can often be in double-digit TB/s, which demands interconnect PHYs with extremely high linear and areal bandwidth density and at least a 10x increase in power efficiency when compared to off-package PHYs. Another key requirement will be standardization of the interconnect to foster a future chiplet ecosystem. We will cover the various categories of die-to-die (D2D) interconnect PHYs & circuits as well as the importance of D2D standardization and the components entailed.
Sam Palermo, Texas A&M University, USA
Bio: Samuel Palermo received the Ph.D. degree in electrical engineering from Stanford University. In 2009, he joined the Electrical and Computer Engineering Department of Texas A&M University where he is currently a professor. His research interests include high-speed electrical and optical interconnect architectures, RF photonics, and high performance clocking circuits.
Title: Transceiver Architectures for Future System Interconnect Demands
Abstract: Future high-throughput systems will require significant increases in both inter-package and intra-package interconnect bandwidth. Current electrical SERDES transceivers are operating in excess of 200Gb/s for communication inside server racks and from large switch chips to optical modules, but there are open questions on how to scale to higher data rates. Longer reach signaling is possible with optical transceivers that have traditionally been pluggable modules, but are now migrating inside the package to more efficiently meet interconnect bandwidth requirements. Finally, the rise of chiplet-based architectures necessitates energy-efficient die-to-die transceivers that achieve very high bandwidth density. This talk gives an overview of state-of-the-art transceiver design techniques across this spectrum of interconnect systems.
Educational Session 4: Nascent Sensing Devices and Interfaces
Session Chairs: Constantine Sideris, University of Southern California, USA and Kyeongha Kwon, KAIST, South Korea
Minkyu Je, Korea Advanced Institute of Science and Technology, South Korea
Bio: Minkyu Je received M.S. and Ph.D. degrees in electrical engineering and computer science from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 1998 and 2003, respectively.
In 2003, he joined Samsung Electronics, Giheung, Korea, as a Senior Engineer and worked on multi-mode multi-band RF transceiver SoCs for GSM/GPRS/EDGE/WCDMA standards. From 2006 to 2013, he was with the Institute of Microelectronics (IME), Agency for Science, Technology and Research (A*STAR), Singapore. He worked as a Senior Research Engineer from 2006 to 2007, a Member of Technical Staff from 2008 to 2011, a Senior Scientist in 2012, and a Deputy Director in 2013. From 2011 to 2013, he led the Integrated Circuits and Systems Laboratory at IME as a Department Head.
Title: Capacitance-to-Digital Converters (CDCs), Interfacing with Capacitive Sensors
Abstract: With the rise of the Internet of Things (IoT) and the proliferation of wearable smart devices, the demand for diverse sensor systems has surged significantly. Many environmental and biomedical sensor systems rely on sensors that convert physical quantities into outputs such as capacitance, resistance, voltage, or current. Notably, capacitive sensing transducers are extensively utilized for IoT applications due to their favorable attributes of low noise and reduced temperature sensitivity. Various capacitive sensors find a broad application range in sensing various physical quantities, such as pressure, humidity, acceleration, gas molecules, and proximity. To read out from such capacitive sensors and extract useful information, proper interface circuits or capacitance-to-digital converters (CDCs) need to be accompanied. Despite well-established studies and ongoing active research on CDCs, there are challenges caused by design tradeoffs among various performance parameters, including energy efficiency, sensing resolution, and input range. In this talk, the basic principles of capacitive sensors, design goals and tradeoffs of CDCs, and traditional CDC circuit structure will be reviewed first. Then, more recent and advanced circuit structures and design techniques proposed to improve energy efficiency, sensing resolution, and input range will be introduced. Also, we will discuss the future research direction of the CDC design and application.
Massimo Alioto, National University of Singapore, Singapore
Bio: Massimo Alioto is a Professor at the National University of Singapore, where he leads the Green IC group and the Integrated Circuits and Embedded Systems area. Previously, he held positions at the University of Siena, Intel Labs, University of Michigan Ann Arbor, University of California, Berkeley, and EPFL.
He has authored more than 350 publications and six books with various best paper award (e.g., ISSCC, ICECS). Among the others, he is/was the Editor in Chief of the IEEE Transactions on VLSI Systems, Deputy EiC of IEEE JETCAS, Chair of the IEEE CASS Distinguished Lecturer Program, and ISSCC TPC member. Prof. Alioto is an IEEE Fellow.
Title: Highly Power-Scalable Circuits for Purely-Harvested Sensing Systems down Well Below Leakage
Abstract: In this tutorial, key ideas and state-of-the-art silicon demonstrations of circuit techniques for purely-harvested systems without energy storage are introduced for aggressive form factor and cost reductions, as well as for unrestricted lifespan.
Highly power-scalable sub-systems and systems with adaptation to the highly-fluctuating power profile of energy harvesters are discussed. Circuit concepts and silicon demonstrations with aggressive power scaling by orders of magnitude are presented. Circuit techniques and silicon examples with power well below transistor leakage are also introduced.
Ample coverage of common sub-systems of systems is provided from power management, to sensor interfaces and wireless communications, as exemplified by numerous silicon demonstrations and ultimately their system integration.
Mehdi Javanmard, Rutgers University, USA
Bio: Mehdi Javanmard is the Paul and Mary Monroe Faculty Fellow Professor in the Electrical and Computer Engineering Department at Rutgers University. He received the BS (2002) from Georgia Institute of Technology and the MS (2004) and PhD (2008) all in electrical engineering from Stanford University. During his time at Stanford, he worked on the development of electronic microfluidic platforms for low-cost genomic and proteomic biomarker detection, and later worked as a Senior Research Engineer at the Stanford Genome Technology Center. In 2014, he joined the Electrical and Computer Engineering Department, Rutgers University as an Assistant Professor. His research interests include developing portable and wearable technologies for continuous health monitoring and understanding the effects of the environment on health. In 2017, he was recipient of the Translational Medicine and Therapeutics Award by the American Society for Clinical Pharmacology and Therapeutics for his group’s work in point of care diagnostic tools for assessing patient response to cancer therapies. He has received various awards as a Principal Investigator from the National Science Foundation, National Institutes of Health, DARPA, and the PhRMA foundation to support his research. He was awarded the National Science Foundation CAREER Award for young faculty in 2019 and the DARPA Young Faculty Award in 2020. In 2018, he co-founded RizLab Health, a venture capital funded startup company dedicated to enabling point-of-care hematology analysis.
Title: Micro- and Nanoscale Electro-fluidics: From Basic Research to Translational Medicine
Abstract: In this talk, I will discuss my group’s work on fabricating micro- and nanosensing platforms for health monitoring. My group has developed novel electronic sensing modalities and has demonstrated their use for both in vitro with human clinical samples and in vivo in animals. In the first part of my talk, I will discuss sensor fabrication, characterization, and benchmarking against the gold standard, along with the role that these sensors can play in monitoring various chronic and acute inflammatory conditions. I will also discuss a new class of wirelessly powered nanobiosensors for immune monitoring. Finally, I will discuss challenges in translation of biosensing and microfluidic technologies beyond the lab, my personal experience, and potential solutions.