The forums are special sessions of invited papers.
Monday, April 24
9:30 am-11:30 am
Ultra High-Speed Data Converters
Session Chairs: Jintae Kim, Konkuk University, Korea and Yong Liu, Broadcom, USA
Title: Data Converters for 200+Gbps Wireline Links and Transceivers
Abstract: High density wireline communication inside Mega Scale Data Centers is approaching a major crossroads after 112Gbps data rate. The tremendous demand in bandwidth growth inside data centers are calling for doubling the data rate every 2~3 years. Co-packaged optics remains to be an unviable solution inside switches and ASICS, SERDES circuit designers will need to build electrical 224Gbps and beyond data rates which requires technological advancement in all key technology elements of the ecosystem. DSP based transceivers present are the only viable solution to reach those data rates. In this presentation we will focus data converters: ADCs and DACs that make those transceivers possible; Analog circuit techniques, calibration and equalization DSP needed to run links at 224Gbps and beyond.
Tamer Ali, MediaTek, USA
Bio: Tamer Ali is Sr. director of technology in MediaTek, Irvine, CA, where his team develops the next generation serdes for data centers, AI, and 5G infrastructure applications. He had his Bsc. and MSc. in Ain Shams University, Cairo, Egypt in 2000 and 2005, respectively. He had his Phd. from UCLA, Los Angeles, CA in 2012. His research interests include RF circuits, high speed mixed signal, circuits, high speed ADCs and DACs, and clock distribution circuits. Tamer holds many IEEE publications and more than 40 US and international patents.
Title: High-Speed DAC Design in 4nm FinFET for 200+ Gb/s Wireline Transmitters
Abstract: DAC-based transmitters have become common in wireline communication links, as they ease the high-speed analog design for transmitters requiring high number of FFE taps. Moreover, DACs provide flexibility to support wide variety of higher-order digital modulation formations in both the time as well as frequency domain. In this talk, we will review the design of a 72-GS/s 8b DAC in 4nm FinFET CMOS. The segmented DAC architecture employs source-series terminated (SST) drivers with a hybrid analog/digital tuning approach in the LSB segments to overcome minimum device-size limitations that can hinder the effectiveness of pure digital tuning for SST-based DACs. This segmentation approach, combined with the use of a single-ended LSB, is key to reducing the number of driver segments in order to minimize driver self-loading and maximize analog output bandwidth. A technique to mitigate uneven driver switching activity in thermometer-encoded DAC MSB segments is presented, which reduces worse-case electromigration currents and improves thermal matching in DAC segments particularly when OFDM modulation is applied. Measurements show well-matched MSB/LSB DAC segments with -0.63/0.67 LSB INL and -0.16/0.43 LSB DNL. Time domain modulation of 216Gb/s PAM8 and frequency domain modulation of 212Gb/s OFDM are reported, demonstrating the capability of CMOS DACs to support frequency domain modulation for wireline applications. The TX consumes 288mW from a 0.95V power supply.
Tod Dickson, Senior Research Scientist, IBM T.J. Watson Research Center, USA
Bio: Timothy (Tod) Dickson received the B.S. and M.Eng. degrees from the University of Florida, and the Ph.D. degree from the University of Toronto. Since 2006, he has been with the IBM T.J. Watson Research Center where he is currently a Senior Research Scientist working in the area of high-speed SerDes for server and networking applications. He is also an Adjunct Professor at Columbia University, where he has taught graduate level courses in analog and mixed-signal integrated circuit design since 2007.
Dr. Dickson has been a recipient or co-recipient of several best paper awards, including the Best Paper Award for the 2009 IEEE Journal of Solid-State Circuits, the Beatrice Winner Award for Editorial Excellence at the 2009 ISSCC, the Best Paper Award at the 2015 IEEE Custom Integrated Circuits Conference (CICC), and the Best Student Paper Award at the 2004 Symposium on VLSI Circuits. He is an Associate Editor for the IEEE Solid-State Circuits Letters, and also currently serves on the CICC Technical Program Committee. In 2019-2020, he served as a Distinguished Lecturer for the IEEE Solid-State Circuits Society. He is a Senior Member of the IEEE.
Title: Precision Clocking for High-Speed Data Converters
Abstract: Precise clocking is a key but often overlooked element of high-speed data converter design. Jitter introduced by clock distribution and delay buffers consume a significant fraction of overall power and regularly limit high-frequency performance. Thus, we begin with a quantitative analyses of the main sources of jitter in clocking circuits: power supply induced jitter, jitter generation, and jitter amplification. We proceed to consider design guidelines for clock distribution and tunable delay buffers. Following these guidelines can simultaneously reduce power supply noise sensitivity and power consumption of the clock distribution circuits. The guidelines are illustrated by simulations and measurements of 16-nm FinFET clock distribution networks.
Tony Chan Carusone, University of Toronto, Canada
Bio: Dr. Tony Chan Carusone has taught and researched integrated circuits and systems in academia and industry for over 20 years. He has been a faculty member at the University of Toronto since completing his Ph.D. there in 2002. He and his graduate students have received eight best-paper awards at leading conferences for their work on chip-to-chip and optical communication circuits, analog-to-digital conversion, and precise clock generation. He has also been a consultant to industry since 1997, and in 2022 became the Chief Technology Officer of Alphawave Semi in Toronto, Canada.
Dr. Chan Carusone was a Distinguished Lecturer for the IEEE Solid-State Circuits Society 2015-2017 and served on the Technical Program Committee of the International Solid-State Circuits Conference from 2015-2021. He has co-authored the latest editions of the classic textbooks “Analog Integrated Circuit Design” along with D. Johns and K. Martin, and “Microelectronic Circuits” along with A. Sedra and K.C. Smith. He was Editor-in-Chief of the IEEE Transactions on Circuits and Systems II: Express Briefs in 2009, an Associate Editor for the IEEE Journal of Solid-State Circuits 2010-2017 and is now Editor-in-Chief of the IEEE Solid-State Circuits Letters. He is a Fellow of the IEEE.
Title: High-speed D/A Conversion in FinFET CMOS Technology
Abstract: Digital-to-analog converters (DACs) are crucial building blocks in modern communication systems like wireline transceivers and digital mm-wave phased arrays. These applications drive steady increases in bandwidth, channel count, as well as integration density, which mandates data converters that are compatible with the latest CMOS technology. For analog-to-digital converters (ADCs), this has led to an architectural shift toward time-interleaved successive approximation, which exploits the strengths of modern CMOS while mitigating its weaknesses. On the other hand, DACs have not significantly changed since the 1970s and predominantly rely on the current steering topology.
In this Forum, we present State-of-the-Art DAC designs which use an alternative approach for high-speed (>10 GS/s), moderate-resolution (6-8 bit) digital-to-analog conversion, with the specific goals of reducing chip area and improving FinFET CMOS compatibility. These DACs use a switched capacitor (SC) architecture that separates the functions of level generation, timing/combining, and output power delivery, which are conventionally lumped into a single node.
Pietro Caragiulo, Stanford University, USA
Bio: Pietr0 Caragiulo pursued his Ph.D. degree in Electrical Engineering at Stanford University and Master and Bachelor degree at Politecnico di Bari. From 2010 to 2018, he was with the SLAC National Accelerator Laboratory, where he was involved in the development of high-frame-rate cameras and time-of-flight sensors. Dr. Caragiulo is the recipient of several awards, including the Stanford Graduate Fellowships (SGF) in Science and Engineering in 2018 and the ADI Outstanding Student Designer Award in 2020. He is currently a Silicon Research Scientist at Meta.
Tuesday, April 25
8:00 am-10:00 am
Recent Progress in LDOs and Voltage, Current, and Timing References
Session Chairs: Mahdi Kashmiri, Meta, USA and Ping-Hsuan Hsieh, National Tsing Hua University, Taiwan
Title: Recent Advancements in Integrated LDO Regulators
Abstract: Integrated low-dropout regulator (LDO) provides clean supply for a system on a chip, and provides design flexibility for better system energy efficiency. Recent LDO designs on longer restrict to analog control, but also embrace digital, switching, and hybrid control methods. In addition, people are using multiple distributed cooperating LDOs for high-current and large-area digital systems. This talk tries to cover the recent advancements in integrated LDO designs, will discuss the control loop and power stage design considerations.
Yan Lu, University of Macau, China
Bio: Yan Lu (Senior Member, IEEE) received the PhD degree from the Hong Kong University of Science and Technology (HKUST), Hong Kong, China, in 2014. Then, he joined the State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China, where he is currently an Associate Professor.
He has authored/coauthored more than 130 peer-reviewed technical papers and two books, and holds several US and CN patents. His research interests include highly integrated power converters and voltage regulators, wireless power transfer circuits and systems.
He is serving as a TPC Member for ISSCC and CICC, an IEEE SSCS Distinguished Lecturer for 2022-2023. Dr. Lu was a recipient/co-recipient of the IEEE Solid-State Circuits Society Pre-Doctoral Achievement Award 2013-2014, the IEEE CAS Society Outstanding Young Author Award in 2017, and the ISSCC 2017 Takuo Sugano Award for Outstanding Far-East Paper.
Title: Design of Ultra-low-power Bandgap Reference Circuits
Abstract: The voltage reference, as an essential block of a system, can be a nonnegligible player in energy management in battery-limited applications since it dissipates a static power even in power-down modes. Though the Vth-based CMOS-only references can achieve ultra-low-power consumption, they suffer from high sensitivity to process variations, inevitable cost for die-to-die trimming, and amplified uncertainty by up-scaling of a small reference voltage. For more stable approach at the cost of an increased power consumption, the bandgap reference (BGR) has been widely adopted to secure a well-defined untrimmed value (~1.15V) with strong immunity to process, supply and temperature changes. This talk reviews issues in the implementation of ultra-low-power circuits for BGR. Various circuit techniques to achieve nano-watt and sub-nano-watt consumption will be also presented.
Jae-Yoon Sim, POSTECH, Korea
Bio: Jae-Yoon Sim received the B.S., M.S., and Ph.D. degrees in electronic and electrical engineering from the Pohang University of Science and Technology (POSTECH), Korea, in 1993, 1995, and 1999, respectively.
From 1999 to 2005, he was a Senior Engineer with Samsung Electronics. In 2005, he joined POSTECH, where he is currently a Professor. Since 2019, he has been the Director of the Scalable Quantum Computer Technology Platform Center, which is an engineering research center nominated by the Ministry of Science and ICT of Korea. His research interests include sensor interface circuits, high-speed serial/parallel links, phase-locked loops, data converters, deep-learning accelerator, and quantum computing.
Dr. Sim was a co-recipient of the Takuo Sugano Award in 2001 and the Jan Van Vessem Award in 2023 from the IEEE International Solid-State Circuits Conference (ISSCC). In 2020, he received the Scientist of the Month Award from the Ministry of Science and ICT of Korea. He has been an IEEE Distinguished Lecturer and has served on the Technical Program Committees for the ISSCC, the IEEE Symposium on VLSI Circuits, and the IEEE Asian Solid-State Circuits Conference.
Title: Sub-μW Non-Bandgap Voltage References: Review & Recent Progress
Abstract: Internet-of-Things devices have miniaturized to a millimeter scale. Completely disconnected from an external power source, the electronics operate relying on a battery, or they are directly powered by a wireless power transfer technique. To recharge the energy storage device or perform assigned tasks under limited power, the power consumption of circuits integrated into the system must be minimized. A basic low-power technique is duty-cycling which turns off most components and keeps only essential circuits on in sleep mode. The always-on circuits continuously maintain the system operation and critically contribute to the overall system energy consumption since the sleep mode is significantly longer than the active mode. A voltage reference is one of the essential circuits in electronic systems, so the power must be minimized with other always-on circuits. This talk will review low-power non-bandgap voltage references by categorizing them and discuss recent progress in ultra-low-power voltage reference design that overcomes its major disadvantages.
Inhee Lee, University of Pittsburgh, USA
Bio: Inhee Lee is an assistant professor in the Electrical and Computer Engineering department at the University of Pittsburgh. Inhee Lee received his B.S. and M.S. degrees in electrical and electronic engineering from Yonsei University, South Korea, in 2006 and 2008, respectively, and a Ph.D. degree in electrical engineering from the University of Michigan in 2014. He was an assistant research scientist at the University of Michigan from 2015 to 2019. His research interests include adaptive, energy-efficient reference circuits, sensor interfaces, energy harvesters, power management circuits, machine learning accelerators, emerging memory interfaces, and Cryogenic-CMOS circuits. Dr. Lee is an IEEE senior member and has been serving as a TPC Member for VLSI Symposium, A-SSCC, and ISLPED. He is the recipient of the ACM MobiCom Best Paper Award.
Title: Recent Developments in RC Frequency References
Abstract: RC frequency references are getting better! By moving away from the classic relaxation oscillator and instead using frequency-locked loops (FLLs) and multi-resistor temperature compensation schemes, modern RC frequency references can achieve temperature coefficients of only a few ppm/C after a 2-point trim. In this talk, an overview of the current state-of-the-art in RC frequency references will be presented and some of the remaining challenges will be discussed.
Kofi Makinwa, Delft University of Technology, Delft, Netherlands
Bio: Kofi Makinwa is a Professor at Delft University of Technology, Delft, The Netherlands. His main research interests are in the design of mixed-signal circuits, sensors and sensor interfaces. This has resulted in 20 books, over 300 papers and over 35 patents. He is the co-recipient of 17 best paper awards, from the JSSC (2) and the ISSCC (5) among others. At the 70th anniversary of ISSCC, he was recognized as its top contributor. Prof. Makinwa has been on the program committees of several IEEE conferences, and has served the Solid-State Circuits Society as both a distinguished lecturer and as a member of its Adcom. He is a co-organizer of the Advances in Analog Circuit Design workshop (AACD) and the Sensor Interfaces Meeting (SIM). He is an IEEE Fellow and a member of the Royal Netherlands Academy of Arts and Sciences.
Tuesday, April 25
8:00 am-10:00 am
Emerging Electrical and Optical Devices for Biomedical Applications
Session Chairs: Youngcheol Chae and Yaoyao Jia
Title: Future of Neural Interfaces: Multimodal Experiments and Neuromorphic Computing
Abstract: The next leap in implantable neural interfaces requires technological advances in materials, devices, and computing paradigms. Holistic approaches integrating optical and electrical sensing modalities can overcome spatiotemporal resolution limits of neural sensing as well as open up new avenues for non-invasive neural recording. Integration of sensing, computation and memory on a single array can enable real-time processing of neural signals for compact, low-power and high-throughput brain machine interfaces. Here, we present this vision, its challenges, and discuss recent advances in the areas of transparent neural interfaces for multimodal recordings, neuromorphic approaches for on-chip neural processing and computational co-design at the system level for minimally invasive neural interfaces.
Duygu Kuzum, University of California, San Diego, USA
Bio: Duygu Kuzum received her Ph.D in Electrical Engineering from Stanford University in 2010. She is currently an Associate Professor in Electrical and Computer Engineering Department at University of California, San Diego. Her research focuses on development of nanoelectronic synaptic devices for energy-efficient neuro-inspired computing. Her group applies innovations in nanoelectronics to develop new technologies, which will help to better understand circuit-level computation in the brain. She is the author or coauthor of over 50 journal and conference papers. She was a recipient of a number of awards, including Texas Instruments Fellowship and Intel Foundation Fellowship, Penn Neuroscience Pilot Innovative Research Award (2014), Innovators under 35 (TR35) by MIT Technology Review (2014), ONR Young Investigator Award (2016), IEEE Nanotechnology Council Young Investigator Award (2017), NSF Career Award (2018), NIH NIBIB Trailblazer Award (2018), and NIH New Innovator Award (2020).
Title: All-Electrical Imaging of Cultured Cells with Semiconductor Sensor Arrays
Abstract: Biotechnology applications have increasingly turned to custom integrated circuits for massive parallelism in neural recording and DNA sequencing platforms. Yet many opportunities still remain to take advantage of the spatially-resolved nature of dense semiconductor platforms to complement other forms of microscopy. In this talk I will review examples of recent progress in this direction, including our work on devices with more than 100,000 active addressable microelectrodes on a semiconductor chip. These CMOS sensor chips can be used to create non-destructive all-electrical “images” of cells, particles, biofilms, and other materials near the surface of the sensor, without any labels, illumination, lenses, dyes, or scanning probes. In addition to offering low cost, high throughput, and small physical size, scaling electrochemical sensor arrays to the size and density of image sensors may also open new opportunities for multi-modal computational imaging.
Jacob Rosenstein, Associate Professor of Engineering, Brown University, USA
Bio: Jacob K. Rosenstein is an Associate Professor in the School of Engineering at Brown University, in Providence, Rhode Island. He received a Ph.D. in electrical engineering from Columbia University, and previously worked in the wireless division at Analog Devices and MediaTek. His research focuses on electronic interfaces with chemical and biological systems, which has included integrated circuits for DNA sequencing, molecular information systems, machine olfaction, and smart cell culture platforms.
Title: Novel Sensors and Systems for Digital Twin for Precision Health
Abstract: The bold vision of pervasive physiological monitoring, through proliferation of off-the-shelf wearables that began a decade ago, has created immense opportunities for precision health outside clinics and in ambulatory settings. Although significant progress has been made, several unmet needs remain; the sensors often do not fully satisfy the requirement of the AI algorithms as it pertains to providing advanced physiological parameters with sufficient fidelity and robustness. Sensor calibration and personalization of AI algorithms also pose a challenge as the AI algorithms understand very little about the physical sensors and their underlying physics.
This seminar presents several topics that coherently articulate on the vision and the opportunities of digital twin and advanced wearable biomedical sensor and circuit development. We will introduce several novel sensing paradigms using bio-impedance that leverage various types of electrodes and electronic tattoos enabling blood pressure measurement with clinical grade accuracy. We will discuss AI algorithms that operate with such sensors. We will then introduce the notion of digital twin aimed at enhancing the robustness of measurements while fully taking advantage of the capabilities of the underlying sensors and circuits.
Digital health and wearables will play a significant role in the future of medicine outside clinics. The future directions present opportunities both in short-term translational research efforts with direct influence on clinical practice as well as long-term foundational development of circuits, theories and computational frameworks combining human physiology, physics, computer science, engineering, and medicine, all aimed at impacting the health and wellbeing of our communities.
Roozbeh Jafari, Texas A&M University, USA
Bio: Roozbeh Jafari (http://jafari.tamu.edu) is the Tim and Amy Leach Professor at Texas A&M university with appointments in School of Engineering Medicine in Houston TX and College of Engineering in College Station, TX. His appointments span over Electrical and Computer Engineering, Biomedical Engineering, Computer Science and Engineering departments. He received his Ph.D. in Computer Science from UCLA and completed a postdoctoral fellowship at UC-Berkeley. His research interest lies in the area of wearable computer design and signal processing. He has raised more than $86M for research with $23M directed towards his lab. His research has been funded by the NSF, NIH, DoD (TATRC), DTRA, DIU, AFRL, AFOSR, DARPA, SRC and industry (Texas Instruments, Tektronix, Samsung & Telecom Italia). He has published over 200 papers in refereed journals and conferences. He has served as the general chair and technical program committee chair for several flagship conferences in the areas of wearable computers. Dr. Jafari is the recipient of the NSF CAREER award (2012), IEEE Real-Time & Embedded Technology & Applications Symposium best paper award (2011), Andrew P. Sage best transactions paper award (2014), ACM Transactions on Embedded Computing Systems best paper award (2019), William O. and Montine P. Head Memorial research award for outstanding engineering contribution award from the College of Engineering at Texas A&M (2019), dean of engineering excellence award at Texas of A&M University (2021) and TEES research impact award at Texas A&M University (2021). He has been named Texas A&M Presidential Fellow (2019). He serves on the editorial board for the Nature Digital Medicine, IEEE Transactions on Biomedical Circuits and Systems, IEEE Sensors Journal, IEEE Internet of Things Journal, IEEE Journal of Biomedical and Health Informatics, IEEE Open Journal of Engineering in Medicine and Biology and ACM Transactions on Computing for Healthcare. He is currently the chair of the IEEE Wearable Biomedical Sensors and Systems Technical Committee (elected) as well the IEEE Applied Signal Processing Technical Committee (elected). He serves on scientific panels for funding agencies frequently, served as a standing member of the NIH Biomedical Computing and Health Informatics (BCHI) study section (2017-2021), and was the inaugural chair of the NIH Clinical Informatics and Digital Health (CIDH) study section (2020-2022). He is a Fellow of the American Institute for Medical and Biological Engineering (AIMBE).
Title: Soft Deformable Bioelectronics towards Seamless Integration with Tissues and Organs
Abstract: Electronics that can seamlessly integrate with human body could have significant impact in medical diagnostic, therapeutics. However, seamless integration is a grand challenge because of the distinct nature between electronics and human body. Conventional electronics are rigid and planar, made out of rigid materials. Human body are soft, deformable and curvilinear, comprised of biological materials, organs and tissues. This talk will introduce our solution to address the challenge through a few emerging bioelectronics technologies, such as stretchable electronics and most recently rubbery electronics. By taking the advantage of the enable mechanics of ultra-thin, open-mesh structures, conventionally non-stretchable electronic materials could become mechanically stretchable. Special mechanical structures or architectures accommodate or eliminate mechanical strain in the non-stretchable materials while stretched. Stretchable electronics in this fashion allow integration with skin, organ and tissues. On contrary, rubbery electronics is constructed all based on elastic rubber electronic materials of semiconductors, conductors and dielectrics, which possesses tissue-like softness and mechanical stretchability to allow seamless integration with soft deformable tissues and organs. Rubbery electronic materials and device innovations set the foundation for rubbery electronics. This presentation will feature the development of stretchable electronics and the recent advancement of rubbery electronics and bioelectronics. As platform technologies, stretchable electronics and rubbery electronics could address many scientific challenges in biomedical research and clinical studies.
Cunjiang Yu, Pennsylvania State University, USA
Bio: Dr. Cunjiang Yu is the Dorothy Quiggle Career Development Associate Professor of Engineering Science and Mechanics, Biomedical Engineering, and Materials Science and Engineering at Pennsylvania State University. His recent research concerns the fundamentals and applications of soft-/bio-electronics. His work has been recognized by numerous awards, including the CAB Mid-Career Award, ASME Thomas J. R. Hughes Young Investigator Award, ASME Chao and Trigger Young Manufacturing Engineer Award, the Society of Engineering Science Young Investigator Medal Award, NSF CAREER Award, ONR Young Investigator Award, NIH Trailblazer Award, MIT Technology Review TR35 Top Innovator of China, AVS Young Investigator Award, etc.
Wednesday, April 26
9:00 am-11:00 am
Standardizing Chiplet Design
Session Chairs: Monodeep Kar, IBM, USA and Divya Prasad, AMD, USA
Title: SerDes Architectures for Die to Die Interfaces in a Multi-Chip Module
Amin Shokrollahi, Kandou Bus, Switzerland
Title: The New Open Chiplet Economy
Shahab Ardalan, Luminous Computing, USA
Bio: Shahab Ardalan has been with Luminous Computing since 2022, where he is the senior director of analog & mixed-signal and leading monolithic optical I/O development. Shahab was with Ayar Labs, Santa Clara, CA, USA, 2017-2021 where he was working on a high-speed SerDes link for CMOS monolithic optical I/Os. He was with AMS R&D Group in Gennum Corporation from 2007 to 2010. In 2010, he joined San Jose State University as an Assistant Professor and Director of the Center for Analog and Mixed-Signal where he was teaching and conducting research on analog and mixed-signal integrated circuits. Shahab has a Ph.D. from the University of Waterloo, Waterloo, ON, Canada. He has published over 80 papers in integrated circuit design. He is the IEEE Senior Member, was the IEEE Canada Board member from 2003 to 2012, and IEEE Solid State Circuit Society Chapter Chair for Santa Clara Valley for 2021 and 2022.
Wednesday, April 26
9:00 am-11:00 am
Standardizing Chiplet Design
Session Chairs: Monodeep Kar, IBM, USA and Divya Prasad, AMD, USA
Title: SerDes Architectures for Die to Die Interfaces in a Multi-Chip Module
Abstract: In his groundbreaking 1965 paper, Gordon Moore not only predicted the now-famous “Moore’s Law,” but also anticipated the end of its reign and the emergence of chiplets. Today, industry leaders have demonstrated the significant advantages of designing large chips using chiplets. However, the interconnect between these chiplets is crucial for the success of such a chiplet architecture. Many current architectures imitate single-die approaches by relying on a vast number of thin silicon wires to connect the die, resulting in significant constraints on the design and manufacturing costs. Alternatively, some industry players have adopted a different approach by utilizing specialized SerDes architectures for the interconnect. A well-designed SerDes architecture can address issues surrounding manufacturability, yield, and cost. During this presentation, I will discuss modulation techniques that can be employed for this purpose, as well as touch upon Kandou’s innovative approach.
Amin Shokrollahi, Kandou Bus, Switzerland
Bio: Amin Shokrollahi finished his PhD at the University of Bonn in 1991 where he was an assistant professor until 1995. From 1995 to 1998 he was at the International Computer Science Institute in Berkeley. In 1998 he joined the Bell Laboratories as a Member of the Technical Staff. From 2000 to 2009 he was the Chief Scientist of Digital Fountain. In 2003 he joined EPFL as a full professor of Mathematics and Computer Science. In 2011 he founded the company Kandou Bus which designs fast and energy efficient chip-to-chip links and has since been the CEO of the company. In addition to his academic and professional achievements, Dr. Shokrollahi has also made significant contributions to the academic and engineering communities. He has served as an editor for several prestigious journals, organized numerous IEEE conferences, and has served on the board of the IEEE Information Theory Society.
Dr. Shokrollahi’s academic and industrial achievements span a wide range of topics, from pure mathematics to electronics. His most well-known research is centered around the reliable transmission of information. He has co-authored three books and boasts more than 200 peer-reviewed publications. Furthermore, Dr. Shokrollahi is named as the inventor on more than 250 pending and granted patent applications. He is recognized as an IEEE Fellow and has received numerous honors throughout his career, including several IEEE Paper Awards, the IEEE Eric E. Sumner Award, the Advanced Research Grant of the ERC, the IEEE Hamming Medal, the Mustafa Prize, and the ISSCC Jan van Vessem Award for outstanding European paper.
Title: The New Open Chiplet Economy
Abstract: Multiple technological and business trends are driving a change to realizing semiconductor products as systems in package (SiP) that integrate multiple die, usually referred to as chiplets, into a single package. Compared to monolithic SoCs, chiplet-based designs require an evolution in architecture, interfaces, design and manufacturing flows. Several large companies have already made the transition to chiplet-based designs with proprietary tools and technologies. Many have not and need the expertise to do so. A new and open Chiplet economy to help companies adopt chiplet technologies is developing. It is based on and will require collaboration and standardization on multiple dimensions, ensuring that companies are able to interact in an open, efficient and scalable manner. This talk will profile the chiplet economy including its motivations, standards, participants and growth areas.
Bapi Vinnakota, Open Compute Project, USA
Bio: Bapi Vinnakota currently leads the Open Domain-Specific Architecture sub-project, within the Open Compute Project. The ODSA has active volunteers from over 50 companies and has 8 active workstreams with several activities essential for establishing an open Chiplet economy. Achievements by ODSA include the release of the Bunch of Wires (BoW) die-to-die Interface (now in products at multiple companies) and CDXML, the first open spec for the physical description of chiplets.
After a Ph.D. at Princeton, he taught at the University of Minnesota for a decade. He has also worked at Intel, Broadcom on several networking products and in algorithmic trading. He is an author or co-author of over 50 refereed conference and journal papers, including the work of the ODSA. Bapi has also been an invited speaker at several IEEE, ACM and industry conferences. He is currently with the Lawrence Berkeley Labs.
Title: Emerging Photonic Technologies Enable Scaling the Chiplet Eco-System
Abstract: The relentless demand in CMOS performance, which is primarily driven by applications such as machine learning and real time information processing associated with self-driving vehicles, for example, exerts formidable pressure on interconnect technologies to scale and keep up with the mounting demand in compute and memory bandwidth densities within Systems-in-a-package (SiP).
Photonic technologies with their various flavors, hold immense promise for achieving numerous superlatives towards interconnect scalability at current and emerging bit rates. Some photonic approaches can enable substantially reduced latency and power consumption as well as unpresented bandwidth densities, not currently offered by electronic SERDES or conventional Si photonics.
In this talk, the opportunities and challenges associated with bringing existing generations of Si photonics, closer to the logic to aide in scaling the interconnect bottle neck will be discussed. Emerging approaches, that complement Si photonics, by eliminating the current challenges, while enabling 100s of Tbps/mm bandwidth density will also be presented.
Amr Helmy, University of Toronto, Canada
Bio: Amr S. Helmy is a Professor in the department of electrical and computer engineering at the University of Toronto. Prior to his academic career, Amr held a position at Agilent Technologies – UK, between 2000 and 2004. At Agilent his responsibilities included developing lasers and monolithically integrated optoelectronic circuits. He received his Ph.D. and M.Sc. from the University of Glasgow with a focus on photonic integration technologies, in 1999 and 1995 respectively.
His research interests include photonic device physics, with emphasis on plasmonic nanostructures, nonlinear and quantum photonics addressing applications in information processing / sensing, and data communications. Amr is an active volunteer within the IEEE Photonics Society, currently serving as an Elected Member of the Society’s Board of Governors and as a Distinguished Lecturer. He was also recipient of the Society’s 2019 Distinguished Service Award.