IEEE CICC 2025 Call for Papers
Regular Paper Submission Opens: September 9, 2024
Regular Paper Submission FIRM Deadline: November 11, 2024
2025 IEEE Custom Integrated Circuits Conference (CICC)
Sponsored by the IEEE Solid-State Circuits Society
April 13 – 16, 2025 – Boston, MA, USA
Submission of original unpublished work in following areas:
Analog Circuits and Techniques: encompass circuits characterized by analog-dominated innovation, featuring building blocks such as amplifiers, comparators, frequency generation (oscillators and PLL) and clocking circuits, dividers, filters, references, nonlinear signal processing circuits, digitally-assisted analog circuits, sensor interface circuits.
Biomedical Technologies and Applications focus on biomedical circuits, systems, and applications including but not limited to neural interfaces, microarrays, lab-on-a-chip, bio-inspired circuits, implantable and/or wearable systems, neuromodulation, electroceuticals, closed-loop systems with sensing and actuation, medical imaging, biotelemetry systems, bio-energy harvesting/scavenging systems, body area sensor networks for wireless health monitoring, biomedical signal processing SoCs, AI/ML techniques for mixed-signal biomedical applications, brain computer interfaces, and other biosensors.
Data Converters include a range of innovative converters, such as Nyquist and oversampled A/D, D/A, time-to-digital, frequency-to-digital, and analog-to-information converters of all types driven by innovative techniques, architectures, technologies or applications.
Digital Circuits and SoCs for papers with IC prototypes in technologies that enhance the efficiency, performance, reliability, integrity or security of integrated systems. Areas of interest include but are not limited to processors, accelerators, interconnect fabrics, communication SoCs, memory, and in-memory computing. Foundational hardware design building blocks, and associated tools and techniques to demonstrate novel circuits in relevant technology nodes are encouraged. Holistic innovations such as hardware-software codesign, advancement in cloud and edge computing, and autonomy are also of interest.
Emerging Technologies, Systems, and Applications solicit hardware-focused papers that explore the technologies of tomorrow extending from new devices, circuits to applications. Topics of interest include next-generation technology for MEMS, THz, flexible, printed, large-area and organic electronics, as well as emerging computing paradigms including photonic and quantum computing hardware.
Systems and Security: Papers on the latest advancements in the areas: system and platform design, and hardware security. Relevant topics include large-scale SoCs and FPGA-based designs, systems based on large-scale platforms such as RISC-V and neuromorphic platforms, 2.5D/3D chiplet system-in-package (SiP), system-on-interposer and multi-die integration, and methodologies for system and platform design. For the security category, topics covering novel security primitives, circuit attack/defense mechanisms, and comprehensive secure system designs are sought.
Power Management circuits and design techniques on switched-mode integrated converters using inductive, capacitive, and hybrid architectures, 3D power delivery for high performance computing and chiplets, energy harvesting circuits, wireless power transfer, isolated power, power management circuits for automotive applications, linear regulators and digital LDOs, circuit with novel wide-bandgap devices and drivers, battery chargers, supply modulators, and various methods to improve system overall energy efficiency and performance.
Wireless Transceivers and RF/mm-Wave Circuits and Systems for low-power, energy-efficient and high-performance wireless links, IoT applications, cellular connectivity including M2M applications (LTE-M, NB-IoT), emerging broadband and MIMO networks (5G, WLAN), vehicle-to-vehicle (V2V), millimeter-wave; and design technology co-optimization, THz systems (radar, sensing and imaging, B5G/6G communication), integrated sensing and communications frequency synthesis and LO generation, from block level (PA, LNA, VCO etc.) to full transceivers. Papers discussing agile and low-latency spectrum management and sharing, AI/ML assisted RF/mmWave design are also encouraged.
Wireline and Optical Communication Circuits and Systems welcome papers on serial/parallel data links for intra-chip/chip-to-chip/die-to-die interconnections, memory/graphics interfaces, backplanes, silicon-photonics optical communications, 2.5/3D interconnects, and chiplet-based packaging solutions. Additionally papers on novel I/O circuits, signaling methods, CDRs, equalizers, ADC/DAC/DSP-based transceivers, and electro-optical interface circuitry for pluggable and co-packaged optics are of interest.
Conference Technical Sessions and Events
Technical Sessions addressing a broad range of circuits, applications, design techniques, tools, test, reliability, and emerging technologies, and providing education on new, state-of-the-art developments is the core of the CICC technical program.
Educational Sessions instructed by recognized invited speakers who are among the best in the industry are included in the conference. They are valuable opportunities to refresh key skills in traditional circuit-design methods and acquire knowledge in vital new areas in analog, digital, and RF integrated circuit design.
Panels, Forums and Keynote Sessions provide a platform for leaders from industry and academia to present highlights on new research and development related to circuit design and to debate key issues and controversial topics. CICC panels are well known for their lively and thought-provoking discussion and audience participation.
Our Welcome Reception and Keynote Luncheon provide additional opportunities for discussion and peer networking.
Paper Submission
Regular Technical Session Papers are 3 pages in length. Papers should be camera-ready and submitted electronically in PDF format using the CICC website instructions (www.ieee-cicc.org). Please follow the instructions given at the submission website to submit a blind version for review and a complete version for publication. Appropriate company and government clearances MUST be obtained prior to submission. Papers must report an original unpublished work and concisely explain how the state-of-the-art is advanced, including results. Circuit-design papers must include measured experimental results that substantiate performance claims. FIRM DEADLINE for paper submission is 11:59 pm Eastern Time on November 11, 2024. Authors of accepted papers will be notified by email by January 14, 2025. Top-rated papers will be invited to special issues in the IEEE Journal of Solid-State Circuits and IEEE Solid-State Circuits Letters.
For more information, please visit www.ieee-cicc.org.
General Chair: Eric Soenen, AMD: eric.soenen@amd.com
Conference Chair: Nan Sun, Tsinghua University: sunnansunny@gmail.com
Technical Program Chairs:
Carlos Tokunaga, Intel: carlos.tokunaga@intel.com
Ulkuhan Guler, WPI: uguler@wpi.edu