2024 Keynote Sessions
Monday, 22 April
8:00 am-9:10 am
Welcome and Opening Remarks and Keynote Session 1
Dr. Tsung-Yung Jonathan Chang, TSMC, Taiwan
Bio: Tsung-Yung Jonathan Chang is a TSMC Fellow and Senior Director leading memory IP development at TSMC. He is responsible for SRAM DTCO and memory IP development for advance technology nodes. Before joining TSMC, Dr. Chang was a principal engineer at Intel responsible for cache development for Enterprise server processors. He received B.S. degree from National Taiwan University, and M.S. and Ph.D. from Stanford University, all in electrical engineering. Dr. Chang is a fellow of IEEE, had served as the memory subcommittee chair from for ISSCC, TPC members of ISSCC, VLSI, associate and guest editors of Journal of Solid-State Circuits, and associate editor of IEEE Trans on VLSI. Dr. Chang has published more than fifty technical papers in IEEE conferences or journals and held twenty-five patents in embedded memory design.
Title: Semiconductor in Artificial Intelligence Era
Abstract: Advances in semiconductor have been essential in driving revolutions in modern electronics and affect every aspect of the global economy. The inventions of the PC, the internet, and the ubiquitous, mobile devices, have brought computing to all our daily lives. This paper discusses the present and future of semiconductor technology in the Era of Artificial Intelligence – from the advancement of logic, memory, and the specialty technologies to heterogeneous integration, which are all critical in meeting the ever-increasing demand for data-centric computing. Specialized IP’s such as compute in memory, customized for AI applications, have also emerged by improving energy efficiency and computing throughput. Also, how artificial intelligence can help accelerate the development of semiconductor technology, circuit design and chip integration will be discussed. The semiconductor technology in the era of AI is full of possibilities and can inspire abundant innovations to bring more positives to society.
Tuesday, 23 April
12:00 pm-1:30 pm
Keynote Luncheon
*Pre-registration Required
Dr. Noah Sturcken, Ferric Semi, USA
Bio: Noah Sturcken is a Founder and CEO of Ferric with over 40 patents issued and 15 publications on Integrated Voltage Regulators. Ferric is a venture-backed start-up focused on advancing power delivery systems for high-performance processors. Noah holds a Ph.D. and M.S. in Electrical Engineering from Columbia University and B.S. from Cornell University.
Title: Integrated Voltage Regulators: from Research to Production
Abstract: Modern datacenter processors will see power supply current levels increase from 500A to 1500A within the next few generations. Conventional Power Delivery Networks (PDNs) for microprocessors are struggling to maintain power supply integrity now and will be challenged further as current levels continue to increase. Integrated Voltage Regulators (IVRs) are an attractive solution for alleviating these power delivery challenges, but implementations are challenging. This talk will describe 15 years of IVR development at Ferric, from research to production.
Wednesday, 24 April
8:00 am-8:50 am
Keynote Session
Suman Datta, Georgia Tech, USA
Bio: Datta is the Joseph M Pettit Chair of Advanced Computing and Georgia Research Alliance (GRA) Eminent Scholar and Professor in the School of Electrical & Computer Engineering at Georgia Tech. He received his B.Tech degree in Electrical Engineering from the Indian Institute of Technology, Kanpur, India, and his Ph.D. degree in Electrical and Computer Engineering from the University of Cincinnati, Ohio, USA. His research group focuses on semiconductor devices that accelerate current compute models as well as enable new compute models such as in-memory compute, cryogenic compute, resilient compute, collective compute. From 2015 till 2022, Datta was the Stinson Endowed Chair Professor of Nanotechnology at the University of Notre Dame, where he was the Director of a multi-university microelectronics research center, ASCENT, funded by the Semiconductor Research Corporation (SRC) and the Defense Advanced Research Projects Agency (DARPA). Datta also served as the Director of a six-university research center for Extremely Energy Efficient Collective Electronics (EXCEL), funded by the SRC and National Science Foundation (NSF) that leverages continuous- time dynamics of emerging devices to execute optimization, learning, and inference tasks. From 2007 till 2015, he was a Professor of Electrical Engineering at The Pennsylvania State University, where his group pioneered advances in compound semiconductor-based quantum-well field effect transistors and tunneling field effect transistors. From 1999 till 2007, he was in the Advanced Transistor Group at Intel Corporation, where he led device R&D effort for several generations of high-performance logic transistors such as high-k/metal gate, Tri-gate and strained channel CMOS transistors. He has published over 450 journal and refereed conference papers and holds more than 187 issued patents related to semiconductor devices. In 2013, Datta was named a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) for his contributions to high-performance advanced silicon and compound semiconductor transistor technologies. In 2016, he was named Fellow of the National Academy of Inventors (NAI) in recognition of his inventions that have made a tangible impact on quality of life, economic development, and the welfare of society.
Title: Embracing A System-Driven Strategy to Semiconductor Technology Advancement
Abstract: Breakthroughs in semiconductor theory during the 1930s and the refinement of germanium and silicon crystals in the 1940s paved the way for the development of the point-contact junction transistor in 1947, marking the inception of semiconductor microelectronics. Seventy-five years later, the relentless pursuit of transistor density doubling through “scaling” at each new process node persists, albeit at a decelerated pace in recent times. This scaling has yielded exponential enhancements in the performance and energy efficiency of integrated circuits, fundamentally reshaping the landscape of computing from mainframes to personal computers, and from mobile devices to cloud computing platforms. Future advancements in transistor scaling hinge upon innovations in novel materials, transistor architectures, cryogenic operation, and the co-optimization of design technologies. Monolithic 3D integration and the stacking of polylithic chips are poised to drive an exponential increase in transistor count, while advancements in backside power delivery and power conversion technologies will unlock the utilization of silicon real estate beneath transistors. This system-inspired collective innovation approach promises to sustain the trajectory of improved performance and energy efficiency in future microsystems. Notably, this research is underpinned by support from the Joint University Microelectronics Program (JUMP), sponsored by the Semiconductor Research Corporation (SRC) in collaboration with DARPA.