2024 Call for Papers

IEEE CICC 2024 Call for Papers

Thank you for your Submissions. Paper Submissions for 2024 CICC are now CLOSED.

2024 IEEE Custom Integrated Circuits Conference (CICC)

Sponsored by the IEEE Solid-State Circuits Society

April 21 – 24, 2024 – Denver, Colorado

Submission of original unpublished work in following areas:

Analog Circuits and Techniques: Circuits with analog-dominated innovation, building blocks such as amplifiers, comparators, frequency generation (oscillators and PLL) and clocking circuits, dividers, filters, references, nonlinear signal processing circuits, digitally-assisted analog circuits, sensor interface circuits.

Data Converters including Nyquist and oversampled A/D, D/A, time-to-digital, frequency-to-digital, and analog-to-information converters of all types driven by innovative techniques, architectures, technologies or applications.

Digital Circuits and SoCs for papers with IC prototypes in technologies that enhance the efficiency, performance, reliability or security of integrated systems. Areas of interest include processors, accelerators, interconnect fabrics, memory and foundational hardware design building blocks with associated tools, techniques, and methodologies in advanced nodes. Circuit, process, and architecture co-design for domain-specific applications such as AI, hardware security, cloud computing, edge computing, autonomy and communication SoCs, low-voltage design, and low-temperature computing are also of interest.

Emerging Technologies, Systems, and Applications solicit hardware-focused papers in the technologies of tomorrow extending from new devices to applications with a focus on, but not limited to: 1) Next-generation technology and sensors, sensor interfaces for MEMS, mm-wave/THz, flexible, printed, large-area and organic electronics, electronic-photonic co-design, and silicon photonics. Emerging computing paradigms including photonic and quantum computing hardware, AI/ML and in-memory computing utilizing new devices, analog, and mixed-signal circuits. 2) Biomedical circuits, systems, and applications including neural interfaces, microarrays, lab-on-a-chip, bio-inspired circuits, implantable and/or wearable systems, closed-loop systems with sensing and actuation, medical imaging, and other biosensors including biomedical signal processing SoCs, AI/ML for mixed- signal/sensing.

Foundation of System Design with research topics that show innovations in system and platform design, which extend beyond a single integrated circuit. The platforms may include large-scale systems on chip (e.g., SoCs, FPGA-based designs), 2.5D/3D chiplet based system-in-package, system-on-interposer, and multi- die integrations (including die-to-die interfaces), neuromorphic accelerators, quantum computers, and RISC / general-purpose compute systems. The submission may focus on design methodologies to enable applications such as IoT, biomedical and healthcare, machine learning, big data management, autonomous systems, robotics, secure manufacturing, datacenter platforms, domain-specific compute, and advanced connectivity platforms.

Power Management circuits and design techniques for papers on switched-mode integrated converters using inductive, capacitive, and hybrid architectures, 3D power delivery for high performance computing and chiplets, energy harvesting circuits, wireless power transfer, isolated power, power management circuits for automotive applications, linear regulators and digital LDOs, circuit techniques with novel wide-bandgap devices and drivers, battery chargers, supply modulators, and other methods to improve system overall energy efficiency and performance. Wireless Transceivers and RF/mm-Wave Circuits and Systems for low-power, energy-efficient and high performance wireless links, biomedical and sensing networks, IoT applications, cellular connectivity including M2M applications (LTE-M, NB-IoT), emerging broadband and MIMO networks (5G, WLAN), vehicle-to-vehicle (V2V), millimeter-wave & THz systems (radar, sensing and imaging, B5G/6G communication), frequency synthesis and LO generation, from block level (PA, LNA, VCO etc.) to full transceivers.

Wireline and Optical Communication Circuits and Systems for papers on serial/parallel data links for intra-chip/chip-to-chip/die-to-die interconnections, memory/graphics interfaces, backplanes, silicon-photonics optical communications, 2.5/3D interconnects, and chiplet-based packaging solutions; also for papers on novel I/O circuits, signaling methods, clocking techniques, PLLs, CDRs, equalizers, ADC/DAC/DSP-based transceivers, and electro-optical interface circuitry for pluggable and co-packaged optics.

Conference Technical Sessions and Events

Technical Sessions addressing a broad range of circuits, applications, design techniques, tools, test, reliability, and emerging technologies, and providing education on new, state-of- the-art developments is the core of the CICC technical program.
Educational Sessions instructed by recognized invited speakers who are among the best in the industry are included in the conference. They are valuable opportunities to refresh key skills in traditional circuit-design methods and acquire knowledge in vital new areas in analog, digital, and RF integrated circuit design.
Panels, Forums and Keynote Sessions provide a platform for leaders from industry and academia to present highlights on new research and development related to circuit design and to debate key issues and controversial topics. CICC panels are well known for their lively and thought-provoking discussion and audience participation.

Our Welcome Reception and Keynote Luncheon provide additional opportunities for discussion and peer networking.

Paper Submission

Regular Technical Session Papers are 2 pages in length. Papers should be camera-ready and submitted electronically in PDF format using the CICC website instructions ( Appropriate company and government clearances MUST be obtained prior to submission. Papers must report an original unpublished work and concisely explain how the state-of-the-art is advanced, including results. Circuit-design papers must include measured experimental results that substantiate performance claims.

Deadline for paper submission is 11:59 pm Mountain Time on November 20, 2023.

Authors of accepted papers will be notified by email by January 5, 2024.

Top-rated papers will be invited to special issues in the IEEE Journal of Solid-State Circuits and IEEE Solid-State Circuits Letters.

General Chair:
Arijit Raychowdhury, Georgia Institute of Technology:
Conference Chair:
Eric Soenen, Silicon Labs:
Technical Program Chairs:
Nan Sun, Tsinghua University:
Carlos Tokunaga, Intel: