2026 IEEE Custom Integrated Circuits Conference (CICC) Best Paper Winners

BEST PAPER WINNERS WILL BE FORMALLY ANNOUNCED AT THE WELCOME REMARKS AT CICC 2027 IN APRIL 2027

Best Paper Award

Mr. Kai Yuan, The Chinese University of Hong Kong (Shenzhen), China

Bio: Kai Yuan received the B.Eng. degree from Zhejiang University, China, in 2022. He is currently pursuing the Ph.D. degree with The Chinese University of Hong Kong (CUHK), Shenzhen, China. His research interests include power management IC and analog IC design, especially in high-frequency dc–dc converters and hybrid power converters.

Talk Title: (16-2) A 3-4.2V-to-Sub-1V Dual-Phase-Multi-Path-NLDO Sigma Converter Achieving 50ns Recovery Time for 2.5A/20ns Load Step and 1028W/cm3 Power Density

Abstract: This paper proposes a sigma converter with a dual-phase-multi-path (DPMP) converter on the high side and an NMOS LDO on the low side to achieve high power density and fast transient response for computing processors’ power supply. The converter delivers a maximum output power of 4W with a power density of 1028W/cm³ by the proposed DPMP topology. For a 2.5A/20ns load step, a fast recovery of 50ns is achieved by fast regulation of low-side NLDO.

Outstanding Student Paper Award

Dr, Mahmoud Khalil, University of Illinois Urbana-Champaign, United States

Bio:. Mahmoud Khalil received the B.Sc. and M.Sc. degrees from Ain Shams University, Cairo, Egypt, in 2013 and 2019. From 2013–2021, he was a Staff Design Engineer at Si-Vision, Egypt. He is pursuing a Ph.D. at the University of Illinois, Urbana-Champaign. His research interests include frequency synthesizers and high-speed SerDes.

Talk Title: (12-1) A 14GHz 16-Phase Calibration-Free Fractional-N Ring-PLL with 118fs Jitter Using Phase- and Voltage-domain Quantization Error Cancellation

Abstract: This paper presents a calibration-free, type-III fractional-N ring PLL that generates 16 phases at 14GHz from a 1.125GHz reference. A high-gain phase detector enables >40MHz loop bandwidth and –121dBc/Hz in-band noise, strongly suppressing VCO noise. To address fractional-N quantization error at OSR=14, the synthesizer combines phase- and voltage-domain cancellation with a noise-shaped segmented ΔΣ scheme, eliminating supply- and temperature-sensitive DTCs. Fabricated in 16-nm FinFET, the PLL occupies 0.083mm² and achieves 118fs jitter (10kHz–100MHz) without calibration.

Outstanding Student Paper Award

Mr. Harshit Naman, Purdue University, United States

Bio: Harshit Naman received his B.Tech. in Electronics and Communication Engineering from Birla Institute of Technology, Mesra, India (2022). He is currently pursuing a Ph.D. in Electrical and Computer Engineering at Purdue University, West Lafayette, USA.
His research interests include Mixed signal IC design for low power computing and biomedical circuits.

Talk Title: (7-8) A 16nm 0.67pJ/bit 80Mb/s Circuit-System Co-Optimized Time Domain Brain Channel Receiver

Abstract: Emerging brain–computer interfaces require high data rates and ultra-low power for continuous neural communication. This work presents a 16-nm circuit–system co-optimized time-domain brain-channel receiver (TD-BC Rx). A channel-inspired time-domain modulation scheme leverages the brain channel’s high-loss, phase-flat characteristics for robust signaling. A ratio-metric, self-referencing detection technique stabilizes decoding under PVT variation, enabling an ultra-low-power free-running RO architecture. The fabricated receiver achieves 80 Mb/s at 0.67 pJ/bit, delivering a 33× energy-efficiency improvement.

Outstanding Student Paper Award

Ms. Eojin Kim, KAIST, Republic of Korea

Bio: This paper presents a simultaneous 16-channel adiabatic charge-tracking stimulator (SACT) for implantable systems. Time-multiplexed stimulation enables parallel operation using a single current-generation block. An on-chip capacitor ensures accurate per-channel charge balance, while an inductor adiabatically recovers energy each cycle. A time-based sensor predicts phase transitions. A stimulator efficiency of 87.4% with <3.7% variation and <0.54% charge mismatch across 500Ω–10kΩ and 60–250nC stimulation charge was achieved. In-vivo multi-channel stimulation was successfully demonstrated.

Talk Title: (14-2) A Simultaneous 16-Channel Adiabatic Charge-Tracking Stimulator with 87.4% Stimulator Efficiency and Low Load Sensitivity

Abstract: Eojin Kim received a B.S. degree in Bio-Mechatronic Engineering from Sungkyunkwan University, South Korea and a M.S. degree in Bio and Brain Engineering from KAIST, South Korea, where she is currently pursuing a Ph.D. degree. Her research focuses on Energy Efficient Biomedical Systems and Neural Stimulators