[vc_custom_heading text=”Session 11: Circuit Device Interaction – CMOS Scaling and Circuit/Device Variability” font_container=”tag:h1|text_align:left” use_theme_fonts=”yes”]

Tuesday, December 8, 9:00 a.m.
International Ballroom East
Co-Chairs:       Curtis Tsai, Intel
Susan Wu, Xilinx

9:05 a.m.
11.1        2RW Dual-port SRAM Design Challenges in Advanced Technology Nodes, K. Nii, M. Yabuuchi, Y. Yokoyama, Y. Ishii, T. Okagaki, M. Morimoto, Y. Tsukamoto, K. Tanaka, M. Tanaka, and S. Tanaka, Renesas Electronics Corporation

We discuss the candidates of 2 read/write (2RW) 8T dual-port (DP) SRAM bitcell layouts in advanced planar/FinFET technologies. 256-kbit 2RW DP SRAM macros with good symmetrical 8T DP bitcell were designed and fabricated using 16 nm FinFET technology. With introducing wordline over-driven read/write assist, Vmin is improved by 120 mV and observed 0.5 V operations successfully.

9:30 a.m.
11.2        Design and Process Technology Co-Optimization with SADP BEOL in sub-10nm SRAM Bitcell, Y. Woo, M. Ichihashi, S. Parihar, L. Yuan, S. Banna, and J. Kye, GlobalFoundries

As the device scaling continues, multiple patterning technologies are implemented. The patterning technology and metal architecture should be co-optimized to improve electrical performance of circuitry. This paper demonstrates how such an optimization in a sub-10nm node technology can improve the electrical performance of SRAM bitcell.

9:55 a.m.
11.3        Experimental Study on BTI Variation Impacts in SRAM Based on High-k/Metal Gate FinFET: From Transistor Level Vth Mismatch, Cell Level SNM to Product Level Vmin, C. Liu, H. Nam, K. Kim, S. Choo, H. Kim, H. Kim, Y. Kim, S. Lee, S. Yoon, J. Kim, J. Kim, L. Hwang, S. Ha, M-J Jin, H.C. Sagong, J.-K. Park, S. Pae, and J. Park, Samsung Electronics Company Ltd.

Aging induced variability has been shaving away the design margins in advanced SRAM which may become more serious with highly scaled process node. This paper provides a systematical study of the BTI variation impacts in FinFET SRAM based on 14nm 128Mbit SRAM, including the characterization from transistor and cell level to product. The results indicate that besides the process optimization for BTI mean shifts, reliability aware circuit design is necessity to consider intrinsic BTI variation increase with transistor scaling down.

10:20 a.m.
11.4        Magnetic Thin-Film Inductors for Monolithic Integration with CMOS, N. Sturcken, R. Davies, H. Wu, M. Lekas, K. Shepard, K.W. Cheng*, C.C. Chen*, Y.S. Su*, C.Y. Tsai*, K.D. Wu*, J.Y. Wu*, Y.C. Wang*, K.C. Liu*, C.C. Hsu*, C.L. Chang*, W.C. Hua*, and A. Kalnitsky*, Ferric, Inc., Columbia University, *Taiwan Semiconductor Manufacturing Company

This paper presents magnetic thin-film inductors for monolithic integration with CMOS for DC-DC power conversion. Magnetic core inductors were fabricated using conventional CMOS processes to achieve peak inductance density of 290nH/mm2, quality factor 15 at 150MHz, current density exceeding 11A/mm2 and coupling coefficient of 0.89 for coupled inductors.

10:45 a.m.
11.5        Reliability Variability Simulation Methodology for IC Design: an EDA Perspective (Invited), A. Zhang, C. Huang, T. Guo, A. Chen, S. Guo*, R. Wang*, R. Huang*, J. Xie, Cadence Design Systems Inc., *Peking University

This paper presents reliability variability simulation with Monte Carlo method. Both process variation and aging variation, as well as their correlation, are considered. Two simulation flows are developed and used to study reliability variability. Simulation accuracy and performance are discussed. The flows are validated with ring oscillator and SRAM circuit.

11:10 a.m.
11.6        Self-heating on Bulk FinFET from 14nm Down to 7nm Node, D. Jang, E. Bury*, R. Ritzenthaler, M. Garcia Bardon, T. Chiarella, K. Miyaguchi, P. Raghavan, A. Mocuta, G. Groeseneken*, A. Mercha, D. Verkest, A. Thean, imec,*also with KU Leuven

Self-heating effects of scaled bulk FinFETs from 14nm to 7nm node are discussed, as well as ways to mitigate SHE at device level based on 3DFEM simulations and electrical measurements. Finally, the impact of SHE on circuit level performance is also studied for high performance and low power devices.

11:35 a.m.
11.7        Adding the Missing Time-Dependent Layout Dependency into Device-Circuit-Layout Co-Optimization–New Findings on the Layout Dependent Aging Effects, P. Ren, X. Xu*, P. Hao, J. Wang,  R. Wang, M. Li, J. Wang**, W. Bu**, J. Wu**, W. Wong**, S. Yu**, H. Wu**, S.-W. Lee**, D.Z. Pan*, and R. Huang, Peking University, *The University of Texas at Austin, **Semiconductor Manufacturing International Corporation (SMIC)

In this paper, a new class of layout dependent effects (LDE)—the time-dependent layout dependency due to device aging, is reported for the first time. The BTI and HCI degradation in nanoscale HKMG devices are experimentally found to be sensitive to layout configurations, even biased at the same stress condition. This new effect of layout dependent aging (LDA) can significantly mess the circuit design, which conventionally only includes the static LDE modeled for time-zero performance. Further studies at circuit level indicate that, for resilient device-circuit-layout co-design, especially to ensure enough design margin near the end of life, LDA cannot be neglected. The results are helpful to guide the cross-layer technology/design co- optimization.