{"id":216,"date":"2015-07-16T14:24:57","date_gmt":"2015-07-16T21:24:57","guid":{"rendered":"https:\/\/www.ieee-cicc.org\/2025archive\/?page_id=216"},"modified":"2025-04-07T08:03:54","modified_gmt":"2025-04-07T15:03:54","slug":"cicc-forum-sessions","status":"publish","type":"page","link":"https:\/\/www.ieee-cicc.org\/2025archive\/cicc-forum-sessions\/","title":{"rendered":"Forum Sessions"},"content":{"rendered":"

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CICC 2025 Forum Sessions<\/strong><\/h2>\n

Monday, 14 April<\/strong><\/p>\n

10:05 am-12:05 pm<\/strong><\/p>\n

Hardware and Architectural Strategies for Building Cutting-edge AI Platforms<\/strong><\/p>\n

Session Chairs: Sumanth Kamineni, NVIDIA Corporation & Visvesh Sathe, Georgia Institute of Technology<\/p>\n

Speakers:<\/u><\/strong><\/p>\n

Urmesh Thakker, Sambanova, USA<\/strong><\/p>\n

\"\"<\/a>Bio:<\/strong> Urmish leads the Foundation ML Team at SambaNova Systems. The Foundation ML team at SambaNova focuses on adapting models to enterprise use-cases and HW-SW co-design to enable efficient training and inference. Before SambaNova, Urmish was in various engineering and research roles at Arm, AMD and Texas Instruments. Urmish also helped drive the TinyML Performance Working Group in MLPerf, contributing to the development of key benchmarks for IoT ML. He has 45+ publications and patents focusing on efficient deep learning and Foundation ML across conferences like NeurIPS, ICLR, EMNLP, ISCA and MICRO. He completed his masters at the University of Wisconsin Madison and bachelors from Birla Institute of Technology and Science.<\/p>\n

Title:<\/strong> A Hardware Platform for Agentic AI: The SN40L Reconfigurable Dataflow Unit<\/p>\n

Abstract: <\/strong>Agentic AI involves multiple specialized language models working in concert to perform complex tasks. Test-time scaling has enabled the machine learning community to build systems with smaller models that exceed the capabilities of large language models. However, this approach presents two key challenges when using conventional hardware: (1) GPUs significantly underperform during token generation due to inadequate operator fusion and synchronization overheads at kernel boundaries, utilizing only 19% of their peak memory bandwidth and (2) hosting and dynamically switching between a large number of models can be prohibitively expensive and slow. This talk describes SambaNova\u2019s approach to address the challenges above with the SambaNova SN40L Reconfigurable Dataflow Unit (RDU). This chip introduces a new three-tier memory system with SRAM, HBM and DDR DRAM. Model parameters reside in DDR, and actively used models are cached and served from HBM. Dataflow enables an unprecedented level of operator fusion achieving over 90% of peak performance. The SN40L RDU reduces machine footprint by up to 19x, speeds up model switching time by 15x to 31x, and achieves an overall speedup of 3.7x over a DGX H100 and 6.6x over a DGX A100, respectively. Techniques described in this talk are deployed in production in a commercial AI inference cloud at cloud.sambanova.ai.<\/p>\n

Carole-Jean Wu, Meta, USA<\/strong><\/p>\n

\"\"<\/a>Bio:<\/strong> Carole-Jean Wu is a Director of AI Research at Meta, where she leads the Systems and Machine Learning Research team. She is a founding member and a Vice President of MLCommons \u2014 a non-profit organization that aims to accelerate machine learning for the benefit of all. Dr. Wu\u2019s expertise sits at the intersection of computer architecture and machine learning. Her work in sustainability has influenced at-scale adoption for hyperscalar datacenter infrastructures. Before Meta\/Facebook, she was an associate professor at Arizona State University. Dr. Wu earned her M.A. and Ph.D. from Princeton and a B.Sc. from Cornell University.<\/p>\n

Title: <\/strong>Architecture Considerations for Sustainable AI Computing<\/p>\n

Abstract: <\/strong>The past 50 years have seen a dramatic increase in the amount of compute capability per person, in particular, those enabled by AI. This talk explores the architecture design space for new computing devices for AI where carbon is a first order tradeoff with power, performance, and cost. Architecture and design that considers embodied carbon is a new field and requires a measurement framework along with strategies, principles and techniques that support tradeoffs.<\/p>\n

Our first principal analysis shows that considering carbon impact as a factor in datacenter component refresh could shift optimal refresh dates, or motivate skipping some generations of components. As digital technologies continue to grow and to drive economic growth in many industry sectors, embodied carbon emissions due to semiconductor manufacturing are expected to scale up at the same time. This talk will shed light on key directions, where architectural considerations can reduce the sustainability implications of computing.<\/p>\n

Magnus Ekman, Nvidia, USA<\/strong><\/p>\n

\"\"<\/a>Bio:<\/strong> Magnus Ekman, PhD, is a Director of Architecture at NVIDIA. He leads an engineering team working on CPU performance, power, and simulation for chips targeting markets ranging from autonomous vehicles to data centers for artificial intelligence. Ekman has also authored the book and associated video lecture series “Learning Deep Learning.<\/p>\n

Title:<\/strong> AI Model Size Scaling with Accelerated Computing \u2013 a System Perspective<\/p>\n

Abstract:<\/strong> The unprecedented growth in Artificial Intelligence (AI) model size and performance over the past decade would not have been possible without corresponding innovation in accelerated computing, specifically for AI. This presentation highlights examples of how added hardware features map to, and accelerate, Deep Learning model constructs. We discuss both GPU core features and system-level features. We touch on the trade-off between programmability and fixed-function implementations, and its impact on model efficiency and future innovation. We provide examples of design choices made in current systems to strike this balance. We conclude with outlining problem areas to focus on to continue model scaling over the coming decade. We argue that as model training shift from textual data to multimodal data, all parts of the system need to scale to handle these larger data volumes. This will require innovation throughout the compute stack spanning the range from algorithms, system-architecture, to the compute cores. Providing the required performance increase in an environment that is already power constrained will be a key challenge, especially since we can no longer rely as much on process scaling as much we could in the past.<\/p>\n

Subramanian S. Iyer, UCLA Center for Heterogeneous Integration and Performance Scaling, University of California<\/strong><\/p>\n

\"\"<\/a>Bio:<\/strong> Subramanian S. Iyer (Subu) is Distinguished Professor and Director of the Center for Heterogeneous Integration and Performance Scaling (UCLA CHIPS) at UCLA. As Director of the National Advanced Packaging Manufacturing Program (NAPMP), he laid the foundational strategy for the national packaging imperative. Prior to that he was an IBM Fellow.<\/p>\n

Title:<\/strong> Strategic Directions for Electronics Packaging<\/p>\n

Recent advances in electronics packaging have come to the rescue as CMOS scaling has stalled making possible the incredible advances in AI\/ML and other fields, that promise to transform our lives. This journey, however, has only just begun and much more is yet to come. The key features that will drive this transformation can be described with the simple strategy of \u201cscale-down and scale-out\u201d that has characterized monolithic CMOS scaling for several decades, the drive to chiplets with higher yields, and the ability to assemble a diversity of technologies on the same substrate allowing us to blur the lines between monolithic chip and a large heterogeneous assembly of chips. In this talk we will describe our approach to simplify packaging at all levels: from design, architecture, process and manufacturing that have the potential to take packaging to the next level including the ability to scale packaging systematically.<\/p>\n

Tuesday, 15 April<\/strong><\/p>\n

10:05 am-12:05 pm<\/strong><\/p>\n

Potential of Open Source Design for Analog\/Mixed Signal IC Education<\/strong><\/p>\n

Open-source integrated circuit (IC) design is transforming traditional methodologies, increasing accessibility and encouraging collaborative innovation. In analog\/mixed-signal IC education, traditional design flows struggle to keep pace with hands-on training demands as system complexity grows and AI-driven applications expand. This session features experts sharing insights on leveraging open-source tools to revolutionize education and advance chip design.<\/p>\n

Session Chairs: Jorge Marin, Advanced Center for Electrical and Electronic Engineering & Nazanin Neshatvar, University College London<\/p>\n

Speakers: <\/u><\/strong><\/p>\n

Harald Pretl, Johannes Kepler University, Austria<\/strong><\/p>\n

\"\"<\/a>Bio: <\/strong>Harald Pretl received the Dr. techn. Degree from the Johannes Kepler University in Linz, Austria, in 2001. From 2000 to 2022, he developed cellular RF transceivers at Infineon, Intel, and Apple. Since 2015, he is a full professor, heading the Institute for Integrated Circuits (IIC) at JKU.<\/p>\n

Title: <\/strong>Using Open-Source EDA Tools in Hands-On IC Design Education<\/p>\n

Abstract:<\/strong> Our group maintains a collection of open-source IC EDA tools (https:\/\/github.com\/iic-jku\/IIC-OSIC-TOOLS), available pre-integrated as a virtual machine image, for analog, mixed-signal, and digital design using the available open-source PDKs. We are using this tool collection, hosted on a browser-accessible server, to teach an undergraduate digital design course (using Tiny Tapeout for IC fabrication) and a graduate analog design course, freely available at https:\/\/iic-jku.github.io\/analog-circuit-design. In this talk, we will detail our approach and talk about our experience using open-source tools.<\/p>\n

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Jaeduk Han, Hanyang University, South Korea<\/strong><\/p>\n

\"\"<\/a>Bio: <\/strong>Jaeduk Han is an Assistant Professor of Electronic Engineering at Hanyang University. He earned his B.S. and M.S. from Seoul National University and Ph.D. from UC Berkeley. With experience at TLI, Intel, Xilinx, Apple, and SK Hynix, his research focuses on high-speed analog and mixed-signal circuit design and automation.<\/p>\n

Title: <\/strong>Custom Circuit Layout Generation Technologies for Open Source IC Design and Education<\/p>\n

Abstract: <\/strong>The increasing complexity of circuit design at advanced semiconductor nodes, coupled with limited academic access to cutting-edge processes, poses challenges in training skilled engineers. This talk explores automating layout design using open-source PDKs and software tools, focusing on teaching these methods to undergraduate and graduate students. Experiences in adapting these techniques to advanced processes for developing industry-ready talent will also be shared.<\/p>\n

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Elles Raaijmakers, Eindhoven University of Technology, Netherlands<\/strong><\/p>\n

\"\"<\/a>Bio: <\/strong>Elles Raaijmakers obtained her master degree in electrical engineering from Eindhoven University of Technology in 2015. Elles performed her PhD (2023) part-time at the University of Amsterdam. Additionally, she worked as an illustrator for the for the faculty and university magazines. To inform the general public, Elles has published a comic book of her collected research results.<\/p>\n

Title: <\/strong>IC tycoon<\/p>\n

Abstract: <\/strong>Chip designers are in high demand. In contrast with the ever-growing need of new engineers, there is a growing skepticism regarding science among a portion of the general public. We seek the answer through enabling people to experience chip design themselves. We use the open-source PDKs to enable interested laymen to design their own chip, which we will produce and measure for them. And for a younger audience, we are working on a game about IC design.<\/p>\n

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Tim Edwards, Efabless Corporation, USA<\/strong><\/p>\n

\"\"<\/a>Bio: <\/strong>Tim Edwards is SVP Analog and Design at Efabless Corporation, where he has worked since 2014. He is a well-known advocate of open source silicon, and is the developer and maintainer of multiple open source software tools for EDA, including magic, netgen, and open_pdks. He was one of the principle developers of the sky130 and gf180MCU open PDKs, has helped develop the IHP sg13g2 open PDK, and architected the Efabless Caravel harness chip.<\/p>\n

Title: <\/strong>Efabless Frigate: Open source analog and mixed-signal harness<\/p>\n

Abstract: <\/strong>The Efabless chipIgnite program and the Caravel “harness” chip design have enabled access to tools, PDKs, instruction, and community for small businesses, students, makers, bringing real silicon to anyone unable to afford the cost of traditional chip design and manufacture. The Efabless Frigate chip is the next generation of harness, including an improved RISC-V SoC and configurable analog and mixed-signal hardware components, all open source and developed in part by our community of users.<\/p>\n

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Dan Frietchman, Stealth Mode Startup, USA<\/strong><\/p>\n

\"\"<\/a>Bio: <\/strong>Dan Fritchman serves as the CEO of San Francisco, Ca based Generation Alpha Transistor, a provider of AI-based IC design tools. He holds a PhD in Electrical Engineering & Computer Sciences from the University of California, Berkeley, MS from Santa Clara University, and BS from Duke University.<\/p>\n

Title: <\/strong>Lessons From Where Open Source Has (And Hasnt\u2019t) Worked<\/p>\n

Abstract: <\/strong>Open-source distribution has transformed the software industry – or at least parts of it. This talk examines where its impacts have been greatest and most muted, and offers a roadmap for open-source IC design by way of analogy. We feature the design suites principally authored at UC Berkeley for both digital and analog IC design as primary examples.<\/p>\n

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Tuesday, 15 April<\/strong><\/p>\n

3:35 pm-5:35pm<\/strong><\/p>\n

Probabilistic Computing<\/strong><\/p>\n

Session Chairs: Tathagata Srimani, Carnegie Mellon University, & Win-san (Vince) Khwa, TSMC<\/p>\n

Speakers:<\/u><\/strong><\/p>\n

Kerem Camsari, University of California, Santa Barbara, USA\u00a0 \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 <\/strong><\/p>\n

\"\"<\/a>Bio<\/strong>:\u00a0Kerem Y. Camsari, Associate Professor in Electrical and Computer Engineering at UC Santa Barbara (Ph.D., Purdue, 2015). His research in probabilistic computing has earned him many awards, including the IEEE Magnetics Society Early Career Award, a Bell Labs Prize, ONR YIP, NSF CAREER, and most recently the Misha Mahowald Prize.<\/p>\n

Title: <\/strong>Probabilistic Computers for Combinatorial Optimization and Beyond\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\u00a0<\/strong><\/p>\n

Abstract: <\/strong>Probabilistic computing has emerged as a computational paradigm bridging quantum and the classical, accelerating optimization, machine learning, and quantum simulation tasks. Using distributed architectures with interconnected FPGAs, we will show how probabilistic computers can achieve near-linear performance scaling with minimal overhead. We will also show example benchmarks against the state-of-the-art quantum computers as well as other specialized accelerators. Future implementations of p-computers with dedicated ASICs can lead to energy-efficient, scalable solutions to previously intractable problems. \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 <\/strong><\/p>\n

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Jean Anne C. Incorvia , <\/strong>The University of Texas at Austin, USA<\/p>\n

\"\"<\/a>Bio: <\/strong>Jean Anne C. Incorvia is an Associate Professor and Engineering Foundation Endowed Faculty in Electrical and Computer Engineering at The University of Texas at Austin, where she directs the Integrated Nano Computing Lab. Dr. Incorvia develops nanodevices using emerging physics and materials, with an emphasis on applications in computing.<\/p>\n

Title: <\/strong>Co-Design of Probabilistic and Neuromorphic Computing using Magnetic Materials<\/p>\n

Abstract:<\/strong><\/p>\n

Nanoscale magnetic materials have thermally-driven dynamics that make them candidates for probabilistic and neuromorphic computing. We will show prototyping of artificial synapses and neurons based on magnetic domain walls, with 3-5 stable synapse levels achieved, and continuous leaky, integrate-and-fire neurons demonstrated. The stochastic magnetization dynamics aids in learning and inference for both synapses and neurons. For probabilistic computing, we will show co-design of the materials, device, and algorithm for optimizing magnetic true random number generators.<\/p>\n

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Dr. Behtash Behin-Aein<\/b>, Ludwig Computing, USA\u00a0\u00a0\u00a0\u00a0\u00a0<\/b> \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0<\/strong><\/p>\n

\"\"<\/a>Bio:<\/strong>Behtash Behin-Aein, a DARPA Activate Fellow and CTO of Ludwig Computing, earned his PhD from Purdue in 2010. Previously at GLOBALFOUNDRIES, he contributed to STT-MRAM development. His research on spin-based computing influenced the C-SPIN Center. At Ludwig, he pioneers probabilistic computing with p-bits, achieving significant energy efficiency and speed improvements<\/p>\n

Authors: <\/strong>Lakshmi Anirudh Ghantasala, Risi Jaiswal, Behtash Behin-Aein, Joseph Makin,\u00a0Supriyo Datta<\/p>\n

Title:<\/strong> p-Bits for Deep Neural Networks<\/p>\n

Abstract: <\/strong>Probabilistic or p-circuits using p-bits are usually associated with Boltzmann machines and Ising computing where they have been shown to reduce energy costs significantly.\u00a0We will first review this earlier work and then discuss the prospects for using \u00a0p-bits in place of the usual continuous-valued neurons in feed-forward deep neural networks.\u00a0Such feed-forward networks are used in virtually all applications of machine learning and improving their energy efficiency represents a major societal challenge.<\/p>\n

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Sayeef Salahuddin, University of California, Berkeley, USA\u00a0\u00a0\u00a0\u00a0\u00a0 <\/strong><\/p>\n

\"\"<\/a>Bio: <\/strong>TBD<\/p>\n

Title: <\/strong>TBD<\/p>\n

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Abstract: <\/strong>TBD\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 <\/strong><\/p>\n

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Pedram Khalili \u00a0 \u00a0\u00a0<\/strong><\/p>\n

\"\"<\/a>Bio: <\/strong>Pedram Khalili is AT&T Professor of Electrical and Computer Engineering and Co-Director of Applied Physics at Northwestern University. He is a Distinguished Lecturer of the IEEE Nanotechnology Council, serves on the Executive Committee of the IEEE Task Force for Rebooting Computing, and is a Senior Member of the IEEE.<\/p>\n

Title: <\/strong>Probabilistic Computing with Voltage-controlled Magnetic Tunnel Junctions and Digital CMOS<\/p>\n

Abstract: <\/strong>The integration of magnetic tunnel junctions (MTJs) on CMOS provides exciting opportunities for the development of probabilistic (p-) computing ASICs. We discuss how appropriately designed voltage-controlled MTJs can serve as compact and high-throughput entropy sources for such hardware [1]. We discuss device\/circuit interactions\/trade-offs and show experimental results from a 130nm ASIC interfaced with voltage-controlled MTJs [2], along with projections for more advanced nodes.<\/p>\n

[1] Nanotechnology 34, 495203 (2023)<\/div>\n
[2] C. Duffee et al., arXiv:2412.08017 (2024)<\/div>\n

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Wednesday, 16 April<\/strong><\/p>\n

10:05 am-12:05 pm<\/strong><\/p>\n

Emerging Techniques for Phase Locked Loops<\/strong><\/p>\n

The Phase-locked loop (PLL) performance requirements are getting challenging with the increase of data-rate. This forum will cover different areas of innovations happening to improve the PLL performance to achieve the desired performance. Four presentations will provide a background of many emerging techniques incorporated in the PLL circuit designs as well as in the digital signal processing targeted primarily for wireless application.<\/p>\n

Session Chairs: Somnath Kundu, AMD & Sachin Kalia TI<\/p>\n

Speakers:<\/u><\/strong><\/p>\n

Mike Chen, University of Southern California, USA<\/strong><\/p>\n

\"\"<\/a>Bio: <\/strong>Mike Shuo-Wei Chen is a professor in Electrical Engineering Department at University of Southern California (USC). As a graduate student, he proposed and demonstrated the asynchronous SAR ADC architecture, which has been adopted in industry today for low-power high-speed analog-to-digital conversion products. He currently leads an analog mixed-signal circuit group, focusing on data converters, frequency synthesizers, wireless\/wireline transceiver designs, AI-assisted analog circuit design automation, analog\/neuromorphic computing, non-uniformly sampled circuits and systems.<\/p>\n

Dr. Chen was the recipient of Qualcomm Faculty Award in 2019, NSF Faculty Early Career Development (CAREER) Award, DARPA Young Faculty Award (YFA) both in 2014. His research group received ISSCC Jack Kilby Award in 2022 and best student paper awards from RFIC and CICC. Dr. Chen has been serving as an associate or guest editor of the IEEE Journal of Solid-State Circuit (JSSC), IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS), IEEE Solid-State Circuits Letters (SSC-L), IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), as well as a TPC member in IEEE Solid-State Circuits Society conferences, including the IEEE International Solid-State Circuits Conference (ISSCC), IEEE Symposium on VLSI Circuits (VLSIC), IEEE Custom Integrated Circuits Conference (CICC), and IEEE European Conference on Solid-State Circuits (ESSCIRC). He served as Distinguished Lecturer for IEEE Solid-State Circuits Society (SSCS). He is an IEEE Fellow.<\/p>\n

Title: <\/strong>Trend in Digital PLL Design and Signal Processing Opportunities<\/p>\n

Abstract: <\/strong>A phase locked loop (PLL) that uses a digital control loop is becoming a popular architecture for frequency synthesis, typically known as digital PLL or all-digital PLL. The mostly digital nature of such PLL design allows new digital signal processing (DSP) opportunities. In this talk, I will first overview the recent trend of digital PLL design and several emerging techniques applied in this mostly digital architecture to further enhance its performance and robustness. Specifically, one key design objective is to minimize the spurious tones, which can originate from various non-idealities. I will review those sources and introduce various techniques to mitigate them under different PLL architecture. Lastly, I will go over several silicon prototypes of Fractional-N digital PLL and digital MDLL to validate the effectiveness of those techniques.<\/p>\n

Wanghua Wu, Samsung, USA<\/strong><\/p>\n

\"\"<\/a>Bio: <\/strong>Wanghua Wu is currently a Senior Principal Engineer and Design Manager in Samsung Semiconductor Inc. USA. Her research focus is on advanced cellular RFIC design and frequency synthesis for various wireless applications. She has served on the TPC of several IEEE SSCS conferences and was a SSCS Distinguished Lecturer from 2022 to 2023.<\/p>\n

Title: <\/strong>DTC-Assisted PLLs for Advanced Wireless Transceivers<\/p>\n

Abstract: <\/strong>Fractional-N PLLs employing a digital-to-time converter (DTC) have demonstrated low jitter and high figure-of-merit. This talk starts with the basics of this PLL architecture, followed by advanced analog circuit design and digital calibration techniques to reduce jitter and fractional spurs, and concludes with a few LO chain design examples for WLAN and 5G mm-wave cellular applications.<\/p>\n

Sudhakar Pamarti, University of California, Los Angeles, USA<\/strong><\/p>\n

\"\"<\/a>Bio: <\/strong>Dr. Pamarti is a Professor of ECE at UC Los Angeles. He received his Ph.D. degree from UC San Diego in 2003. He has previously worked for or consulted with both software and IC design companies. He focuses on developing circuit and algorithmic techniques to overcome common impairments in ICs.<\/p>\n

Title: <\/strong>Open loop techniques in precision frequency and phase synthesis<\/p>\n

Abstract: <\/strong>Open-loop techniques such as those based on digital-to-phase converters can enable wide bandwidth frequency\/phase synthesis and compact multi-clock generation. This talk will discuss outstanding challenges to spectral purity in such techniques and the latest techniques to address them.<\/p>\n

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Heein Yoon, Ulsan National Institute of Science & Technology, South Korea<\/strong><\/p>\n

\"\"<\/a>Bio: <\/strong>Heein Yoon received the B.S. and Ph.D. degrees in EE from Ulsan National Institute of Science and Technology (UNIST), Ulsan, South Korea, in 2014, and 2019, respectively. Since 2019, she has been with Qualcomm Inc., San Diego, CA, USA, where she was involved in designing the next-generation cellular transceivers. Since 2022, she has been an Assistant Professor with UNIST. Her current research interests include analog\/RF, mixed-signal ICs.<\/p>\n

Title: <\/strong>Design and Trends of Digital PLLs<\/p>\n

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Abstract: <\/strong>This talk reviews digital Phase-Locked Loops (DPLLs), critical in modern communication and processing systems. It examines fundamental building blocks such as digital phase detectors, loop filters, and digitally controlled oscillators, highlighting their interplay in shaping frequency synthesis, jitter performance, and loop stability. By addressing key performance metrics\u2014lock time, phase noise, power consumption, and dynamic range\u2014this talk underscores the importance of strategic architectural design. Emerging trends and implementation considerations further provide a comprehensive perspective on optimizing advanced and future DPLL solutions.<\/p>\n

\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 <\/strong>[\/vc_column_text][\/vc_column][\/vc_row]<\/p>\n<\/div>","protected":false},"excerpt":{"rendered":"

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\nCICC 2025 Forum Sessions
\nMonday, 14 April
\n10:05 am-12:05 pm
\nHardware and Architectural Strategies for Building Cutting-edge AI Platforms
\nSession Chairs: Sumanth Kamineni, NVIDIA Corporation & Visvesh Sathe, Georgia Institute of Technology
\nSpeakers:
\nUrmesh Thakker, Sambanova, USA
\nBio: Urmish leads the Foundation ML Team at SambaNova …<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":3,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_acf_changed":false,"footnotes":""},"class_list":["post-216","page","type-page","status-publish","hentry"],"acf":[],"yoast_head":"\nForum Sessions - CICC 2025 Archive<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.ieee-cicc.org\/2025archive\/cicc-forum-sessions\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Forum Sessions - CICC 2025 Archive\" \/>\n<meta property=\"og:description\" content=\"[vc_row][vc_column width=”1\/4″][vc_wp_custommenu nav_menu=”20″ el_class=”page-menu”][\/vc_column][vc_column width=”3\/4″ el_class=”contant-page”][vc_column_text css=””] CICC 2025 Forum Sessions Monday, 14 April 10:05 am-12:05 pm Hardware and Architectural Strategies for Building Cutting-edge AI Platforms Session Chairs: Sumanth Kamineni, NVIDIA Corporation & Visvesh Sathe, Georgia Institute of Technology Speakers: Urmesh Thakker, Sambanova, USA Bio: Urmish leads the Foundation ML Team at SambaNova ...\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.ieee-cicc.org\/2025archive\/cicc-forum-sessions\/\" \/>\n<meta property=\"og:site_name\" content=\"CICC 2025 Archive\" \/>\n<meta property=\"article:modified_time\" content=\"2025-04-07T15:03:54+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/www.ieee-cicc.org\/2025archive\/wp-content\/uploads\/sites\/21\/2025\/02\/Thakker-CICC.jpg\" \/>\n\t<meta property=\"og:image:width\" content=\"367\" \/>\n\t<meta property=\"og:image:height\" content=\"393\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data1\" content=\"19 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"WebPage\",\"@id\":\"https:\\\/\\\/www.ieee-cicc.org\\\/2025archive\\\/cicc-forum-sessions\\\/\",\"url\":\"https:\\\/\\\/www.ieee-cicc.org\\\/2025archive\\\/cicc-forum-sessions\\\/\",\"name\":\"Forum Sessions - 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CICC 2025 Archive","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/www.ieee-cicc.org\/2025archive\/cicc-forum-sessions\/","og_locale":"en_US","og_type":"article","og_title":"Forum Sessions - CICC 2025 Archive","og_description":"[vc_row][vc_column width=”1\/4″][vc_wp_custommenu nav_menu=”20″ el_class=”page-menu”][\/vc_column][vc_column width=”3\/4″ el_class=”contant-page”][vc_column_text css=””] CICC 2025 Forum Sessions Monday, 14 April 10:05 am-12:05 pm Hardware and Architectural Strategies for Building Cutting-edge AI Platforms Session Chairs: Sumanth Kamineni, NVIDIA Corporation & Visvesh Sathe, Georgia Institute of Technology Speakers: Urmesh Thakker, Sambanova, USA Bio: Urmish leads the Foundation ML Team at SambaNova ...","og_url":"https:\/\/www.ieee-cicc.org\/2025archive\/cicc-forum-sessions\/","og_site_name":"CICC 2025 Archive","article_modified_time":"2025-04-07T15:03:54+00:00","og_image":[{"width":367,"height":393,"url":"https:\/\/www.ieee-cicc.org\/2025archive\/wp-content\/uploads\/sites\/21\/2025\/02\/Thakker-CICC.jpg","type":"image\/jpeg"}],"twitter_card":"summary_large_image","twitter_misc":{"Est. reading time":"19 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"WebPage","@id":"https:\/\/www.ieee-cicc.org\/2025archive\/cicc-forum-sessions\/","url":"https:\/\/www.ieee-cicc.org\/2025archive\/cicc-forum-sessions\/","name":"Forum Sessions - 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