{"id":21,"date":"2015-07-07T07:23:50","date_gmt":"2015-07-07T14:23:50","guid":{"rendered":"https:\/\/www.ieee-cicc.org\/program\/short-courses\/"},"modified":"2020-03-22T05:16:39","modified_gmt":"2020-03-22T12:16:39","slug":"educational-sessions","status":"publish","type":"page","link":"https:\/\/www.ieee-cicc.org\/2020\/program\/educational-sessions\/","title":{"rendered":"Educational Sessions"},"content":{"rendered":"

Educational Sessions<\/strong><\/h1>\n

Sunday, 22 March<\/h3>\n

Educational Sessions are held on Sunday, March 22nd<\/sup> all-day. Attendance to any of them is included in the standard conference registration. Take this opportunity to learn about new topics from leading engineers in the field.<\/h2>\n

 <\/p>\n

Abstract and Bios for the Speakers and Sessions can be found below.<\/p>\n

 <\/p>\n

Educational Session 1 –<\/strong>RF\/mmW Power Amplifiers<\/strong><\/h3>\n

Chair:\u00a0Debo\u00a0Chowdhur<\/strong>y<\/p>\n

ES1-1. Peter Asbeck, UCSD Bio | Abstract<\/strong>
\n\u2013Title: High Efficiency mm-Wave Power Amplifiers in CMOS-SOI and SiGe for 5G<\/p>\n

ES1-2. Saeid\u00a0Daneshgar, Intel<\/strong>
\n\u2013Title:\u00a0High\u00a0Power Generation for mm-Wave 5G Power Amplifiers in Deep Submicron\u00a0Planar and\u00a0FinFET\u00a0Bulk CMOS<\/p>\n

ES1-3. Sangmin\u00a0Yoo, Michigan State University<\/strong>
\n\u2013Title:\u00a0Digital Power Amplifiers and Transmitters Based on RF Digital-to-Analog\u00a0Converter<\/p>\n

ES1-4. Johanna Yan,\u00a0Maxentric<\/strong>
\n\u2013Title:\u00a0Envelope Tracking for 5G and mm-wave Power Amplifiers<\/p>\n

Educational Session 2 – <\/strong>Phase-Locked Loops<\/strong><\/h3>\n

Chair:\u00a0Woogeun\u00a0Rhee<\/strong><\/p>\n

ES2-1. Robert Staszewski, University College Dublin, Ireland
\n<\/strong>– Title: Beyond All-Digital PLL for RF and Millimeter-Wave Frequency Synthesis<\/p>\n

ES 2-2. Sudhakar Pamarti, UCLA
\n<\/strong>– Title: Basics of Closed- and Open-Loop Fractional Frequency Synthesis<\/p>\n

ES 2-3. Mike Shuo-Wei Chen, USC
\n<\/strong>– Title: Low-Spur PLL Architectures and Techniques<\/p>\n

ES 2-4. Nereo\u00a0Markulic,\u00a0IMEC, Leuven, Belgium
\n<\/strong>– Title: Digital-to-Time Converter-based Subsampling PLLs for Frequency Synthesis and Phase Modulation<\/p>\n

Educational Session 3 – <\/strong>Transceivers (5G \/IoT)<\/strong><\/h3>\n

Chair:\u00a0Yanjie\u00a0Wang<\/strong><\/p>\n

ES3-1. Jongwoo\u00a0Lee, Samsung<\/strong>
\n– Title:\u00a05G RF transceiver design for EN-DC and\u00a0mmWave<\/p>\n

ES3-2. Zhihua Wang,\u00a0Tsinghua\u00a0University<\/strong>
\n–\u00a0Title:\u00a0Design of RF transceivers for\u00a0medical applications in 5G\/IoT era<\/p>\n

ES3-3. Jerald\u00a0Yoo, National\u00a0University of Singapore<\/strong>
\n–\u00a0Title: Body Area Network \u2013 Connecting Things Together Around the Human Body<\/p>\n

ES3-4. Brian Ginsburg, Texas\u00a0Instruments<\/strong>
\n– Title: Fundamentals of Modern mmW Radars<\/p>\n

Educational Session 4 – <\/strong>Data Converters and Interface Circuits<\/strong><\/h3>\n

Chair: Nan Sun<\/strong><\/p>\n

ES4-1. Nima Maghari, University of Florida
\n<\/strong>– Title: Backend Improvement in \u0394\u03a3 ADCs<\/p>\n

ES4-2. Ben Hershberg, IMEC
\n<\/strong>-Title: Ringamp: The Scalable Amplifier We\u2019ve All Been Waiting For?<\/p>\n

ES 4-3. Gabriele Manganaro, Analog Devices Inc.
\n<\/strong>-Title: High Speed Digital-to-Analog Converters \u2013 A tutorial<\/p>\n

ES4-4. Ross Walker,\u00a0 University of Utah
\n<\/strong>-Title: Analog front-ends for large scale neural recording<\/p>\n

Educational Session 5 – MathWorks Sessions<\/h3>\n
\n

ES5-1. Idin Motedayen-Aval, Applications Engineer, MathWorks<\/strong>
\n-Title: Top-Down Design for Mixed-Signal Circuits<\/p>\n

This session will provide an introduction to using Simulink for behavioral simulation of analog\/mixed-signal devices. We will provide a brief tutorial on the tool and its interface, and then explore mixed-signal examples. The talk will also cover connections to downstream circuit design tools.<\/p>\n

    \n
  • Tutorial on Simulink for feedback control systems<\/li>\n
  • Top-Down Design for Mixed-Signal<\/li>\n
  • Examples\n
      \n
    • ADC<\/li>\n
    • PLL<\/li>\n<\/ul>\n<\/li>\n
    • Connections to EDA Tools\n
        \n
      • Co-simulation between Simulink and other analog simulators<\/li>\n
      • Exporting DPI-C (SystemVerilog) models<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n

        ES5-2. Mike Mayer, Applications Engineer, MathWorks<\/strong>
        \n-Title: Introduction to IBIS-AMI<\/p>\n

        The speed of serial communication links (SerDes) continues to climb, and design complexity grows with it. IBIS-AMI models are a standardized way for SerDes designers to share a behavioral model of their chip with downstream system designers such as board-level signal integrity engineers. Creating IBIS-AMI models is now part of the workflow for SerDes designers, but it is a complex and time consuming task which requires knowledge of the IBIS-AMI specification, SerDes, signal integrity, and C programming. This talk covers the background of IBIS-AMI, the basics of the specification, and approaches to generating standard models more efficiently.<\/p>\n

          \n
        • What is IBIS and IBIS-AMI?<\/li>\n
        • Why behavioral models?<\/li>\n
        • IBIS History<\/li>\n
        • IBIS-AMI for SerDes<\/li>\n
        • IBIS-AMI for DDR5<\/li>\n
        • Creating IBIS-AMI models<\/li>\n
        • Using IBIS-AMI models<\/li>\n<\/ul>\n<\/div>\n","protected":false},"excerpt":{"rendered":"

          Educational Sessions
          \nSunday, 22 March
          \nEducational Sessions are held on Sunday, March 22nd all-day. Attendance to any of them is included in the standard conference registration. Take this opportunity to learn about new topics from leading engineers in the field.<\/p>\n

           <\/p>\n

          Abstract and Bios for the Speakers and Sessions can be found below.<\/p>\n

           <\/p>\n

          Educational Session 1 –RF\/mmW Power Amplifiers<\/p>\n

          Chair:\u00a0Debo\u00a0Chowdhury<\/p>\n

          ES1-1. Peter …<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":8,"menu_order":1,"comment_status":"open","ping_status":"closed","template":"","meta":{"_acf_changed":false,"footnotes":""},"class_list":["post-21","page","type-page","status-publish","hentry"],"acf":[],"_links":{"self":[{"href":"https:\/\/www.ieee-cicc.org\/2020\/wp-json\/wp\/v2\/pages\/21","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.ieee-cicc.org\/2020\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.ieee-cicc.org\/2020\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.ieee-cicc.org\/2020\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.ieee-cicc.org\/2020\/wp-json\/wp\/v2\/comments?post=21"}],"version-history":[{"count":0,"href":"https:\/\/www.ieee-cicc.org\/2020\/wp-json\/wp\/v2\/pages\/21\/revisions"}],"up":[{"embeddable":true,"href":"https:\/\/www.ieee-cicc.org\/2020\/wp-json\/wp\/v2\/pages\/8"}],"wp:attachment":[{"href":"https:\/\/www.ieee-cicc.org\/2020\/wp-json\/wp\/v2\/media?parent=21"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}