Session 25 – Advanced Oscillator Concepts
Oak Ballroom, Wednesday Afternoon, September 19
Chair:
Co-Chair: Nobuyuki
Itoh
Oscillators
form the fundamental building blocks of all wireless transceivers. Oscillators
also play an important role in power efficient frequency dividers. The papers in this session examine the basic
trade-offs in oscillator performance and novel low phase noise topologies.
1:30 pm
Introduction
25.1
1:35 pm
Advanced Design Techniques for Integrated Voltage
Controlled LC Oscillators (Invited Paper), P. Kinget, B. Soltanian, S. Xu, S.-A.
Yu and F. Zhang,
25.2
2:25 pm
A 0.5-V 16GHz-20GHz Differential Injection-Locked
Divider in 0.18-µm CMOS Process, H.
Zheng and H. Luong, The Hong Kong University of Science and Technology
An ultra-low-voltage (ULV) differential injection-locked (IL) divider topology
is presented. By making use of a double-balanced active mixer with transformer feedback
(TF) and a TF-VCO, the proposed ULV-IL divider features double-balanced
differential-input differential-output, an ultra-low supply voltage comparable
to the device threshold voltage, and low power consumption. Fabricated in a standard 0.18-µm CMOS process
and operated at 0.5-V supply, the ULV-IL divider measures an input frequency
range from 16.1 GHz to 20 GHz while consuming a total power from 2.75 mW to
4.35 mW. Moreover, two identical proposed ULV-IL dividers with differential
inputs are implemented to achieve quadrature outputs with measured IQ sideband
rejection of better than -35 dBc.
25.3
2:50 pm
A 1V 4GHz-and-10GHz Transformer-Based Dual-Band
Quadrature VCO in 0.18µm CMOS, S.
Rong and H. C. Luong, The Hong Kong University of Science and Technology
A notch-peak cancellation concept is introduced in transformer-based LC
tanks to achieve a dual-band quadrature VCO. Fabricated in 0.18µm CMOS process
and operated at 1V supply, the QVCO prototype measures a stable dual-band
operation from 3.27GHz to 5.02GHz and from 9.48GHz to 11.36GHz. At 4.2GHz and
10GHz, the QVCO measures phase noise at 1MHz offset of -116.3dBc/Hz and
-112dBc/Hz, and sideband rejection ratios of 49dB and 47dB while drawing 6mA
and 10mA, respectively.
Session 26 – Imagers and MEMS
Fir Ballroom, Wednesday Afternoon, September 19
Chair: Sang-Soo Lee
Co-Chair: Makoto
Nagata
This session presents CMOS image sensors for DNA microarrays, electrochemical
and fluorescence detection, as well as a high frame rate imager and a MEMs-based
system for
in-vivo neural imaging.
1:30 pm
Introduction
26.1
1:35 pm
A CMOS Image Sensor for DNA Microarrays, S. Parikh, G.
Gulak and P. Chow, The
An image sensor designed with standard 0.18 µm CMOS technology is used to construct a DNA
microarray scanner. The detection limit of 4590 fluorophores/µm2 is
compared with 4.49 fluorophores/µm2 of a commercial photomultiplier-tube-based
microarray scanner. The performance gap can be reduced by improving optical
coupling, mechanical alignment, laser power supply noise, improved circuit
noise and an increase in the conversion gain.
The CMOS sensor offers multiple-pixels for reduced scan time and an
integrated analog-to-digital converter.
26.2
2:00 pm
Active CMOS Array for Electrochemical Sensing of
Biomolecules, P. Levine, P. Gong, K.
Shepard,
We describe the design of a 4x4 active sensor array for multiplexed electrochemical
biomolecular detection in a 0.25- µm -CMOS process. Integrated potentiostats sense the current
flowing through the on-chip Au electrodes that result from reactions occurring
at the chip surface. Preliminary experimental
results include cyclic voltammetry of several redox species and application to DNA
probe coverage characterization.
26.3
2:25 pm
A CMOS Array Sensor for Sub-800-ps Time-Resolved
Fluorescence Detection, T.-C. Huang, K. Shepard, P. Gong,
This paper describes the design of an active CMOS sensor array for fluorescence
applications which enables time-gated, time-resolved fluorescence spectroscopy.
The 64 x 64 array is sensitive to photon densities as low as 8 x 106 pho-ton/cm2
with 64-point averaging and, through a differential pixel design, has a
measured impulse response of better than 800 ps. Applications include both
active microarrays and high-frame-rate imagers for fluorescence lifetime imaging
microscopy.
26.4
2:50 pm
A High-Speed CMOS Image Sensor with On-chip Parallel
Image Compression Circuits, Y.
Nishikawa, S. Kawahito, M. Furuta, Shizuoka University, and T. Tamura, Photron
Ltd.
This paper presents a high-speed CMOS image sensor with on-chip parallel
image compression circuits. The chip consists of a pixel array, an A/D
converter array with noise canceling function and an image compression
processing element array and buffer memories. The image compression processing
element is implemented with a 4x4 point Discreate Cosine Transform(DCT) and a
modified zigzag scanner with 4 blocks. A prototype high-speed CMOS image sensor
integrating the image compression circuits is implemented based on 1-poly 5-metal
0.25-µm CMOS technology. Image encoding using the implemented parallel image
compression circuits to the image captured by the high-speed image sensor is
successfully performed at 3,000[frame/s].
26.5
3:15 pm
Integration of CMOS and MEMS Technologies in the
Development of a Neural Imaging and Interface Device: Showcase of an Emerging
Bioimaging Technique, D.
Ng, T. Mizuno, T. Tokuda, M. Nunoshita, H. Tamura, Y. Ishikawa, S. Shiosaka and
J. Ohta, Nara Institute of Science and Technology
We combine MEMS technology and CMOS image sensors to develop a neural
imaging and interface device. Pt
electrodes are embedded onto strategic sites on the image sensor for electrical
stimulus and recording. On-chip
fluorescence imaging is realized by integrating LED chips and coating the
device with an excitation light filter.
The fully-packaged device demonstrated simultaneous imaging and
stimulation inside the brain. We also
verified physiologically that the brain is not impaired by the implanted
device.
Session 27 – Substrate Noise Modeling; Behavioral
Models
Pine Ballroom, Wednesday Afternoon, September 19
Chair: Laurence Nagel
Co-Chair:
Recent substrate noise models are the subject of the first part of the
session. The second part includes
applications of behavioral modeling to advanced integrated circuit design.
1:30 pm
Introduction
27.1
1:35 pm
Physical Model for Power Supply Noise and Chip/Package
Co-Design in Gigascale Systems with the Consideration of Hot Spots,
G. Huang, D. Sekar, A. Naeemi, J. Meindl, Georgia Institute
of Technology, K. Shakeri, Cypress Semiconductor
An analytical physical model is derived to predict the first droop SSN
noise for non-uniform current switching conditions. The model not only captures
the impact of package parameters and the distributed nature of power grid and
decap but also addresses the non-uniform current distribution brought by hot
spots. A case study shows that both the frequency domain power noise model and
the projected peak noise value have less than 1% error comparing with SPICE simulation.
27.2
2:00 pm
Simulation and Modeling of Substrate Noise Generation
from Synchronous and Asynchronous Digital Logic Circuits, C.
Hanken, J. Le, T. Fiez and K. Mayaram, Oregon State University
An efficient methodology for simulating the substrate noise generated by complex
synchronous and asynchronous digital logic circuits is presented. By simulating
digital logic at the gate level, the substrate noise generated is used in a
transistor level simulation of the sensitive analog blocks. This approach is
shown to be accurate for both traditional CMOS logic and NULL Convention Logic
(NCL) by correctly modeling critical gate characteristics. Simulations with
different implementations of an 8051 processor core are in good agreement with measurements
from a 0.25µm CMOS test chip.
27.3
2:25 pm
Chip-Level Substrate Noise Analysis with Emphasis of
Vertical Impurity Profile for Isolation, D.
Kosaka, M. Nagata, Kobe University, Y. Murasaka, A. Iwata, A-R-Tec
Slice-and-stack representation of a vertical substrate impurity profile in
F-matrix computation captures isolation effects of deep N-wells as well as guard
rings in chip-level substrate coupling. It is elucidated that the models of
substrate coupling in twin-tub and triple-well designs are dominated by the leakage
of Vss noise and capacitive coupling from Vdd noise, respectively, from measurements
and analysis of a reference test chip in a 0.18- µm CMOS p-type bulk technology.
27.4
2:50 pm
Automated Extraction of Model Parameters for Noise Coupling
Analysis in Silicon Substrates, B. Peterson, K. Mayaram and T. Fiez,
An automated process, requiring the fabrication of only a few simple test structures,
can efficiently characterize a silicon substrate by extracting the process constants of a Z-parameter based
macromodel. The resulting model is used to generate a resistive substrate
network that can be used in noise coupling simulations. This process has been
integrated into the Cadence DFII environment to provide a seamless substrate
noise simulation package which alleviates the need for pre-characterized
libraries.
27.5
3:15 pm
Modeling
and Simulation of Noise in Closed-Loop All-Digital PLLs using Verilog-A, W. Fergusson, R. Patel and W. Bereza,
Altera Corp.
The modeling and simulation of an all-digital PLL is presented. Verilog-A,
owing to its flexibility, is used to create both behavioral and gate-level models
used in system-level and circuit-based simulation. The methodology presented
allows us to simulate the PLL closed-loop and accurately take into account
reference phase noise, DCO phase noise, quantization noise and any excess of
it, allowing us to validate our jitter budget for any given application.
3:40 pm – Break
27.6
3:50 pm
Time-Domain Modeling of a Phase-Domain All-Digital
Phase-Locked Loop for RF Applications, I.
Syllaios, P. Balsara, University of Texas, and R. Staszewski, Texas Instruments
A new all-digital phase-locked loop (ADPLL) for RF wireless applications
has recently been proposed and commercially demonstrated. It replaces
conventional phase/frequency detector and charge pump with a time-to-digital
converter (TDC). Analog frequency tuning of a VCO is replaced with an
all-digital tuning of a digitally-controlled oscillator (DCO). In this paper,
we present novel time-domain modeling and simulation techniques of the ADPLL phase
detection mechanism. The modeling principles are validated through experimental
results.
27.7
4:15 pm
Accurate Modeling of RF Circuit Blocks:
Weakly-Nonlinear Narrowband LNAs, J. Croon, D. Leenaerts and D. Klaassen, NXP
Semiconductors
An extensive behavioral model is presented for weakly-nonlinear narrowband
LNAs. The electrical transfer, intermodulation, and noise properties are all well
described. Performance figures can be predicted for varying source and load
conditions. A Verilog-A implementation facilitates cross-platform simulations.
The model is compared to transistor-level simulations of a simple textbook LNA
and of a state-of-the-art 65nm CMOS LNA in combination with a mixer. Excellent
agreements are achieved.
27.8
4:40 pm
Analytical Eye-diagram Model for On-chip
Distortionless Transmission Lines and Its Application to Design Space
Exploration, M. Hashimoto, J. Siriporn,
This paper proposes a closed-form eye-diagram model for on-chip
distortionless transmission lines with intentionally inserted shunt
conductance. We derive expressions of eye-opening both in voltage and time, by
assuming a piece-wise linear waveform model. The model is experimentally
verified. We also apply the proposed
model to design trade-off analysis.