Session 20 – Analog Techniques
Oak Ballroom, Wednesday Morning, September 19
Chair: Don Thelen
Co-Chair :
This session presents analog circuit design techniques used in frequency
selective filters, image sensors, and temperature and process compensated
oscillators.
8:25 am
Introduction
20.1
8:30 am
An 80MHz Noise Optimized Continuous-Time Bandpass
Filter in 0.25 µm
BiCMOS, A. Kumar and P.
Allen, Georgia Institute of Technolgy
An 80 MHz bandpass filter with a tunable quality factor of 16~44 using an improved
transconductor circuit is presented. The noise optimized biquad structure
achieves SNR of 45dB at IMD of 40dB. The P-1dB compression point and IIP3 of
the filter are -10dBm and -2.68dBm, respectively. The proposed filter gives an
output of 1.87Vpp at -1dB compression point in 3.3V supply and consumes 66mW.
It is fabricated in 0.25 µm BiCMOS.
20.2
8:55 am
A Low Power 44-300 MHz Programmable Active-RC Filter
in 0.18µm CMOS, T. Laxminidhi, V. Prasadu and S. Pavan, Indian
Institute of Technology-
We present a widely programmable fifth order Chebyshev opamp-RC ladder
filter whose 3 dB bandwidth is digitally
tunable over a 7X range, from 44-300
MHz. The opamp uses feed-forward
compensation to achieve high DC gain and wide bandwidth with reduced bias
currents. The principle of ``constant capacitance scaling" is used to maintain the shape of the filter response
when the bandwidth is changed by a large factor. The filter consumes 36 mW from
a 1.8V supply and has a dynamic range of 56.6 dB.
20.3
9:20 am
A Q-enhanced Transformer Coupling Dynamic Dual-Mode
5GHz Bandpass NB / Interference Rejection UWB Filter, B.
Pham and A. Dinh, University of Saskatchewan
This paper presents a fully integrated dual mode Q-enhanced bandpass/notch
filter front-end designed for Narrowband and UWB receivers. Using a simple logic
state to switch its function, the filter can provide bandpass filtering for
channel selection in the NB mode or NB interference rejection in the UWB mode.
A Q-enhanced circuit coupled through a transformer is used to realize the modes.
Using 1.8V supply, the filter consumes 22 mW of power and provides a 32dB
interference rejection in the UWB mode and a gain of 24dB in the NB mode. The design occupies a die area of 1mm2 using
the mainstream 0.18µm CMOS process.
20.4
9:45 am
A Process and Temperature Compensated Two-Stage Ring
Oscillator, K. Lakshmikumar, V. Mukundagiri and S. Gierkink,
Conexant Systems
Local positive feedback in a delay element enables a ring oscillator with
only two stages to oscillate and produce quadrature clocks. Routh-Hurwitz’s criterion is
applied to prove that such a structure can oscillate. An internally generated
power supply from a constant-gm bias keeps the free running frequency to within
±5% from -40 to 125°C over process variations.
The 1.25GHz oscillator in 0.13 µm CMOS draws 3.4mA and has a phase noise of -88dBc/Hz
at 1MHz offset.
10:10 am - Break
20.5
10:25 am
Signal Processing Architectures for Low-Noise
High-Resolution CMOS Image Sensors (INVITED PAPER), S. Kawahito,
In this paper, signal processing architectures for low-noise
high-resolution CMOS image sensors are reviewed and discussed. For low-noise signal readout, a column
amplifier plays an important role for reducing both the noises due to a wideband
output buffer and a pixel source follower. With high amplifier gain, a double-stage
noise canceling technique and an advanced signal processing using oversampling
techniques effectively reduces the noise due to the pixel source follower.
Architectures and topologies for on-chip A/D conversion including pixel
parallel, column parallel and serial schemes are discussed. On-chip column
parallel analog-to-digital (A/D) conversion is particularly important for
low-noise and high-speed signal readout.
20.6
10:50 am
A 1.8 mm2, 11 mA, 23.2 dB-NF, discrete-time
filter for GSM/WCDMA/WLAN using retiming technique, T.
Sano, T. Maruyama, I. Yasui, H. Sato and T. Shimizu, Renesas Technology
The discrete-time filtering is suitable for pass band selection and
anti-alias filtering. Reduction of large switched-capacitor area is a key issue
for the filter. In this paper, we propose the retiming technique and the
optimization of unit capacitor to reduce the number of capacitors. The area of
the filters is 1.8 mm2. Noise Figure (NF) and current consumption in
GSM mode are 23.2 dB and 11 mA, respectively.
20.7
11:15 am
An Equalized Ultra-Wideband Channel-Select Filter with
a Discrete-Time Charge-Domain Band-Pass IIR Filter, A. Yoshizawa and
S. Iida, Sony Corporation
An ultra-wideband channel-select filter with equalized pass-band characteristics
has been implemented with a 0.13 µm CMOS
technology. A discrete-time charge-domain IIR band-pass filter is used to
compensate degradation of the 3rd-order continuous-time LC-LPF and the sinc
response of the 1st-order charge-domain LPF. Measurements show that the IIR BPF
reshapes the pass-band, allowing a 3-dB bandwidth of 500 MHz with a notch at 1
GHz. The filter dissipates 18.8 mW from a 1.2-V supply voltage.
Session 21 – High Performance Processors
and Digital Techniques
Fir Ballroom, Wednesday Morning, September 19
Chair: Aurangzeb Khan
Co-Chair: Henry Chang
This session examines processor architectures, design methods, and
implementations in 90nm and 65nm.
Additional digital techniques are explored in the areas of low power,
reliability and emulation-based verification.
8:25 am
Introduction
21.1
8:30 am
Cell Broadband Engine Processor Design Methodology
(INVITED PAPER), O.
Takahashi, E. Behnen, S. Cottier, P. Coulman, S. Dhong, B. Flachs, P. Hofstee,
C. Johnson and S. Posluszny, IBM
The Cell BE design methodology is described which enables high frequency,
high performance, power efficient, and area optimized design. It includes a hierarchical
design style, clean clock boundary, effective use of non-scan latches, at-speed
scan testing, custom design like synthesized macro, fine grained clock gating
scheme, and cycle accurate power analysis.
21.2
9:20 am
Implementation of the 65nm Cell Broadband Engine, M.
Riley, B. Flachs, S. Dhong, G. Gervais, S. Weitzel, M. Wang, D. Boerstler, M.
Bolliger, J. Keaty, J. Pille, R. Berry,and O. Takahashi, IBM, Y. Nishino, Sony
Computer Entertainment, T. Uchino, Toshiba America
The first generation Cell Broadband Engine processor introduced the CELL Architecture
that consists of nine processor cores fabricated in the 90nm CMOS SOI
technology. This paper describes the
advances made by moving Cell Broadband Engine design from 90nm CMOS SOI to 65nm
CMOS SOI.
21.3
9:45 am
Compact Fault Recovering Flip-Flop with Adjusting
Clock Timing Triggered by Error Detection, S. Yasuda and S.
Fujita, Toshiba Corporation
We propose novel compact fault recovering flip-flops (CFR-FFs) which can recover
timing error and soft error. Two kinds of CFR-FFs are proposed. One is that the
clock rises every cycle, and the other is that the clock rises only when data
has changed. Error rates were experimentally measured by applying a noise
signal to the supply voltage. It is confirmed that the proposed CFR-FFs can
highly suppress the errors more than a conventional FF.
10:10 am - Break
21.4
10:25 am
A 2GHz, 7W (max) 64b Power™ Microprocessor Core, D.
Murray, J. Burnette, B. Campbell, M. Chung, B. Fernandes, S. Ghosh, R. Goel, G.
Hess, H. Huang, Z. Huang, N. Javarappa, P. Kanapathipilai, F. Klass, F. Liu, A.
Mehta, Y. Modukuru, N. Nerurkar, A. Radhakrishnan, S. Santhanam, J. Sugisawa,
S. Sundar, H. J. Tam, R. Wen E. Wu,
J.-C. Yeh, J. Yong, and Z. Zambare, PA Semi, Inc.
The PA6T core is an out-of-order superscalar implementation of the Power Architecture.
Power efficiency is achieved through micro-architecture, logic, and circuit
optimizations. The processor is fabricated in a 65nm, triple Vt, dual oxide 8M
CMOS process. Worst-case power dissipation at 2GHz is 7W.
21.5
10:50 am
Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm
CMOS Technology, B. Campbell, J. Burnette, N. Javarappa and V. von
Kaenel, PA Semi, Inc.
The 64kB L1 caches on the PA6T-1682M SoC CPU are composed of common data
and tag structures fabricated in a 65nm CMOS process and deliver a 1.5 cycle
read latency with 32GB/s bandwidth at 2GHz.
Several features optimize cache performance and power including
power-down safe level shifters, streamlined dual-supply bitslices, fine-grain
clock gating, and a centralized tag floorplan.
21.6
11:15 am
Process-Tolerant Low-Power Adaptive Pipeline under
Scaled-Vdd, S.
Ghosh, P. Batra, K. Kim and K. Roy, Purdue University
We implement a low-power and robust pipeline design methodology suitable
for aggressive voltage scaling while maintaining high frequency operations. We isolate
the critical paths; make them predictable (by design) and ensure they are
activated rarely. At scaled supply (frequency unchanged), possible delay errors
(under 1-cycle) are predicted ahead in time and avoided by adaptively stretching
the clock period. Test-chip implementation in 130nm process shows 40% power
savings with 13% performance loss and ~9.4% area overhead.
21.7
11:40 am
ASIC Design and Verification in an FPGA Environment, D. Markovic, C.
Chang, B. Richards, H. So, B. Nikolic and R. Brodersen,
A unified algorithm-architecture-circuit co-design environment for
dedicated signal processing hardware is presented. The approach is based on a single design
description in the graphical Matlab/Simulink environment that is used for FPGA
emulation, ASIC design, verification and chip testing. The tool flow propagates up circuit-level
performance and power estimates to rapidly evaluate architecture-level
tradeoffs. The common Simulink design
description minimizes errors in translation of the design between different
descriptions, and eases the verification burden. The approach is demonstrated on an ASIC for
4x4 MIMO signal processing.
Session 22 – mm-Wave Systems and Building-Blocks
Pine Ballroom, Wednesday Morning, September 19
Chair:
Co-Chair:
This session will present advances in mm-Wave transmitters and
receivers. In addition the design of
on-chip programmable phase shifters and mm-wave power amplifiers will be
addressed.
8:25 am
Introduction
22.1
8:30 am
mm-Wave Silicon ICs: Challenges and Opportunities
(INVITED PAPER), A. Hajimiri,
Millimeter-waves offer promising opportunities and interesting challenges
to silicon integrated circuit and system designers. These challenges go beyond standard
circuit design questions and span a broader range of topics including wave
propagation, antenna design, and communication channel capacity limits. It is
only meaningful to evaluate the benefits and shortcoming of silicon-based mm-wave
integrated circuits in this broader context. This paper reviews some of these
issues and presents several solutions to them.
22.2
9:20 am
65-nm CMOS, W-Band Receivers for Imaging Applications,
K. Tang, M. Khanpour, S. Voinigescu, University of
Toronto, P. Garcia, C. Garnier, STMicroelectronics
Two 76-92 GHz receivers, featuring 3-stage cascode LNAs coupled through a transformer
to a double-balanced Gilbert-cell mixer and differential DC-5GHz IF buffer, are
reported in 65-nm general purpose (GP) CMOS technology. One receiver features a traditional LNA with
series-series inductive feedback, while the LNA of the second receiver employs
a shunt-series, transformer-feedback cascode stage. Both receivers have a differential down-conversion
gain of 12 dB, an input P1dB of -13 dBm, and a double-sideband noise figure of
9-10 dB. They each occupy an area of 550um×550um and consume 94 mW. An LO-to-RF
isolation of 60 to 59 dB was measured for LO signals in the 80-85 GHz
range. The transformer-feedback provides
a broader bandwidth input match, lower than -10 dB from 74 to 95 GHz.
22.3
9:45 am
A 4-Channel 24-27 GHz UWB Phased Array Transmitter in
0.13µm CMOS for Vehicular Radar, H.
Krishnaswamy and H. Hashemi, University of Southern California
An Ultra-wideband (UWB) Variable-Phase Ring Oscillator (VPRO) and
Phase-Locked Loop (PLL) architecture for integrated phased-array transmitters
is presented. A wideband VPRO operates
at half the desired frequency range, and a squarer is used in each channel to
cover the ±180o phase-shift range completely. A waveform-adaptive,
tunable-narrowband design paradigm is introduced that greatly simplifies the
design of the UWB blocks. A fully-integrated, 4-channel, 24-27 GHz,
phased-array transmitter is implemented in 0.13µm CMOS to validate these
claims.
10:10 am – Break
22.4
10:25 am
A CMOS 22-29GHz Receiver Front-End for UWB Automotive
Pulse-Radars, V.
Jain, P. Heydari, University of California Irvine and S. Sundararaman, Avago
Technologies
The design of a CMOS 22-29GHz pulse-radar receiver (RX) front-end for ultra-wideband
(UWB) automotive radar sensors is presented. Fabricated in a 0.18µm CMOS
process, the 3mm2 RX chip achieves a conversion gain of 35-38.1dB, noise
figure of 5.5-7.4dB and input return loss less than -14.5dB in the 22-29GHz
band. The phase noise of the constituent QVCO is -107dBc/Hz at 1MHz offset from
a center frequency of 26.5GHz. The total dc power dissipation of the RX
including LO/output buffers is 131mW.
22.5
10:50 am
An X- and Ku-Band 8-Element Linear Phased Array
Receiver, K.-J. Koh and G. M. Rebeiz,
This paper presents an 8-element linear phased array receiver adopting RF
phase shifting architecture in 0.18- µm SiGe BiCMOS technology for X- and Ku-band applications.
The receiver shows about 20 dB of power gain per channel at 12 GHz with a 3-dB
gain bandwidth from 8.5 to 14.5 GHz. The rms gain error is less than 0.9 dB and
the rms phase error is less than 6 degree at 6-18 GHz for all the 4-bit phase
states. The minimum NF is 3.85 dB at 10-11 GHz and typical input P1dB at 12 GHz
is -31 dBm with 170 mA of current consumption from a 3.3 V supply voltage. The
overall chip size is 2.2×2.45 mm2.
22.6
11:15 am
A 30-40 GHz 1:16 Internally Matched SiGe Active Power
Divider for Phased Array Transmitters, J.
May and G. Rebeiz, University of California, San Diego
An active 1:16 30-40 GHz power divider was implemented in 0.18 µm SiGe BiCMOS.
The 2 x 2 mm2 splitter exhibits 4.5 ± 1.5 dB total power gain with rms phase
imbalance of less than 6º from 30 to 40 GHz across all 16 channels, consumes
190 mA from a 3.3 V supply, is 15x smaller than an equivalent Teflon-based PCB
transmission-line 1:16 power divider, and is the first 1:16 Ka-Band SiGe active
power divider.
22.7
11:40 am
A 60 GHz Power Amplifier in 90nm CMOS Technology, B.
Heydari, M. Bohsali, E. Adabi and A. Niknejad, University of California
Berkeley
A two-stage 60 GHz 90nm CMOS PA has been designed and fabricated. The
amplifier has a measured power gain of 9.8 dB. The input is gain matched while
the output is matched to maximize the output power. The measured P-1dB =6.7 dBm
with a corresponding power added efficiency of 20%.This amplifier can be used
as a pre-driver or as the main PA for short range wireless communication. The
output power can be boosted with on-chip or spatial power combining.
Session 23 – Methodology and Design for Process
Variability Mitigation
Cedar Ballroom, Wednesday Morning, September 19
Chair:
Co-Chair:
This session addresses different aspects and approaches to mitigate
process variability for yield enhancement for nano-scale CMOS
technologies. The discussed topics
include yield estimation, design/process interaction, and design for yield.
8:25 am
Introduction
23.1
8:30 am
At Tape-out: Can System Yield in Terms of Timing/Energy
Specifications Be Predicted? (INVITED PAPER), A. Papanikolaou,
M. Miranda, P. Marchal, B. Dierickx and F. Catthoor, IMEC
Process variability is introducing uncertainty in all the system level parametric
specifications. Existing variability aware techniques can only capture and
model the variations on system timing and leakage power. This paper proposes a
framework that can capture variability in the dynamic energy consumption as
well. It percolates variability information from semiconductor process to the
Register Transfer Level. This enables to capture the application dynamics and
provide an accurate estimation of dynamic energy along with leakage and timing.
23.2
8:55 am
Process/Product Interactions in a Concurrent Design
Environment (INVITED PAPER), L. Bair, Advanced Micro Devices
The interactions between VLSI processes and the products built in them
continue to perplex those who design and those who manufacture semiconductor
chips. Predicting, preventing, and
minimizing these interactions is compounded by attempts to minimize
time-to-market through concurrent process and design development in integrated
design and manufacturing environments.
Past experience, engineering conservatism, and flexible design
techniques enable successful concurrent deep submicron CMOS VLSI designs.
23.3
9:20 am
Dynamic Supply Noise Measurement with All Digital
Gated Oscillator for Evaluating Decoupling Capacitance Effect,
Y. Ogasahara, M. Hashimoto and T. Onoye, Osaka
University
This paper proposes an all digital measurement circuit called "gated oscillator"
for capturing waveforms of dynamic power supply noise. The gated oscillator is
constructed with standard cells, and thus easily embedded in SoCs. The
performance of the gated oscillator is testified with fabricated test chips in
a 90nm process. Characteristics of decoupling capacitance are discussed
focusing on channel length and distance, based on supply noise waveforms
measured by the gated oscillator.
23.4
9:45 am
An
Embedded 8-bit RISC Controller for Yield Enhancement of the 90-nm PRAM, H. Kim, J. Yoo, H.-J. Yoo, KAIST, and K. Sohn, Samsung
An embedded 8b RISC for advanced memories is designed to control, analyze
and optimize the memory timing and voltage parameters. The processor-based built-in-selfoptimize(BISO)
algorithm is proposed to enhance the memory yield. A test PRAM with the RISC is fabricated in
90nm, 3-metal diode-switch process. By
applying BISO, the PRAM margin window increases by 221%. It operates at 100MHz
and consumes 28.4mW at 1.0V supply voltage. The embedded RISC enables 100Mb/s/pin
read/write throughputs to PRAM.
10:10 am – Break
Session 24 – Advanced Memories
Cedar Ballroom, Wednesday Morning, September 19
Chair :
Co-Chair:
This session covers SRAM alternatives, and describes the evolution of
electronically-programmed fuses to enable redundancy.
10:20 am
Introduction
24.1
10:25 am
A 180 Kbit Embeddable MRAM Memory Module,
J. J. Nahas, T. Andre, B. Garni, C. Subramanian, H.
Lin, S.M. Alam, K. Papworth and W. L. Martino, Jr., Freescale Semiconductor
A 180 Kbit Magnetoresistive Random Access Memory (MRAM) designed for
embedding in a 0.28 micron CMOS process has been developed. The memory cell is
based on a 1-Transistor 1-Magnetic Tunnel Junction (1T1MTJ) bit cell. The
architecture, write driver, and sense amplifier are described. The use of a
Test Register to characterize and optimize the memory design is also discussed.
24.2
10:50 am
A 1.0GHz multi-banked embedded DRAM in 65nm CMOS
featuring concurrent refresh and hierarchical BIST, D.
Anand, J. Covino, J. Dreibelbis, J. Fifield, K. Gorman, M. Jacunski, J.
Paparelli, G. Pomichter, D. Pontius, M. Roberge and S. Sliva, IBM
An embedded DRAM macro fabricated in 65nm CMOS achieves 1.0GHz
multi-banked operation at 1.0V yielding 584 Gbits/sec. The array utilizes a 0.11um2 cell with
20fF deep trench capacitor and 2.2nm gate oxide transfer gate. Concurrent refresh allows for high availability
via a second bank address. At-speed test
and repair is accomplished with a new hierarchical BIST architecture. Measured random cycle time exceeds 333MHz at
1.0V with functional operation from 750mV to 1.5V and densities up to 36.5Mbits
24.3
11:15 am
Electrically Programmable Fuse (eFUSE): From Memory
Redundancy to Autonomic Chips (INVITED PAPER), N.
Robson, J. Safran, C. Kothandaraman, A. Cestero, X. Chen, R. Rajeevakumar, A.
Leslie, D. Moy, T. Kirihata and S. Iyer, IBM
Electrical fuse (eFUSE) has become a popular choice to enable memory redundancy,
chip identification and authentication, analog device trimming, and other
applications. We will review the evolution and applications of electrical fuse
solutions for 180nm to 45nm technologies at IBM, and provide some insight into future uses in 32nm technology
and beyond with the eFUSE as a building block for the autonomic chip of the
future.