Poster Session
Cascade Ballroom, Tuesday Afternoon, September 18
5:30 pm – 7:30 pm
(Authors are at the posters from 5:30 pm – 7:00 pm)
TP-01
A 2.4GHz Efficiency-Enhanced Rectifier for Wireless
Telemetry, K.-H. Chen, J.-H. Lu and S.-I. Liu,
A 2.4GHz full-wave rectifier for wireless telemetry applications is
presented. A conventional full-wave rectifier using diode-connected MOS
transistors suffers from the power loss due to the intrinsic threshold voltage.
In this paper, a full-wave rectifier using a transformer is presented. It has
been fabricated in a 0.18 µm CMOS
process. When input power ranges from 6dBm~12dBm, this proposed rectifier
improves the efficiency of 2.5% compared with the conventional one.
TP-02
Comparative Studies of Common Control Schemes for ReferenceTtracking
and Application of End-point Prediction,
Y. Wu and P. K. T. Mok, Hong Kong University of
Science and Technology
This paper analyzes the reference tracking behavior of Buck converters
using several control schemes including voltage-mode, current-mode and
V2-control from both large-signal and small-signal domains.
TP-03
An Energy Management Circuit for Self-Powered
Ubiquitous Sensor Modules, J. Pan and Y. Inoue,
An energy management circuit is proposed for self-powered ubiquitous
sensor modules using vibration-based energy. With the proposed circuit, the
sensor modules work with low duty cycle operation. Moreover, a two-tank circuit
as a part of the energy management circuit is utilized to solve the problem that
the average power density of ambient energy always varies with time while the
power consumption of the sensor modules is constant and larger than it. In
addition, the long start-up time problem is also avoided with the timing
control of the proposed energy management circuit. The CMOS implementation and
silicon verification results of the proposed circuit are also presented. Its
validity is further confirmed with a vibration-based energy generation. The
sensor module is used to supervise the vibration of machines and transfer the
vibration signal discontinuously. A piezoelectric element acts as the
vibration-to-electricity converter to realize battery-free operation.
TP-04
An Ultra-Low-Power Power Management IC for Wireless
Sensor Nodes, M. Seeman, S. Sanders and J. Rabaey,
A power interface IC is designed and demonstrated to convert and manage
power for a wireless tire pressure sensor node.
Power conversion is performed using on-chip switched-capacitor
converters with size-optimized devices and level-shifting gate drivers. A synchronous rectifier efficiently harvests energy
from an electromagnetic shaker and control circuitry regulates the output
voltage while minimizing power consumption. The converters achieve efficiencies
approaching 80%.
TP-05
A Low Standby Power Flip-flop with Reduced Circuit and
Control Complexity, L. Clark, M. Kabir and J. Knudsen,
A flip-flop using thin and thick gate transistors combines high
performance and low standby power. The design has reduced circuit and
power-down control complexity compared to previous circuits using thick gate
shadow latches for low standby power state storage. Measured test chip results
on a foundry 130 nm process prove the viability of the design. Reduced shadow
latch supply voltage during standby is shown to be effective at mitigating the
drain to bulk leakage components.
TP-06
A 610-MHz FIR Filter Using Rotary Clock Technique, Z.
Yu and X. Liu, North Carolina State University
This paper presents a novel FIR filter design based on a resonant clocking
technique called rotary clock. It utilizes the spatially distributed multiple rotary
clock phases and achieves the full rotary clock power saving potential. Our
filter operates at 610 MHz, delivering a throughput of 39 Gbps. In comparison
with the conventional clock tree based design, it achieves a 34.6% clocking
power saving and a 12.8% overall circuit power reduction.
TP-07
A 186Mvertices/s 161mW Floating-Point Vertex Processor
for
In this paper, a power-efficient vertex processor with a geometry-specific
arithmetic unit, vertex caches, and a vertex texturing unit is presented for mobile
graphics environments. The proposed vertex processor achieves 186 Mvertices/s
of geometry performance which is 1.6 times faster than the previous results
among the IEEE754-compliant arithmetic units, and it supports OpenGL ES 2.0 and
Vertex Shader Model 3.0. The processor is implemented in a 0.18-µm 1P4M CMOS
process.
TP-08
A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter
with Level-Sensitive Latches, V.
Sathe, J. Kao and M. Papaefthymiou, University of Michigan
In this paper we present the design and experimental validation of RF1, a
0.8-1.2GHz frequency-scalable, resonant-clocked FIR filter test-chip with
level-sensitive latches. Designed using a fully automated ASIC flow, RF1 was
fabricated in a 130nm CMOS process with an on-chip inductor and clock
generator. At its resonant frequency of 1.03GHz, RF1 dissipates 132mW, with
clock power accounting for 10.8% of total power dissipation. Resonating 42pF of
clock load, RF1 achieves 76% clock-power efficiency over CV 2f.
TP-09
Addressing Parametric Impact of Systematic Pattern Variations
in Digital IC Design, P.-H. Wang, B. Lee, G. Han, UMC, R. Rouse, P. Hurat and
N. Verghese, Clear Shape Technologies
A simulation methodology to predict changes in circuit characteristics due
to systematic lithography and etch effects is described. This methodology is
used to update an existing circuit netlist to produce accurate delay
calculation and is silicon validated using various transistor and ring
oscillator structures. In a digital IC design flow, the delay variation due to
lithography and etch is calculated and used to identify and repair timing
“hotspots” or parametric failures due to systematic variations.
TP-10
Design Considerations and Benefits of
Three-Dimensional Ternary Content Addressable Memory, E. C. Oh and P.
Three dimensional (3D) ternary content addressable memory (TCAM) has been designed
in a 0.18 µm fully depleted silicon on insulator (FD SOI) 3D IC process. This
paper demonstrates that a 3D TCAM with three tiers can achieve 40% matchline
capacitance reduction and 21% power reduction compared to a TCAM in a
conventional single-tier process. This paper also discusses design considerations
of 3D TCAM including partitioning methods for multiple tiers and layout methods
of interconnects.
TP-11
A 37 ppm/°C Temperature Compensated CMOS ASIC with ±16
V Supply Protection for Capacitive Microaccelerometers, H. Ko, S.-J.
Paik, B. Choi, D.-I. Cho,
A high reliability CMOS-MEMS hybrid microaccelerometer system is
presented. To enhance the temperature response and to minimize die-to-die
variations, a low-noise continuous-time front-end architecture with
temperature-compensation and parasitic-cancellation is proposed. The
temperature coefficients of the output bias and the scale factor are measured
to be 37 ppm/°C and 27 ppm/°C, respectively. The bias instability level is
measured to be 42 µg. The integrated ±16 V supply protection gives the enhanced
system reliability and reduced form-factor.
TP-12
A 500 MHz Low Phase-Noise A1N-on-Silicon Reference
Oscillator, H. M. Lavasani, R. Abdolvand and F. Ayazi, Georgia
Institute of Technology
This paper presents a 496MHz reference oscillator using a high-Q
lateral-mode AlN-on-Si micromechanical resonator that does not require DC
voltage for operation. The sustaining amplifier consists of an inductorless
high-gain CMOS transimpedance amplifier that is optimized for low phase-noise.
The resonator is designed to have high quality factor in air (Q~3800) with low
impedance. The measured phase-noise at 1kHz is -92dBc/Hz with phase-noise floor
below -147dBc/Hz (exceeding GSM phase-noise requirement by 2dB and 28dB, respectively).
TP-13
1.1 TMACS/mW Load-Balanced Resonant Charge-Recycling
Array Processor, R.
Karakiewicz, R. Genov, University of Toronto and G. Cauwenberghs, University of
California San Diego
A resonant adiabatic mixed-signal 128x256 array processor achieves 1.1 TMACS
(tera-multiply-accumulates per second) per mW of power from a 1.6V DC supply.
The 1.9x9 sq. micron 3T NMOS unit cell with single-wire pitch multiplexed
bit/compute line provides charge-conserving 1b-1b multiplication and
single-wire analog accumulation. A stochastic data modulation scheme minimizes
on-chip capacitance variability maintaining clock oscillations near resonance.
TP-14
Optimization of SC Sigma Delta Modulators based on
Worst-Case-Aware Pareto-Optimal Fronts, J. Zou, H.
Graeb, D. Mueller and U. Schlichtmann, Techn. Univ. Muenchen
This paper presents an optimization method for switched-capacitor
sigma-delta modulators. The SNR performance is maximized while considering the
performance capability of the critical building block, i.e. the Op Amp.
Performance space exploration is applied to find the feasible region of the
building block’s performance, which is represented by a Pareto optimal front. Through
worst-case analysis on design points of the nominal Pareto front, a
worst-case-aware Pareto-optimal front can be computed. The maximized SNR and
the corresponding yield will be presented. The proposed optimization process is
efficient and can be accomplished in some hours.
TP-15
Obtaining Frequency Sensitivities to Variations
Analytically from Parameterized Nonlinear Oscillator Phase Macromodels, Z. Wang and J.
Roychowdhury,
System-level variability analysis and design centering for oscillators
relies on fast and accurate methods for obtaining the parametric sensitivities
of higher-level performances (such as center frequency) directly from phase
macromodels. We present an efficient and elegant method, involving no numerical
simulation, for finding parametric sensitivities of oscillator frequencies
directly from nonlinear phase domain macromodels. We validate the method,
termed FS-PPV, on numerically extracted ring and LC oscillator PPV macromodels,
as well as on a purely analytical exact PPV macromodel for idealized ring
oscillators. We apply FS-PPV to find statistical distributions of oscillator
center frequencies and validate these distributions against Monte-Carlo
simulations. FS-PPV achieves speedups of more than 3000×.
TP-16
Modeling and Validation of Silicon Contour-Based
Extraction and Simulation of Non-Uniform Devices, T.
Devoivre, STMicroelectronics, R. Rouse, N. Verghese and P. Hurat, Clear Shape
Technologies
A current density-based model is proposed to predict the drawn current of transistors
that exhibit non-uniform geometry. Using the active and poly contours of the
actual transistor shape from a lithography-like simulation, the current density
model is integrated over the transistor width to obtain its drawn current and
equivalent transistor parameters for circuit simulation. Comparison to Silicon
drive current measurements of Poly T and Active T structures on a ST 65nm process
show excellent correlation.
TP-17
Standard Cell and Custom Circuit Optimization using
Dummy Diffusions through STI Width Stress Effect Utilization, R. O. Topaloglu,
University of California
Starting at the 65nm node, stress engineering to improve performance of transistors
has been a major industry focus. An intrinsic stress source - shallow trench
isolation - has not been fully utilized up to now for circuit performance
improvement. In this paper, we present a new methodology that enables the
exploitation of STI stress for performance improvement of standard cells and
custom integrated circuits. We start with process simulation of a 65nm STI
technology, and generate mobility models for STI stress based on these simulations.
Based on these models, we are able to perform STI stress-aware modeling and
simulation using SPICE. We then present our optimization of STI stress in
standard-cell and custom designs using active-layer (dummy) fill insertion to
alter the STI widths. Circuit level experimental results are based on a
miscellaneous ring oscillator, which is known to correlate well to silicon.
Using a generic 65nm cell library, we show that the STI-optimized designs
provide up to 8% improvement in clock frequency. The frequency improvement
through exploitation of STI stress comes at practically zero cost with respect
to area and wirelength.
TP-18
FinFET SRAM: Optimizing Silicon Fin Thickness and Fin
Ratio to Improve Stability at iso Area, D. Lekshmanan, A. Bansal and K. Roy,
In FinFET SRAM, width quantization and variation in silicon thickness are
major challenges impacting stability and manufacturability. We propose a
methodology to improve the stability of an SRAM cell by co-optimizing the
different transistor fin combinations (sizing of different transistors) and
silicon thickness (of FinFET) at iso-area. At iso-area, read SNM can be
increased approx. 2X by varying fin-combination while decreasing write margin
by 17%. Further, at iso-area and stability, we propose that silicon fin thickness
constraint can be relaxed in FinFETs to improve the manufacturability and reduce
process variability. Increasing the silicon fin thickness by approx. 50%,
degrades read SNM by 10% while negligibly affecting write margin and increasing
access time by 36%. Increased silicon thickness reduces body thickness
variation in FinFETs, resulting in reduced device mismatch among transistors in
an SRAM cell.
TP-19
A Comprehensive Phase-Transfer Model for Delay-Locked
Loops, J.
Burnham, Stanford University, G.Y. Wei, Harvard University, C.-K. K. Yang,
UCLA, and H. Hindi, PARC
This paper presents a comprehensive model for analyzing the behavior of an
analog delay-locked loop (DLL). Unlike previous models, the proposed version includes
both constant and variable phase-offset terms, making it possible to calculate
jitter transfer characteristics, stability, and static phase errors from a
single unified model. The topology more closely approximates the underlying
architecture of the DLL, resulting in improved accuracy and enabling better
tradeoffs between bandwidth, stability, and power.
TP-20
Efficient Frequency-Domain Simulation of Massive Clock
Meshes Using Parallel Harmonic Balance, W. Dong, P. Li and X. Ye,
High performance IC designs impose stringent design specifications on
clock distribution networks, where clock skews must be well controlled even
under the presence of environmental and process variations. As a result, clock
meshes are gaining increasing popularity due to their inherent low skew and
immunity to variations. While clock meshes are often analyzed in time-domain
for the purpose of verification as well as tuning, the massive couplings within
the passive mesh structure and in between a large number of clock drivers are
challenging to handle. In contrast, frequency-domain steady-state simulation
techniques such as harmonic balance (HB) are specifically advantageous since
the massive passive mesh structure can be rather compactly represented using
matrix transfer function matrices at a discrete set of harmonic frequencies.
The remaining challenge, however, is to develop harmonic balance techniques
that can efficiently simulate highly nonlinear steady-steady problems
corresponding to a large number of tightly coupled clock drivers. In this
paper, we present a hierarchically preconditioned algorithm that is
particularly suitable to clock mesh analysis. Moreover, we show that the parallelizable
nature of our algorithm allows further runtime improvement of large clock mesh
analysis via parallel processing.
TP-21
Low-Voltage Multi-Mode Gm-C Channel
Selection Filter for
A third-order Butterworth low-pass filter implemented with the
transconductors was designed by TSMC 0.18-µm CMOS process. The measurement
results show that the tuning range and
the linearity performance would be suitable for the wireless specifications of
GSM, Bluetooth cdma2000, and Wideband CDMA. In the design, the maximum power
consumption at the highest cutoff frequency is 2 mW under a 1-V supply voltage.
TP-22
Multi-Mode Modulator and Frequency Demodulator
Circuits for Gb/s Data Rate 60 GHz Wireless Transceivers, A.
Valdes-Garcia, S. Reynolds and T. Beukema, IBM TJ Watson
Compact RF circuits that enable Gb/s wireless links on integrated 60 GHz
radios are presented. A multi-mode modulator performs a variety of signaling
schemes including MSK directly from a digital bit-stream and also performs the
IF up-conversion. An FM discriminator operates at an IF frequency of 9 GHz with
a sensitivity of -70 dBm referred to the RF input and yields an output digital bit
stream. Implemented in a SiGe 0.13 µm BiCMOS process as part of a transceiver
chipset, the modulator and demodulator occupy an area of only 0.03mm2
and 0.02mm2, respectively. The performance of the proposed circuits
is verified individually and also in a HDTV 2 Gb/s MSK link.
TP-23
CMOS Low Noise Amplifier with Capacitive Feedback
Matching, E. Adabi and A. Niknejad,
A capacitive shunt feedback LNA input matching network is demonstrated
which offers matching, good noise performance, low component count and low area
consumption. A prototype 9GHz LNA vehicle amplifier is designed and fabricated in
a 130nm RF-CMOS process. The measured amplifier has 20.5dB of gain at 8.8GHz with
input and output match of -15dB and -8dB respectively. It has 1.4GHz of 3dB-bandwidth
around 9GHz with the noise figure of 1.7dB at the center frequency and below
2dB across the band. Large signal measurements reveal that the amplifier can
deliver -2dBm of power to the 50 ohm output load at its 1dB compression point.
It draws 23mA of current from a 1.2V supply. The chip occupies an area of
0.64mm2.
TP-24
A 750Mb/s 12pJ/b 6-to-10GHz Digital UWB Transmitter,
V. Kulkarni, M. Muqsith, H. Ishikuro and T. Kuroda,
Keio University
In this paper, an all-digital, ultra-wideband transmitter in 0.18 µm CMOS is presented. The transmitter realizes
Bi-phase modulation scheme and generate 500ps duration pulses with center
frequency of 8GHz. Measured results show that the transmitter consumes 12pJ/b
to achieve data rate of 750Mb/s. An optional embedded on-chip antenna and a
power amplifier operating in 6-10GHz band are also designed as a future low
cost solution for short distance communications.
TP-25
A 3.1-8.0 GHz MB-OFDM UWB Transceiver in 0.18µm CMOS, H. Zheng, S. Lou, D. Lu, C. Shen, T.
Chan and H. Luong, The Hong Kong University of Science and Technology
This paper presents a complete CMOS dual-conversion zero-IF2 transceiver
for 9-band MB-OFDM UWB systems from 3.1 to 8.0 GHz. The transceiver integrates
all building blocks including a variable-gain wideband LNA, a single mixer for
both RF down and up conversions in RX and TX, a fast-settling frequency
synthesizer, and IQ ADCs and DACs. Fabricated in a standard 0.18-µm CMOS
process, the receiver measures maximum S11 of -13dB, maximum NF of 8.25 dB,
in-band IIP3 of better than -13.7 dBm, and variable gain from 25.3 to 84.0 dB.
IQ path gain and phase mismatch of the receiver chain are measured to be 0.8 dB
and 4o respectively. The transmitter achieves a minimum output P-1dB of -8.2
dBm, sideband rejection of better than -42.2 dBc, and LO leakage of smaller
than -46.5 dBc.
TP-26
A -90dBm Sensitivity 0.13µm CMOS Bluetooth Transceiver
Operating in Wide Temperature Range, K.Agawa,
H. Majima, H. Kobayashi, M. Koizumi, S. Ishizuka, T. Nagano, M. Arai, Y.
Shimizu, G. Urakawa, N. Itoh, M. Hamada and N. Otsuka, Toshiba Corporation
A 2.4GHz 0.13 µm CMOS transceiver
achieves high performance between -40C and +90C. A low-IF receiver and direct-conversion
transmitter architecture is employed. A
temperature compensated receiver chain including LNA achieves a high
sensitivity of -89.6dBm even in the worst environmental condition. Linearity optimization for a transmitter chain
including a variable biasing circuit in PA reduces the second harmonics of TX
signals so that it suppresses the VCO pulling and keeps the carrier frequency
drift within 18kHz.
TP-27
On IIP2 Improvement by Injecting DC Offset at the
Mixer in a Wireless Receiver, I.
Elahi and K. Muhammad, Texas Instruments
We present a digital calibration technique for improving IIP2 by injecting
DC offset at the mixer. By controlling amplitude of the injected DC, IIP2 degradation
due to LO leakage at the input of RF amplifiers can be compensated. Mathematical
analysis and measurement data for a quad-band GSM/GPRS receiver implemented in
90-nm digital CMOS process are presented. Calibrated IIP2 of 50dBm is reported
at LNA input.
TP-28
ECO chip: Energy Consumption Zeroize Chip with a
953MHz High-Sensitivity Radio Wave Detector for Standby Mode Applications, T. Umeda and S.
Otaka,
ECO chip (energy consumption zeroize chip) for standby mode applications
is presented. ECO chip detects 953MHz band radio waves from a remote control
(RC) by using a high-sensitivity rectifier and switches on/off the main power supplies
of applications with ultra-low power consumption. Sensitivity of -42dBm and
communication distance of 10m from 13dBm output RC are achieved with 0.14uW
power consumption.
TP-29
On the Transient Behavior of Injection Locked LC
Oscillators, N.
Lanka, S. Patnaik and R. Harjani, University of Minnesota
An analytical framework has been developed to describe the transient
behavior of negative resistance injection-locked oscillators based on Adler's
equation. Design insights are provided by using a combination of analytical simplifications
and graphical interpretation. It has been shown that injection locking can be
used to meet the requirements for fast hopping systems like the MBOA-UWB specification.
The theoretical analysis and design solutions have been verified by extensive
simulations on real CMOS processes.
TP-30
A Wideband CMOS Linear Digital Phase Rotator, H. Wang and A.
Hajimiri, California Institute of Technology
This paper presents a 10-bit wideband Cartesian phase rotator with a novel
linear digital VGA implemented in a 0.13 µm CMOS process. The VGA topology is robust to
device modeling uncertainties and PVT variations. The system provides 7.8dB
voltage gain with -3dB bandwidth of 7.6GHz. A maximum phase error of 2º has
been achieved for a phase shifting range of 360º with 32 phase steps of 11.25º.
The capability to compensate for mismatched quadrature inputs is also demonstrated.
TP-31
Low-Power CMOS Energy Detection Transceiver for UWB
Impulse Radio System, T.-A. Phan, V. Krizhanovskii, S.G. Lee,
Information and
This paper presents an ultra low-power non-coherent transceiver (TRx)
operating in 3-5 GHz band using energy detection (ED) receiver for impulse
radio ultra-wideband (IR-UWB) systems. The proposed low-complexity ED receiver consists
of a wideband LNA, a squarer, an analog integrator, and a sample and hold
circuit, of which only the LNA consumes static current. The transmitter consists
of a pulser which is based on the ON/OFF operation of an LC oscillator.
Fabricated in 0.18-µm CMOS technology with 1.5 V supply, measurements show the
FCC-compliant output pulses with the duration of 3.5 ns, which corresponds to
520 MHz bandwidth. Maximum pulse rate is up to over 200 MHz. The pulser
dissipates only the dynamic current with average energy of 16.8 pJ per pulse,
and the receiver dissipates 3.5 mA of static current. The receiver shows 9 dB
of NF and a sensitivity of -70 dB.
Transceiver die size is 1.3 x 1mm.