Session 16 – Signal and Data Processing
Oak Ballroom, Tuesday Afternoon, September 18
Chair:
Co-Chair:
This session explores new signal and data processing integrated circuits
for a diverse reange of applications including medical devices, video
processing and high speed communications.
2:00 pm
Introduction
16.1
2:05 pm
Cochlear Implant Signal Processing ICs (INVITED PAPER), B.
Swanson, M. Goorevich, T. Nygard, Cochlear Ltd., E. Van Baelen, K. Van Herck,
Cochlear Technology Center, and M. Janssens, NXP
The Nucleus Freedom cochlear implant system enables a profoundly deaf
person to hear. The system consists of a surgically implanted stimulator and a battery-powered
external sound processor. The processor is based on a 0.18 µm CMOS ASIC
containing four DSP cores. The signal processing includes a two-microphone
adaptive beamformer, a 22-channel quadrature FFT filterbank, multi-band
automatic gain control, a psycho-acoustic masking model and non-linear
compression. The key design challenge was power consumption.
16.2
2:55 pm
An 81.6 GOPS Object Recognition Processor Based on NoC
and Visual Image Processing Memory, D.
Kim, K. Kim, J.-Y. Kim, S. Lee and H.-J. Yoo, KAIST
An 81.6 GOPS object recognition processor is developed by using NoC and
Visual Image Processing (VIP) memory. SIFT (Scale Invariant Feature Transform)
objects recognition requires huge computing power and data transactions among
tasks. The chip integrates 10 SIMD PEs for data/task level parallelism while
the NoC facilitates inter-PE communications. The VIP memory searches local
maximum pixel inside a 3x3 window in a single cycle providing 65.6 GOPS. The
proposed processor achieves 15.9fps SIFT feature extraction at 200 MHz.
16.3
3:20 pm
A Cost-effective Digital Front-End Realization For
20-bit Sigma-Delta DAC in 0.13µm CMOS,
R. Chen, L. Liu and D. Li, Tsinghua
University
A cost-effective digital front-end used in 20-bit sigma-delta DAC is
described in this paper. It includes an interpolator and a sigma-delta modulator.
Mixed-radix number representation algorithm combined with poly-phase filtering technique
and high efficiency hardware realization method are used to achieve high data
conversion precision and reduce the area of the interpolator. A single bit
distributed feedback structure is adopted for DSM to shape quantization noise.
The overall digital front-end achieves above 130dB dynamic range.
3:45 pm – Break
16.4
4:00 pm
A 0.25µm 0.92mW per Mb/s Viterbi Decoder Featuring
Resonant Clocking for Ultra-Low-Power 54Mb/s WLAN Communication, F.
Carbognani, S. Haene, M. Arrigo, C. Pagnamenta, F. Buergin, N. Felber, H.
Kaeslin and W. Fichtner, ETH Zurich
Resonant clocking is applied to a Viterbi decoder for ultra-low-power WLAN
communication. Clock skew balancing and excessive cross-over currents are identified
as the most relevant issues: H-clock-trees and a new latch circuit are proposed
as power-efficient design solutions. The 30000 gate-equivalent core in a 0.25
µm CMOS process dissipates 50 mW at
54Mb/s throughput (1.75 V), with about 27% power savings compared to an
equivalent circuit with one-phase single-edge-triggered clocking and a recently
published competitor.
16.5
4:25 pm
A High-Throughput Maximum a posteriori Probability
Detector, R.
Ratnayake, G.-Y. Wei,
This paper presents a maximum a posteriori probability (MAP) detector,
based on a forward-only algorithm that can achieve high throughputs. The MAP
algorithm is optimal in terms of bit error rate. The proposed detector utilizes
a deep-pipelined architecture implemented in skew-tolerant domino and experimentally
measured results verify the detector can achieve throughputs greater than
750MHz while consuming 2.4W. The detector is implemented in a 0.13µm CMOS
technology and has a die area of 9.9 mm2.
16.6
4:50 pm
A 3.3-Gbps Bit-Serial Block-Interlaced Min-Sum LDPC
Decoder in 0.13µm CMOS, A.
Darabiha, A. Chan Carusone and F. Kschischang,
A bit-serial architecture for multi-Gbps LDPC decoding is demonstrated to alleviate
the routing congestion which is the main limitation for LDPC decoders. We
report on a 3.3-Gbps 0.13- µm CMOS
prototype. It occupies 7.3-mm2 core area with 1416-mW maximum power
consumption from a 1.2-V supply. We demonstrate how early termination and
supply voltage scaling can improve the decoder energy efficiency. Finally, the
same architecture is applied to a (2048, 1723) LDPC code compliant with the
10GBase-T standard.
Session 17 – Wideband Techniques
Fir Ballroom, Tuesday Afternoon, September 18
Chair:
Co-Chair: Ed Van Tuijl
This session focuses on the design of high-speed wireline circuits for
data connectivity up to 100 Gb/s. Novel
architectures and methodologies are presented.
2:00 pm
Introduction
17.1
2:05 pm
A Heterodyne Phase Locked Loop with GHz Acquisition
Range for Coherent Locking of Semiconductor Lasers in 0.13µm CMOS, F.
Aflatouni, O. Momeni and H. Hashemi, USC
A heterodyne electro-optical phase-locked loop (EOPLL) architecture is
proposed that can lock the frequency and phase of semiconductor lasers. An
aided-acquisition circuit inspired by the combination of RF image-rejection
receivers and digital PLL architectures is used to extend the
frequency-acquisition range. An
integrated circuit prototype is implemented in a 0.13 µm CMOS technology and includes a wideband
transimpedance amplifier and PLL circuitry. Measurement results for the locking
of Vertical Cavity Surface Emitting Lasers are reported.
17.2
2:30 pm
A Synthesis-based Bandwidth Enhancing Technique for
CML Buffers/Amplifiers, D.
Pi, B.-K. Chun and P. Heydari,
A synthesis-based bandwidth enhancing technique for current-mode-logic
(CML) buffers/amplifiers is presented, which achieves
bandwidth-enhancement-ratio (BWER) of 4.84, close to a proven theoretical upper
limit of 4.93. By employing a complete step-by-step design methodology, the
proposed technique can be applied to any load condition, which is characterized
by the ratio between the load capacitance and the output capacitance of the
transconductor cell. Several prototype buffer/amplifier circuits are designed
using lower order passive networks to save chip area. The test chip is
fabricated in a 0.18 µm CMOS process,
and measurements show a BWER of 3.8.
17.3
2:55 pm
Towards a sub-2.5V, 100-Gb/s Serial Transceiver
(INVITED PAPER), S.
Voinigescu, R. Aroca, S. Nicolson, T. Chalvatzis, University of Toronto, P.
Chevalier, P. Garcia, C. Garnier and B. Sautreuil, STMicroelectronics, T.
Dickson, IBM
This paper describes first a half-rate, 2.5V, 1.4W, 87-Gb/s transmitter
with on-chip PLL fabricated in a production 130nm SiGe BiCMOS process. Next,
the most critical blocks required for the implementation of a full-rate
100-Gb/s serial transceiver are explored. State-of-the art 105-GHz, SiGe HBT
static frequency dividers and VCOs operating from 2.5V, as well as 65-nm CMOS,
1.2V, 90-GHz static frequency dividers, low-phase noise VCOs, and 100-GHz clock
distribution network amplifiers are fully characterized.
3:45 pm - Break
17.4
4:00 pm
Future Microprocessor Interfaces: Analysis, Design and
Optimization (INVITED PAPER), B.
Casper, G. Balamurugan, J. Jaussi, J. Kennedy, M. Mansuri, F. O'Mahony and R.
Mooney, Intel Corporation
High-aggregate bandwidth interfaces with minimized power, silicon area,
cost and complexity will be essential to the viability of future microprocessor
systems. Optimization of microprocessor interfaces at the system level is crucial
to providing the most cost-effective and efficient solution. This paper details
a comprehensive interconnect and system level analysis method that can be used to accurately evaluate
platform-level tradeoffs and has been correlated to link measurements with 10%
accuracy. System tradeoffs with respect to interconnect quality, equalization, modulation,
clock architecture are shown. Interconnect and circuit density improvements are
identified as a promising research direction to maximize the bandwidth and
power efficiency of future microprocessor platforms.
17.5
4:50 pm
Time-Variant Characterization and Compensation of
Wideband Circuits, A.
Amirkhany, M. Horowitz, Stanford
University, A. Abbasfar, J. Savoj, Rambus, Inc.
Many wideband circuits use interleaving to extend bandwidth leaving them
with a cyclically time-variant output.
This paper describes a technique for characterization of these types of
circuits based on Least-Squares Estimation of the time-varying response of
circuits. Applying the methodology to a 90-nm, 12-GS/s 8-bit
digitally-equalized DAC, shows significant timing varying behavior. Furthermore, using the data obtained from
characterization to construct linear time-variant compensation improves the DAC
signal-to-distortion ratio by at least 6 dB.
17.6
5:15 pm
High-Voltage-Tolerant I/O Circuit Design for USB
2.0-Compliant Applications, M.-J.
Kim, T.H. Lee,
We present design strategies of high-voltage tolerant I/O circuits for interfaces
of 3.3V or higher. The test vehicle is a USB 2.0-compliant I/O circuit. This is
a challenging example because USB 2.0 requires substantial over-voltage
tolerance from -1V to 5.25V. In addition, USB 2.0 requires continuous
monitoring of this condition and protection when no power is present. The
proposed concept is demonstrated in a 90nm CMOS process.
Session 18 – Compact Modeling for Analog and RF
Pine Ballroom, Tuesday Afternoon, September 18
Chair: Rob Jones
Co-Chair: Hong-Ha
Vuong
This session presents advanced compact models and modeling/synthesis
approaches to address analog and RF applications.
2:00 pm
Introduction
18.1
2:05 pm
PSP-Based Scalable MOS Varactor Model,
(INVITED PAPER), J. Victory,
Z. Yan, J. Cordovez,
Jazz Semiconductor, Z. Zhu, Q. Zhou, W. Wu, G. Gildenblat, Arizona State
University, C. McAndrew, Freescale Semiconductor, F.
Anderson, IBM, J. Paasschens, NXP Semiconductors, R.
van Langevelde, Philips Research, P. Kolev, Qualcomm, R. Cherne, Intersil Corp. and C. Yao, Analog Devices
18.2
2:55 pm
An Accurate Scalable Compact Model for the Substrate
Resistance of RF MOSFETs, B.
Parvais, M. Dehan, A. Mercha, S. Decoutere, IMEC, S. Hu, Shanghai IC R&D
Center
A new scalable compact model for the substrate resistance of multi-finger MOSFETs
is presented and validated up to 50 GHz on a 90 nm CMOS technology. The physical foundation, used to capture the
2D distributed nature of the well resistance, provides a more accurate
description of different layout styles over a wide range of geometries. The
model is used to determine the folding for minimum substrate resistance and is
implemented straightforwardly with the PSP model.
18.3
3:20 pm
Synthesis of Optimal On-Chip Baluns, S. Kapur, D.
Long, R. Frye, Integrand Software, Y.-C. Chen, M.-H. Cho, H.-W. Chang, J.-H. Ou
and B. Hung, UMC
We describe a method for synthesizing on-chip baluns. The method involves creating a scalable
transformer model from electromagnetic simulations, followed by a search
through design space to find an optimal balun.
We used this method to design 90nm RFCMOS baluns. The baluns have
insertion loss less than 1.5dB, phase imbalance of 0.25 degrees and amplitude
imbalance of 0.25dB. These
characteristics are equal to or better than off-chip baluns while requiring
significantly less area.
3:45 pm – Break
18.4
4:00 pm
An Integrated Modeling Paradigm of Circuit Reliability
for 65nm CMOS Technology, W.
Wang, R. Vattikonda, Y. Cao, Arizona State University and V. Reddy, A.
Krishnan, S. Krishnan, Texas Instruments
The de facto modeling method to analyze channel-hot-carrier (CHC) is based
on substrate current (Isub), which becomes increasingly problematic with technology
scaling as various leakage components dominate Isub. In this work, we present a
unified approach that directly predicts the change of key transistor parameters
under various process and design conditions, for both negative-bias-temperature-instability
(NBTI) and CHC degradation. Using the general reaction-diffusion model and the
concept of surface potential, the proposed method continuously captures the
performance degradation across subthreshold and strong inversion regions.
Models are comprehensively verified with an industrial 65nm technology. We
benchmark the prediction of circuit performance degradation with measured ring
oscillator data and simulations of an amplifier.
18.5
4:25 pm
Mismatch Characterization of Ring Oscillators,
A. Balankutty, T.-C. Chih, C.-Y. Chen and P. Kinget,
We investigate frequency matching of ring oscillators to study matching of
non-static operation of identical high speed analog, digital and RF circuits. The
oscillator test structures on a 0.25 µm CMOS technology operate in the 500MHz to 3GHz
range. The non-static matching experimental results are compared to predictions
based on DC matching parameters. Stage
averaging versus device size averaging for constant frequency designs is
investigated. Global variations and long distance matching are also examined
and compared.
18.6
4:50 pm
The Advanced Compact MOSFET (ACM) Model for Circuit
Analysis and Design (INVITED PAPER), C.
Galup-Montoro, M. Schneider, O. Siebel, Federal University of Santa Catarina, A.
Cunha, Federal University of Bahia, F. Sousa, Federal University of Rio Grande
do Norte, and H. Klimach, Federal University of Rio Grande do Sul
Most of the new generation compact models for the MOSFET have many commonalities
since they are based on the same main approximations: gradual channel,
charge-sheet, and depletion charge linearization. In this study we show that if
we include some additional physics-consistent conditions for the MOSFET
equations we obtain a very compact model that we call the advanced compact
MOSFET (ACM) model. The core ACM model, design-oriented equations, parameter
extraction, and a design example are presented.
Session 19 – Front-Ends and Synthesizers for
Communication Applications
Cedar Ballroom, Tuesday Afternoon, September 18
Chair:
Co-Chair: Rick Carley
This session begins with presentations on four receiver front ends, covers
two frequency synthesizers, and finishes with a high efficiency CMOS cellular
power amplifier.
2:00 pm
Introduction
19.1
2:05 pm
A 3.5mW 900MHz Down-converter with Multiband Feedback
and Device Transconductance Reuse, J.
Han and R. Gharpurey, University of Texas Austin
A down-converter is presented wherein the IF-output of a mixer is applied
to its input transconductor to enhance gain without increasing bias current. A 900MHz
receiver with power dissipation of 3.5mW is demonstrated in a 0.13 µm CMOS process. The conversion gain is variable
from 10-50dB, the NF is 9.8dB at peak gain and the OIP3 is 8dBV-p. The receiver
has a third-order low-pass response at IF. The area requirement is 0.1mm2.
19.2
2:30 pm
A Highly Linear Broadband Variable Gain LNA for TV
Applications, D. Manstretta, Universita' degli Studi di Pavia, and
L. Dauphinee, Broadcom Corp.
A broadband variable-gain LNA with triple output for TV tuners has been demonstrated
in a 0.18 mm SiGe technology. The gain varies continuously from 27dB to -28dB
and has better than 1dB precision over a 1GHz bandwidth. At 27dB gain the
amplifier shows 6.5dB NF, 82dBmV OIP3 and 121dBmV OIP2. OIP3 is above 73dBmV
down to -21dB gain. With all three outputs enabled the circuit draws 170mA from
a 3.3V supply.
19.3
2:55 pm
A Current-Equalized Distributed Receiver Front-End for
UWB Direct Conversion Receivers, A.
Safarian, L. Zhou and P. Heydari, University of California Irvine
A power-efficient distributed direct-conversion RF front-end (DDC-RF)
circuit, using merged LNA/mixer cells, presented for UWB systems. A
current-equalization technique was implemented to remove systematic IQ
phase/gain mismatches. The DDC-RF prototype in 0.13CMOS with the use of
programmable input matching achieved average gain of 14.3dB and NF of 5.7dB
over the UWB. The IQ gain/phase imbalances are less than ±0.5dB/±2.5degree,
respectively. the current consumption is 8mA from 1.8V.
19.4
3:20 pm
A 65µW, 1.9 GHz RF to Digital Baseband Wakeup Receiver
for Wireless Sensor Nodes, N.
Pletcher, S. Gambini and J. Rabaey, University of California, Berkeley
A complete 1.9GHz receiver, with BAW resonator-referenced input matching network,
is designed as a wakeup receiver for wireless sensor networks. The 90nm CMOS chip includes RF amplifier,
PGA, ADC, and reference generation, while consuming 65uW from a single 0.5V
supply. The input RF bandwidth of the receiver
is 7MHz, while the maximum datarate is 100kbps.
When detecting a 31-bit sequence, the receiver exhibits -56dBm
sensitivity for 90% probability of detection.
3:45 pm – Break
19.5
4:00 pm
A 4GHz Low Complexity ADPLL-based Frequency
Synthesizer in 90nm CMOS, J.
Zhuang, Q. Du and T. Kwasniewski,
A 4GHz ADPLL-based integer-N frequency synthesizer is reported in this
paper. It employs a low-complexity digital phase and frequency detector as well
as a non-linear phase and frequency decision circuit to significantly reduce
the hardware complexity while maintain a comparable in-lock performance to
other high-complexity ADPLLs. The ADPLL was fabricated in 90nm CMOS technology
to prove its feasibility. Operating with an high-frequency-resolution DCO, the proposed
low-complexity ADPLL exhibits a programmable loop bandwidth from 100kHz to 6MHz
with and an excellent in-band phase noise performance.
19.6
4:25 pm
A 4.2 GHz PLL Frequency Synthesizer with an Adaptively
Tuned Coarse Loop, T.
Wu, Rambus Inc., P. Hanumolu, K. Mayaram and U.-K. Moon,
A 4.2 GHz integer-N PLL frequency synthesizer for WLANs is described. An
analog split tuned LC-VCO is controlled by coarse and fine loops to achieve
both a large frequency tuning range and a small VCO gain. An averaging varactor
is employed to reduce the amplitude sensitivity of the varactor, thereby
reducing the AM-to-FM noise conversion. A new adaptively tuned switched
capacitor integrator is used in the coarse loop for a fast lock time. The
prototype test chip in a 0.13- µm CMOS
process has a measured phase noise of -110dBc/Hz at 1 MHz offset, and a
settling time of 50 us.
19.7
4:50 pm
A 1.7-GHz
31dBm differential CMOS Class-E Power Amplifier with 58% PAE, R.
Brama, L. Larcher, A. Mazzanti, Universita di Modena e Reggio Emilia and F.
Svelto, Universita di Pavia
This paper shows that CMOS Class-E PAs are capable of high efficiency,
even when delivering large output powers at RF. A cascode device is used to
assure reliable operation. A differential solution has been adopted to maximize
2nd harmonic suppression and minimize potential on-chip
interference. Prototypes realized in 0.13 µm CMOS technology show 31dBm maximum output
power at 1.7GHz with 67% drain efficiency and 58% PAE, -51dBc and -39.5dBc
suppression for 2nd and 3rd harmonics, respectively.
Poster Session
Cascade Ballroom, Tuesday Afternoon, September 18
5:30 pm – 7:30 pm
(Authors are at the posters from 5:30 pm – 7:00 pm)
TP-01
A 2.4GHz Efficiency-Enhanced Rectifier for Wireless
Telemetry, K.-H.
Chen, J.-H. Lu and S.-I. Liu,
A 2.4GHz full-wave rectifier for wireless telemetry applications is
presented. A conventional full-wave rectifier using diode-connected MOS
transistors suffers from the power loss due to the intrinsic threshold voltage.
In this paper, a full-wave rectifier using a transformer is presented. It has
been fabricated in a 0.18 µm CMOS
process. When input power ranges from 6dBm~12dBm, this proposed rectifier
improves the efficiency of 2.5% compared with the conventional one.
TP-02
Comparative Studies of Common Control Schemes for ReferenceTtracking
and Application of End-point Prediction,
Y. Wu and P. K. T. Mok, Hong Kong University of
Science and Technology
This paper analyzes the reference tracking behavior of Buck converters
using several control schemes including voltage-mode, current-mode and
V2-control from both large-signal and small-signal domains.
TP-03
An Energy Management Circuit for Self-Powered
Ubiquitous Sensor Modules, J. Pan and Y. Inoue,
An energy management circuit is proposed for self-powered ubiquitous
sensor modules using vibration-based energy. With the proposed circuit, the
sensor modules work with low duty cycle operation. Moreover, a two-tank circuit
as a part of the energy management circuit is utilized to solve the problem that
the average power density of ambient energy always varies with time while the
power consumption of the sensor modules is constant and larger than it. In
addition, the long start-up time problem is also avoided with the timing
control of the proposed energy management circuit. The CMOS implementation and
silicon verification results of the proposed circuit are also presented. Its
validity is further confirmed with a vibration-based energy generation. The
sensor module is used to supervise the vibration of machines and transfer the
vibration signal discontinuously. A piezoelectric element acts as the
vibration-to-electricity converter to realize battery-free operation.
TP-04
An Ultra-Low-Power Power Management IC for Wireless
Sensor Nodes, M.
Seeman, S. Sanders and J. Rabaey,
A power interface IC is designed and demonstrated to convert and manage
power for a wireless tire pressure sensor node.
Power conversion is performed using on-chip switched-capacitor
converters with size-optimized devices and level-shifting gate drivers. A synchronous rectifier efficiently harvests energy
from an electromagnetic shaker and control circuitry regulates the output
voltage while minimizing power consumption. The converters achieve efficiencies
approaching 80%.
TP-05
A Low Standby Power Flip-flop with Reduced Circuit and
Control Complexity, L.
Clark, M. Kabir and J. Knudsen,
A flip-flop using thin and thick gate transistors combines high
performance and low standby power. The design has reduced circuit and
power-down control complexity compared to previous circuits using thick gate
shadow latches for low standby power state storage. Measured test chip results
on a foundry 130 nm process prove the viability of the design. Reduced shadow
latch supply voltage during standby is shown to be effective at mitigating the
drain to bulk leakage components.
TP-06
A 610-MHz FIR Filter Using Rotary Clock Technique, Z.
Yu and X. Liu, North Carolina State University
This paper presents a novel FIR filter design based on a resonant clocking
technique called rotary clock. It utilizes the spatially distributed multiple rotary
clock phases and achieves the full rotary clock power saving potential. Our
filter operates at 610 MHz, delivering a throughput of 39 Gbps. In comparison
with the conventional clock tree based design, it achieves a 34.6% clocking
power saving and a 12.8% overall circuit power reduction.
TP-07
A 186Mvertices/s 161mW Floating-Point Vertex Processor
for
In this paper, a power-efficient vertex processor with a geometry-specific
arithmetic unit, vertex caches, and a vertex texturing unit is presented for mobile
graphics environments. The proposed vertex processor achieves 186 Mvertices/s
of geometry performance which is 1.6 times faster than the previous results
among the IEEE754-compliant arithmetic units, and it supports OpenGL ES 2.0 and
Vertex Shader Model 3.0. The processor is implemented in a 0.18-µm 1P4M CMOS
process.
TP-08
A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter
with Level-Sensitive Latches, V.
Sathe, J. Kao and M. Papaefthymiou, University of Michigan
In this paper we present the design and experimental validation of RF1, a
0.8-1.2GHz frequency-scalable, resonant-clocked FIR filter test-chip with
level-sensitive latches. Designed using a fully automated ASIC flow, RF1 was
fabricated in a 130nm CMOS process with an on-chip inductor and clock
generator. At its resonant frequency of 1.03GHz, RF1 dissipates 132mW, with
clock power accounting for 10.8% of total power dissipation. Resonating 42pF of
clock load, RF1 achieves 76% clock-power efficiency over CV 2f.
TP-09
Addressing Parametric Impact of Systematic Pattern Variations
in Digital IC Design, P.-H.
Wang, B. Lee, G. Han, UMC, R. Rouse, P. Hurat and N. Verghese, Clear Shape
Technologies
A simulation methodology to predict changes in circuit characteristics due
to systematic lithography and etch effects is described. This methodology is
used to update an existing circuit netlist to produce accurate delay
calculation and is silicon validated using various transistor and ring
oscillator structures. In a digital IC design flow, the delay variation due to
lithography and etch is calculated and used to identify and repair timing
“hotspots” or parametric failures due to systematic variations.
TP-10
Design Considerations and Benefits of
Three-Dimensional Ternary Content Addressable Memory, E.
C. Oh and P.
Three dimensional (3D) ternary content addressable memory (TCAM) has been designed
in a 0.18 µm fully depleted silicon on insulator (FD SOI) 3D IC process. This
paper demonstrates that a 3D TCAM with three tiers can achieve 40% matchline
capacitance reduction and 21% power reduction compared to a TCAM in a
conventional single-tier process. This paper also discusses design considerations
of 3D TCAM including partitioning methods for multiple tiers and layout methods
of interconnects.
TP-11
A 37 ppm/°C Temperature Compensated CMOS ASIC with ±16
V Supply Protection for Capacitive Microaccelerometers,
H. Ko, S.-J. Paik, B. Choi, D.-I. Cho,
A high reliability CMOS-MEMS hybrid microaccelerometer system is
presented. To enhance the temperature response and to minimize die-to-die
variations, a low-noise continuous-time front-end architecture with
temperature-compensation and parasitic-cancellation is proposed. The
temperature coefficients of the output bias and the scale factor are measured
to be 37 ppm/°C and 27 ppm/°C, respectively. The bias instability level is
measured to be 42 µg. The integrated ±16 V supply protection gives the enhanced
system reliability and reduced form-factor.
TP-12
A 500 MHz Low Phase-Noise A1N-on-Silicon Reference
Oscillator, H.
M. Lavasani, R. Abdolvand and F. Ayazi, Georgia Institute of Technology
This paper presents a 496MHz refere