Session 12 – Nyquist A/D
Converters
Oak Ballroom, Tuesday Morning, September 18
Chair: George La Rue
Co-Chair : Yusuf Haque
The first four papers present pipelined A/D converters with resolution of
10 to 14 bits and conversion rates below 210 MS/s. These are followed by higher conversion rate
circuits up to 4 GS/s.
8:25 am
Introduction
12.1
8:30 am
A 14-b 30MS/s 0.75mm2 Pipelined ADC with
On-Chip Digital Self-Calibration,
H.-Y. Lee, T.-H.
Oh, H.-J. Park, J.-W. Kim, Samsung Electronics, H.-S. Lee, M. Spaeth,
Massachusetts Institute of Technology
A 14-b 30MS/s CMOS pipelined ADC is presented. To facilitate digital calibration, a simple
1-b per stage architecture with redundancy is used. The ADC fully integrates digital
self-calibration, which performs overall sequence by one flag signal. Implemented in a 90nm digital CMOS process,
the prototype ADC achieves 83.7dB SFDR and 69.3dB SNDR with calibration. Its active area is 0.75mm2
including the on-chip calibration logic and the total power consumes 106mW with
3.3V and 1.0V supply.
12.2
8:55 am
A 1.8V 10b 210MS/s CMOS Pipelined ADC Featuring 86dB
SFDR without Calibration,
J. Li, R.
Leboeuf, M. Courcy and G. Manganaro, National Semiconductor Corporation
A 1.8V 10b 210MS/s CMOS pipelined ADC in 0.18µm CMOS process is presented.
The low power consumption at high sampling rate is achieved by using an opamp-sharing
technique in 2.5b/stage pipelined ADC architecture. The opamp settling behavior
is well controlled through a regulated switch driving scheme. With a 20MHz input signal, the ADC achieves
85.9dB SFDR and 9.57ENOB at 210MS/s. Better than 76dB SFDR and 9.5ENOB
performance is maintained for input frequency up to 100MHz. The ADC consumes
140mW at 1.8V. The die area is about 1.5mm2.
12.3
9:20 am
Low-Power and High-Speed Pipelined ADC Using
Time-Aligned CDS Technique,
Y.-J. Kook, U.-K.
Moon,
Time-aligned Correlated Double Sampling (CDS) technique, which overcomes
the error accumulation problem found in the time-shifted CDS technique [4], is proposed.
This technique allows low gain opamp based switched-capacitor operation to
achieve the equivalent accuracy that is traditionally possible only in high
gain opamp based switched-capacitor operation. This allows simple single stage
opamps to be used, leading to low-power and high-speed performance. As a proof
of concept, a prototype pipelined analog-to-digital converter (ADC) is
fabricated in a 0.18um CMOS process. Measured results demonstrate 1.8V 10b
100MS/s 50mW ADC.
12.4
9:45 am
A 1V 10b 30MSPS Switched-RC Pipelined ADC, G.-C. Ahn, M.G.
Kim, P. Hanumolu and U.-K. Moon,
A 10b 30MS/s pipelined ADC using fully-differential switched-RC
multiplying digital-to-analog converter (MDAC) is presented. It utilizes a
resistive loop to reset the feedback capacitor in the MDAC without using the
floating switch. The measured
differential and integral nonlinearities of the prototype IC fabricated in a
0.13µm MOS process are less than 0.54 LSB and 1.75 LSB respectively. The
prototype ADC achieves 51.6dB SNDR and 65.9dB SFDR with 1V supply while
consuming 17mW power.
10:10 am - Break
12.5
10:25 am
A Time-Interleaved Track & Hold in 0.13µm CMOS
sub-sampling a 4 GHz Signal with 43dB SNDR, S. Louwsma, E.
van Tuijl, B. Nauta, University of Twente, and M. Vertregt, NXP Semiconductor
A 16-channel time-interleaved Track and Hold is presented. Three
techniques are introduced enabling a high bandwidth and linearity and good
timing alignment. Integrated ADCs are
used to evaluate the performance of the T/H. Single channel performance is 43
dB SNDR at an input frequency of 4 GHz. Multi-channel performance is 48 dB SNDR
at 1.35 GS/s with an ERBW of 1 GHz. The power consumption of the T/H including
clock-driver and buffers is 74 mW.
12.6
10:50 am
A 43mW Single-Channel 4GS/s 4-Bit Flash ADC in 0.18µm
CMOS, S.
Sheikhaei, S. Mirabbasi and A. Ivanov, University of British Columbia
A low-power small-area single-channel 4GS/s 4-bit flash ADC in 0.18µm CMOS
is presented. The entire ADC is implemented using CML blocks. To enhance the speed,
both analog (comparators) and digital (encoder) parts of the ADC are fully
pipelined. Furthermore, a reformulation for the encoder logic functions is
introduced to reduce the wiring delay in the layout. The ADC achieves a figure
of merit of 2.14pJ/conversion-step. The ADC area including the resistor ladder
is 0.06mm2 and the power consumption is 43mW when supplied with
1.8V.
12.7
11:15 am
A 57dB SFDR Digitally Calibrated 500MS/s Folding ADC
in 0.18µm Digital CMOS, I. Bogue and M.
Flynn,
A digitally calibrated 8-bit folding ADC incorporating redundancy and reassignment
is described. Small, redundant folder and comparator circuits generate 1024
available zero-crossings. An entirely self-contained calibration engine selects
255 zero-crossings from the available set. Unselected circuits are powered
down. The calibration breaks the link between ADC performance and analog
accuracy, allowing small transistors to be used in the signal path. Fabricated in 0.18µm digital CMOS, the DNL of the uncalibrated ADC
is 6.7LSB and 0.8LSB, before and after calibration, respectively. SFDR remains above
55dB up to a sampling rate of 550MS/s. The total die area is 1.2mm2.
12.8
11:40 am
A Sample-Time Error Compensation Technique for
Time-Interleaved ADC Systems, A. Haftbaradaran and K. W. Martin,
Sample-time error among different channels of a time-interleaved Analog-to-Digital
Converter (ADC) is a factor in significant degradation of the ADC performance, especially
in high frequencies. A two-channel, time-interleaved ADC structure with a
background sample-time error compensation technique has been implemented. The
sample-time error detection technique uses random data and has been implemented
in the digital domain at a low level of complexity. The error correction is
performed by adjusting the delay of the clock path of one channel, using a
6-bit Digitally-Controlled Delay Element (DCDE). At a sampling rate of 400
MSamples/s, the experimental results show that the Spurious-Free Dynamic Range
(SFDR) of the ADC system is improved to 58.8 dB at 190 MHz. The ADC system
achieves a Signal-to-Noise-and-Distortion Ratio (SNDR) of 59.6 dB at 5 MHz and
55.2 dB at 190 MHz after compensation. This
error compensation method is especially suitable for time-interleaved ADCs used
in digital data communication systems.
Session 13 – Clocking and CDRs
Fir Ballroom, Tuesday Morning, September 18
Chair :
Co-Chair:
This session explores modern clocking techniques with an emphasis on
digital enhancement along with new CDR implementations.
8:25 am
Introduction
13.1
8:30 am
Low-Jitter and Large-EMI-Reduction Spread-Spectrum Clock
Generator with Auto-Calibration for Serial-ATA Application,
T. Kawamoto, Hitachi Ltd., T. Takahashi, H. Inada and
T. Noto, Renesas Technology
A low jitter VCO with high-frequency-limiter and an auto-calibration
technique was developed for a spread-spectrum clock generator (SSCG) by using a
0.13-µm CMOS process for Serial-ATA applications. The limiter prevents the SSCG
from going into an unlocked state, and the auto-calibration technique optimizes
the performance by controlling VCO gain and maximum output frequency.
Rms-jitter variation at 1.5 GHz is improved from 2.1-7.8 ps to 1.9-3.3 ps and
the EMI reduction of 10.0 dB is achieved.
13.2
8:55 am
Wide Lock-Range, Low Phase-Noise PLL using
Interpolative Ring-VCO with Coarse Frequency Tuning and Frequency Linearization, H.
Kodama, H. Okada, H. Ishikawa and A. Tanaka, NEC Corporation
To relax the trade-off relationship between tuning range and phase noise,
we have developed a new interpolative ring-VCO having a wide control voltage
range over which frequency variation is linear.
A wide lock-range, low phase noise PLL incorporating this VCO has been
fabricated in a 90 nm CMOS process. It successfully
offers between 3.432–4.488 and 6.600–9.240 GHz, as well as low integrated phase
noise, less than 4 degrees.
13.3
9:20 am
A 3.2Gb/s Oversampling CDR with Improved Jitter
Tolerance, M. Brownlee, P. Hanumolu and U.-K. Moon,
A 3.2Gbps CDR circuit employs an oversampling architecture to decouple the
tradeoff between jitter generation and jitter tolerance. The test chip fabricated
in a 0.13µm CMOS process achieves a 30x increase in the jitter tolerance corner
without increasing recovered clock jitter. Power consumption is 19.5mW from a
1.4V supply at 3.2Gbps and die area is 0.081mm2.
13.4
9:45 am
A 2.5Gb/s Burst-Mode CDR based on a 1/8th Rate Dual
Pulse Ring Oscillator, S. Gierkink, Conexant
A 2.5Gb/s burst-mode CDR uses a 1/8th rate ring oscillator with two phase independent
pulses running simultaneously. One pulse sets the ring delay by phase locking
it to a reference, the other tracks the data. Phase acquisition is
instantaneous. CID tolerance is > 72 bits. The 0.6mm2 0.13µm CMOS
chip includes a CML input buffer, PLL, PRBS checker and 1:8 demux. It has
2.7UIpp jitter tolerance at 100kHz and consumes 42mW from a 1.2V supply.
10:10 am - Break
13.5
10:25 am
Digitally-Enhanced Phase-Locking Circuits (INVITED
PAPER), P. Hanumolu, U.-K. Moon and K. Mayaram,
In this paper, we present an overview of digital techniques that can
overcome the drawbacks of analog phase-looked loops (PLLs) implemented in
deep-submicron CMOS processes. The design of key building blocks of digital
PLLs such as the time-to-digital converter and digital-to-frequency converters
are discussed in detail. The implementation and measured results of two digital
PLL architectures, (1) based on a digitally controlled oscillator and (2) based
on a digital phase accumulator, are presented. The experimental results
demonstrate the feasibility of using digital PLLs in digital systems requiring
high-performance PLLs.
13.6
11:15 am
A Low-Jitter Open-Loop All-Digital Clock Generator
with 2 Cycle Lock-Time, M.-Y. Kim, D. Shin, H. Chae, S. Ok and C. Kim,
A portable multiphase clock generator, independent of input duty ratio,
has been developed. The proposed open-loop and full-digital architecture has a
fast lock time of two clock cycles and is a simple, robust and portable IP. In addition, the complementary delay line is
implemented to achieve high phase resolution at a wide frequency range. The
generator has been implemented in a 0.18um CMOS process and operates at
variable input frequencies ranging from 800MHz to 1.6GHz.
13.7
11:40 am
An All-Digital 90-Degree Phase-Shift DLL with
Loop-Embedded DCC for 1.6Gbps DDR Interface, J.-H. Bae, J.-Y.
Sim, H.-J. Park, POSTECH and J.-H. Seo, H.-S. Yeo, J.-W. Kim,Samsung
Electronics
An all-digital 90º phase-shift DLL is proposed for 1.6Gbps DDR interface
by using a loop-embedded DCC and a binary phase detector with the lock range extended
to 0~4π radians. The DCC has a small delay and the fixed rising-edge
property for loop-embedding. The chip fabricated with a 0.13µm CMOS process
gives the DLL data rate of 667Mbps~1.6Gbps and the output duty cycle of 47.8%~49%
for the input duty cycle of 23%~76%, at 1.6Gbps and 1.2V.
Session 14 – Power Management Techniques
Pine Ballroom, Tuesday Morning, September 18
Chair:
Co-Chair:
This session addresses issues in power management, including ac-dc and
dc-dc converters, regulators, controllers, timers, and low-power drivers.
8:25 am
Introduction
14.1
8:30 am
A Low Noise Buck Converter with a Fully Integrated
Continuous Time Sigma Delta Modulated Feedback Controller, M.
Wong, Freescale Semiconductors, B. Bakkaloglu and S. Kiaei, ASU
A low noise synchronous buck converter with a fully integrated second
order single-bit continuous time sigma delta modulator (CT-sigma delta M) based
controller is presented. The converter is designed and fabricated on a 0.18 µm SiGe process. The feedback CT-sigma deltaM is
sampled at 10MHz with a single-bit non-return-to-zero (NRZ) output. Compared to a traditional PWM controller, the
CT-sigma delta M controlled converter shapes the out-of-band noise and
suppresses the in-band noise at the switching node by 25dB with 92% efficiency.
14.2
8:55 am
A Compact Pulse-Based Charge Pump in 0.13um CMOS, J.
Holleman, B. Otis and C. Diorio, University of Washington
In this paper, we present a new class of charge pump capable of generating
voltages 3.75 times greater than the supply in a single clock cycle. It occupies .005 mm2 in a 0.13um CMOS process
and can operate with a supply voltage between 0.4V and 1.2V, or as low as 0.2V
with some pulse-shape distortion. Our
charge pump can provide output voltages of up to 3.9V with less than 10nW of
standby power dissipation.
14.3
9:20 am
An Efficiency-Enhanced Integrated CMOS Rectifier with
Comparator-Controlled Switches for Transcutaneous Powered Implants, S.
Guo and H. Lee, University of Texas
This paper presents a high-efficient rectifier for high-current
transcutaneous power transmission in biomedical implants. By using comparators to control power nMOS
transistors functioning as switches with unidirectional current flow, the
rectifier dropout voltage is decreased to improve the power efficiency. The unbalanced biasing scheme in the
comparator also minimizes the reverse leakage current. Implemented in a standard 0.35µm CMOS, the
rectifier operates at 1.5MHz, achieves the peak conversion ratio of 95% and can
deliver up to 20mA output current.
14.4
9:45 am
Integrated Regulation for Energy-Efficient Digital
Circuits, E. Alon,
Linear regulation can reduce the effective supply impedance of digital
circuits without increasing their total power dissipation. This can be achieved with a push-pull
regulator topology that uses a second, higher-than-nominal supply, comparator-based
feedback, and a switched-source follower output stage. Measured results from a 65nm SOI test-chip
verify that by using these techniques, regulation reduces supply noise by ~30%
while also enabling a slight decrease (~1.4%) in total power.
10:10 am – Break
14.5
10:25 am
An EEPROM Programming Controller for Passive UHF RFID
Transponders with Gated Clock Regulation Loop and Current Surge Control,
R. Barnett, Texas Instruments, and J. Liu, University
of Texas Dallas
This paper describes an EEPROM programming controller for a RFID IC. A
gated clock regulation loop is proposed to regulate the programming voltage
over a wide range of RF input power. A current surge limiting architecture
prevents a collapse of the rectified supply during startup of the charge pump
and a switched bandgap reference is proposed for reducing power and area. The
0.35µm CMOS IC provides 14V from a 2V rectified supply and consumes 7µW.
14.6
10:50 am
A Sub-pW Timer Using Gate Leakage for Ultra Low-Power
Sub-Hz Monitoring Systems,
Y.-S. Lin, D.
Sylvester and D. Blaauw,
In this work, we presented a novel ultra low power timer designed using
the gate leakage of MOS capacitors. The test chip was fabricated with 0.13µm
CMOS technology with area of 480µm2. Measurement results show that
the circuit functions correctly at a wide range of supply voltage from 300mV to
1.2V. The temperature sensitivity is 0.16%/°C at 600mV and 0.6%/°C at 300mV.
The power dissipation is less than 1pW running at 20C and 300mV.
14.7
11:15 am
CMOS-Based MEMS Mirror Driver for Maskless Lithography
Systems, J.
Lee, J. Weiner, Y. Baeyens, V. Aksyuk, Y.-K. Chen, Alcatel-Lucent, H.-H. Chen,
Mediatek
This paper presents a low-power MEMS mirror driver for maskless
lithography systems. The CMOS driver consists of a 512x128 analog memory cell
array to drive the position of 512x128 MEMS mirror array. The row driver
employs an analog de-multiplexing architecture, which eliminates the need for
precise matching among multiple row driver characteristics. It uses two
parallel high-speed 8-b DACs with 128 sample-and-hold amplifiers (SHAs) to
write a multilevel data into memory cells. The driver chip is implemented in a 0.35
µm digital CMOS process. It consumes a
120mA power with 3/3.6 V supplies.
Session 15 – CMOS Scaling and Technology
Implications
Cedar Ballroom, Tuesday Morning, September 18
Chair: David
Sunderland
Co-Chair:
This session of invited papers addresses important issues related to
maintaining
8:25 am
Introduction
15.1
8:30 am
Reliability Trends with Advanced CMOS Scaling and the
Implications for Design (INVITED PAPER), J.
Scaling has pushed existing CMOS materials much closer to their intrinsic reliability
limits. With the expected introduction
of new materials (metal gate electrodes, high-k gate dielectrics, strained
silicon, and ultra-low interconnect dielectrics) legacy-based design rules
should be challenged as to their validity when designing with these new
materials. This work will focus on several key reliability issues: TDDB, NBTI,
HCI, Electromigration, and Stress Migration as we continue to scale with the
new materials.
15.2
9:20 am
Evolution of CMOS Technology at 32 nm and Beyond
(INVITED PAPER), G. Shahidi, IBM
Over the last 15 years, there has been a new CMOS technology node
approximately every two years. The key feature of every node has been 2X
density shrink and ~35% performance gain per technology node. Chip power has been increasing rapidly,
approaching air cool limit. Power limit
is transforming CMOS scaling to more of a density driver. As we move to 32 nm node and beyond a number
of additional fundamental challenges are faced, which may force additional rethinking
of how scaling has been done. This paper is an overview of some upcoming
challenges and possible ways of addressing them.
15.3
9:45 am
High-K/Metal Gate Technology: A New Horizon (INVITED
PAPER), M. Khare, IBM
High-K/Metal Gate technology represents a fundamental change in transistor
structure that restarts gate length scaling, enables performance improvement and
offers chip power reduction. The gate stack presented is compatible with conventional
high temperature CMOS processing and existing performance enhancement elements.
A new knob in the form of metal gate work function promises separate and better
optimization for High Performance and Low Power applications. This technology
introduces a unique PBTI reliability mechanism for N-FET that is now well understood
and modeled.
10:10 am - Break
15.4
10:25 am
Revolutionary NanoSilicon Ancillary Technologies for
Ultimate-Performance Gigascale Systems (INVITED PAPER), M. Bakir, B. Dang
and J. Meindl, Georgia Institute of Technology
This paper describes electrical, optical, and fluidic (or ‘trimodal’) chip
I/O interconnect networks for gigascale systems to meet and exceed
end-of-roadmap projections in the areas of power delivery, off-chip bandwidth,
and heat removal, respectively. The trimodal I/O technology is proposed to
overcome the adverse effects of conventional silicon ancillary technologies on
the performance of a gigascale system. We describe trimodal I/O interconnect configurations,
fabrication, assembly, and testing.
15.5
11:15 am
Reverse Engineering in the Semiconductor Industry
(INVITED PAPER), R. Torrance and D. James, Chipworks, Inc.
This paper covers the place of reverse engineering in the semiconductor industry,
and the techniques used to obtain information from semiconductor products. The paper covers product teardowns;
system-level analysis, both hardware and software; circuit extraction, from the
transistor level up; and process analysis, looking at how a chip is made, and
what it is made of. Examples are also
given of each type of reverse engineering.