Chairperson:
Laurence Nagel, Omega Enterprises
Educational Session 1 –
Mixed-Signal SOC Design
Methodology
Oak
Ballroom, Sunday, September 16
Organizer:
Laurence Nagel, Omega Enterprises
Co-Organizer: Henry Chang,
Designer’s Guide Consulting
8:00 –
9:50
E1-1 Top-down Design
Methodology
Scott
Shelton, Cadence Analog Design Services
Mixed-signal
design at the SOC level necessitates a top-down mixed signal design methodology
to meet today's project schedules with successful end products. This technical discussion examines
methods for successfully handling the analog and digital domain interactions in
large complex ICs with today's tools; crafting and executing a simulation
strategy which efficiently verifies functionality and performance; and
efficiently modeling at appropriate levels of abstraction. The discussion is
presented within the context of actual designs by some of Cadence's internal
design teams, and examines how they have shaped and melded the methodologies as
presented. Given the diverse skill sets and multiple IP vendors garnered for
SOCs, the structure and management of these design teams throughout the various
project stages is explored as well. The session covers these topics through the
complete design cycle, from project kickoff to IP block delivery for integration
or SOC tapeout.
10:10 –
12:00
E1-2 High-Performance
Energy-Efficient Digital Design Technologies for Nanoscale
SOC
This
presentation examines some of the prominent barriers to high-performance and
energy-efficient digital design in the sub-65nm CMOS regime and outlines new
paradigm shifts necessary for next-generation SOC digital design and
methodologies. Emerging trends in SOC industry including special-purpose
multimedia/communication accelerators, networks-on-chip, co-processor arrays,
and reconfigurable DSP and their associated power-performance trade-offs are
reviewed. Energy-efficient data-path and interconnect circuit techniques,
variation-tolerant design methods, static/dynamic supply scaling,
ultra-low-voltage circuits, and multi-supply/multi-threshold design and supply
gating methodologies for switching and leakage energy reduction are described.
Special purpose hardware accelerators and SOC building blocks for enabling high
performance-per-Watt on specialized DSP tasks such as encryption and media
processing are presented. Many chip design examples and their results will be
discussed as part of this presentation.
1:00 –
2:50
E1-3 Top-down Design of RF
Transceivers using VHDL
Khurram
Waheed, Texas Instruments
RF transceivers comprise a
particularly difficult challenge in SOC design because their proper operation
requires correct interoperability of RF subsystems, analog subsystems, and
digital subsystems. This
presentation describes the numerous challenges in the top-down design of a RF
transceiver SOC and describes how VHDL simulation is in the design flow. Case studies of RF transceiver chips
designed at Texas Instruments are used to illustrate how the design challenges
were overcome to produce working SOCs.
3:10 –
5:00
E1-4 Analog
Verification
Ken
Kundert, Designer’s Guide Consulting
Verification is becoming recognized
as one of the most important issues when designing large analog circuits, and as
a result design methodologies are starting to change. This change mirrors a
change that occurred in digital design 10-15 years ago. In this presentation I
will show why the problem has become so significant, and what people are doing
to control the problem.
Educational Session 2
High-Speed Serial I/O Design
Techniques
Fir
Ballroom, Sunday, September 16
Organizer:
Co-Organizer: Gordon Roberts,
8:00 –
9:30
E2-1 Introduction to High-speed
I/O
Randy
Mooney, Intel
I'll
discuss the constraints of the design space for microprocessor platforms, then
take a look at the state of the technologies required to deliver bandwidth in
these platforms. These technologies include analysis tools, interconnect
components, modulation and equalization choices that fit the constraints, and
the various circuits required in silicon. I'll then take a look at future
platform requirements, and the potential solution space to meet those
needs.
9:30 –
11:00
E2-2 Introduction to Signal
Integrity
Bob
Sainati, 3M
The
demand for ever increasing data rates in today’s electronic systems requires the
use of shorter rise time signals and faster clock speeds. Both data and clock
signals are conveyed using interconnects to carry signals on-chip, on a
multilayer pc board, through backplanes or via cables. This tutorial focuses on
the impact of interconnects on high speed digital signals. Here the term
interconnect refers not only signal traces but packaging, connectors, vias, etc.
Shorter rise times, of course, imply wider frequency bandwidths. Many
traditional interconnect design techniques focus on factors such as routing
efficiency, mechanical and thermal issues. Because of this, many interconnect
schemes lack the bandwidth necessary to distribute high speed signals
faithfully. Likewise faster rise times increase the probability of significant
crosstalk between multiple nets. Similar issues exist with power distribution
networks. Short rise time signals can require the supplying of large amounts of
current within a very short time. Improper design of power distribution networks
can create distortion producing supply voltage drops. Finally, the higher
frequencies of short rise time signals are much more easily radiated thus
resulting in potential EMI/EMC problems.
Techniques
such as the use of microwave measurement techniques (e.g., network analyzers),
transmission line theory, microwave scattering parameter analysis and
electromagnetic simulators have been adopted in order to design improved
interconnects and power distribution networks. These techniques all have at
least some basis in electromagnetic theory, that is, Maxwell’s equations.
Although it is common to think of digital signals in terms of voltages and
currents, ultimately they are a set of (coupled) electric and magnetic fields
surrounding the metallization of signal traces, connector and package pins, via
metallization, etc. Many of the issues associated with signal integrity are a
result of the finite velocity of the fields when guided by traces, the
propensity of fields to locally store energy in regions where abrupt changes in
geometry, direction, etc. are encountered and the fact that crosstalk and
radiation increase because a fixed physical size becomes electrically larger as
the wavelength decreases. The intent of this course is to link the physics of
electromagnetic fields to the signal behavior observed on an interconnect. For
instance, quantities such as inductance and capacitance are fundamentally
described in terms of fields. Also guided electromagnetic waves are the
foundation of transmission line theory and scattering parameters. This course
will not be a detailed exposition of electromagnetic theory but rather a review
of concepts and an application of them to high speed digital signal interconnect
behavior.
11:00 –
12:00 and 1:00 – 2:00
E2-3 Jitter
Analysis
In this
tutorial presentation, we will first review where the technology is heading to
for the multiple Gbps high-speed links and I/O buses for devices and systems in
networks and computers. Second, we will discuss why jitter and signal integrity
have become the major challenges, as well as limiting factors for developing
those high-speed, high performance, and more increasingly, high volume link
devices and systems. Third, we will discuss the jitter and signal integrity
modeling, simulation, verification and characterization methodologies for jitter
and signal integrity within the context of a serial link. We will cover these
ever evolving cutting edge topics from generic perspective, as well as practical
application perspective, with real-world examples from multiple Gbps link
technologies of PCI Express, FB DIMM, and Serial ATA in computer I/Os, and Fibre
Channel and Gigabit Ethernet in networks.
2:00 –
3:30
E2-4 Circuit/System Aspects of I/O
Equalization
Vladimir
Stojanovic, Massachusetts Institute of
Technology
Today’s
high-speed interfaces are limited by the bandwidth of the communication channel,
tight power constraints and noise sources that differ from those in standard
communication systems. The wire bandwidth limitations make straight circuit
solutions inefficient, and the power and area constraints make standard digital
communication approaches infeasible. Efficient solutions require bridging the
fields of digital communications, optimization, statistical and dynamic system
modeling, with system architecture, mixed-signal and digital circuit
design.
This
tutorial covers the circuit and system design of equalized high-speed I/Os. We
start by introducing the basics of channel properties, modeling, measurements,
and communications techniques. We then focus on different link equalization
techniques, comparing them both from system perspective and from the performance
of resulting circuit implementations. Some examples will cover trade-offs
between transmit pre-emphasis and decision-feedback equalization, linear analog
receiver equalization as well as joint modulation/equalization and
equalization/coding techniques (like PAM4, duobinary and multitone signaling).
Implementations of transmitter FIR equalizers, several DFE receiver topologies
and peaking amplifiers will be discussed in detail. Several adaptive techniques
for equalizer tuning and link monitoring will also be
presented.
3:30 –
5:00
E2-5 Clocking and
CDRs
High-purity
clock generation enables longer reach in wired communication systems. Optical
and copper standards set an upper bound on the noise and distortion that can be
added to the signal at the source. This tutorial describes means of efficient
clock generation and distribution in high-performance chips to satisfy
requirements imposed by the standards. Clock and data recovery (CDR) circuits
are an integral part of wired communication systems. With the accelerated rate
of device scaling in recent decades, CDR architectures have transitioned from
fully analog into mixed-mode and digital implementations. The tutorial later
addresses the evolution of CDR architectures, as well as the design of its
building blocks.
Educational Session 3
Low Power Embedded ADC
Design
Pine
Ballroom, Sunday, September 16
Organizer:
Sang-Soo Lee, Pixelplus
Co-Organizer:
8:00 –
9:50
E3-1 System
Aspects
Thomas
Cho, Marvell
Aggressive
CMOS scaling in the last couple of decades has enabled powerful DSP engines for
many digital communication systems in both wireless and wired-line applications.
But the world is still analog, and the requirements for the analog-to-digital
interface circuits are becoming increasingly stringent not to limit the overall
system performance. In addition, A/D converters, which used to be discrete
components on the board in the past, are now being integrated onto an IC
together with many other functions for smaller form factors, bringing new
challenges to analog circuit designers. This tutorial will give an overview of
both circuit and system level requirements for the embedded A/D converters used
in various wireless/wired-line applications. Practical considerations for
system-on-chip environments, such as on-chip reference generation, noise
isolation, low-power/low-voltage designs, testing, and other challenges will
also be discussed.
10:10 –
12:00
E3-2 Pipeline ADC
Design
Boris
Murmann,
Pipelined
analog-to-digital converters have evolved as a popular architecture for
broadband quantization in applications requiring 8-14 bit resolution and
sampling rates up to several hundred MS/s. This lecture discusses the design and
implementation of pipelined ADCs using a top-down approach, ranging from an
architecture level analysis to transistor level implementation details. Specific
topics include: (1) Basic operation principle, (2) Redundancy and digital
calibration techniques, (3) Error and noise budgeting; pipeline stage scaling
and choice of per-stage resolution, (4) Transistor level circuit implementation;
low power techniques such as OTA sharing and SHA-less front-ends, and (5)
Performance survey; recent trends and developments in
research.
1:00 –
2:50
E3-3 Sigma Delta
ADC
Katelijn
Vleugels, H-Stream Wireless
In this
talk, we will look at the various aspects of Sigma-Delta Analog-to-Digital
Converter (ADC) design. We begin with a review of the basic concepts of
Sigma-Delta data converters, followed by an overview of state-of-the art
Sigma-Delta ADC implementations. Several architectures exist, and the optimal
architecture heavily depends on the system requirements imposed by the
application. The advantages and challenges of various architectures are
discussed next. We then look at the impact of circuit implementation
non-idealities on the overall ADC performance. The talk will conclude with an example
of a Sigma-Delta ADC design.
3:10 –
5:00
E3-4 Case
Study
Stacy
Ho, Analog Devices
This talk will present case studies
on embedded ADC design for mobile handsets. Factors that influence the selection of
ADC architecture, such as power dissipation, wireless standards requirements,
and cost, will be discussed. Issues
due to the system level integration of ADCs will be addressed, such as:
coexistence with digital baseband and power management blocks, architectural
tradeoffs, reference and clock requirements. The talk will also review published
embedded ADCs for wireless applications.
Technical
Sessions
Monday, September 17 – Wednesday, September
19
Session 1 – Keynote
Presentation
Oak Ballroom, Monday Morning,
September 17
8:15 am
Welcome and Opening Remarks
Awards
Presentations
Keynote Speaker
Introduction
8:30 am
Keynote Presentation
“The Wireless Revolution
Continues:
Can Technology Keep Up with the
Challenge?”
Dr. Bill Krenik, Chief Technical Officer for
The
exploding market for consumer electronics is creating diverse product
opportunities, with many products demanding unique technology features to enable
successful performance, power-efficiency, size and cost. The wireless market is
a high-growth market, and a critical driver of technology innovations. Whether
creating a cutting-edge mobile phone with the hottest features or a modest
handset required for high-growth emerging economies, a mobile designer is
increasingly more challenged to satisfy product goals with existing technology.
From the perspective of the industry-leading semiconductor provider entrenched
in the wireless space, Bill Krenik, Chief Technical Officer for TI’s Wireless
Terminals Business Unit, will address the critical technology, process and
packaging challenges and solutions required to meet mobile market requirements
for today and tomorrow.
Session 2 –3D and SiP
Oak Ballroom, Monday Morning,
September 17
Chair: Rakesh
Patel
Co-Chair : Ann
Rincon
Two invited
papers on 3D wireless high performance interchip communications using capacitive
and inductive interconnect techniques are presented. In addition, resonant clocking in CMOS
is explored for active jitter deskewing.
10:00
am
Introduction
2.1
10:05
am
3D Capacitive
Interconnections for High Speed Interchip Communication (INVITED
PAPER), R.
Canegallo, L. Ciccarelli, P.L. Rolandi, STMicroelectonics, A. Fazzi, L. Magagni, F. Natali, R. Guerrieri
University of Bologna, E. Jung, IZM Fraunhofer, L. Di Cioccio,
CEA-LETI
A 3D
Interconnection scheme based on capacitive coupling for high speed chip to chip
communication has been implemented in a 0.13 µm CMOS process. This work shows, with a
synchronous approach data transmission at 900MHz with electrodes 15x15 µm2 and
energy consumption of 41fJ/bit. With asynchronous approach we demonstrate with
electrodes 8x8 µm2 a propagation of clock at 1.7GHz and a propagation delay of
420ps for general purpose signal with energy consumption of
80fJ/bit.
2.2
10:55
am
Low-Jitter Active
Deskewing Through Injection-Locked Resonant Clocking, Z. Xu
and K. Shepard,
Active deskewing
is an important technique for managing variability in clock distributions but
introduces latency and power-supply-noise sensitivity to the resulting networks.
In this paper, we demonstrate how active deskewing can be achieved with resonant
distributions without introducing significant jitter. The prototype network
operates at a nominal 2-GHz frequency in a 0.18µm CMOS technology with more than
25 pF/mm2 of clock loading.
2.3
11:20
am
Wideband
Inductive-coupling Interface for High-performance Portable System (INVITED
PAPER), H.
Ishikuro, N. Miura and T. Kuroda,
This paper
presents a wideband, low power, and low cost pulse-based inductive-coupling
interface for wireless data transfer in high performance portable devices. General aspects of wireless links are
discussed to understand the position of inductive-coupling technique. Two applications of the
inductive-coupling links are introduced One is a 0.14pJ/b inter-chip link
for System-in-a-Package. The other
is a detachable wireless interface for chip monitoring through LSI package.
Circuit design techniques for power
reduction and an extension of communication range are presented.
Session 3 – Extreme
SRAMs
Fir
Ballroom, Monday Morning, September 17
Chair: Takashi Akioka
Co-Chair:
These papers
explore state-of-the-art SRAMs as well as new structures and analysis techniques
to enable SRAM scaling into future technology generations.
10:00
am
Introduction
3.1
10:05
am
A 550ps
Access-Time Compilable SRAM in 65nm CMOS Technology, L.
Wissel, H. Pilo, C. LeBlanc, X. Wang, S. Lamphier and M. Fragano,
IBM
A
fixed-configuration custom SRAM macro with a highly-scalable architecture was
used as the basis for an ASIC SRAM compiler. The 256Kb fixed-configuration uses
dynamic circuitry [1] and other design techniques, and has been demonstrated in
silicon to have an access time of 550ps. The compilable SRAM extends the column
mux options, and can be compiled from 2Kb to 1.1Mb. Novel circuitry is used for
efficient redundancy implementation in both the row and column
dimensions.
3.2
10:30
am
A Disturb
Decoupled Column Select 8T SRAM Cell, V.
Ramadurai, R. Joshi and R. Kanj, IBM
This paper
presents a novel 8T SRAM cell that provides a way to eliminate the column select
read disturb scenario. The 8T cell is then used in conjunction with a sense-amp
based architecure that minimizes read disturb to selected cells. Fabricated hardware resuls and
simulation of this architecture show improvements of cell Vddmin over
traditional 6T cells by more than 150mV for 90nm PD/SOI technology.
3.3
10:55
am
Canary Replica
Feedback for Near-DRV Standby VDD Scaling in a 90nm
SRAM, J. Wang
and B. Calhoun, University of Virginia
Canary bitcells
act as monitors in a feedback architecture to sense the proximity to the Data
Retention Voltage (DRV) for SRAM bitcells during standby voltage scaling. This
approach implements aggressive standby VDD scaling by tracking PVT variations
and gives the flexibility to tradeoff between reliability and leakage power
savings. A 90nm SRAM test chip confirms the function of this closed-loop
approach. Power savings improve by up to 30x compared with the conventional
guard-banding approach.
3.4
11:20
am
Flex-Pass-Gate
SRAM Design for Static Noise Margin Enhancement Using FinFET-Based
Technology, S.
O'uchi, M. Masahara, K. Sakamoto, K. Endo, Y.X. Liu, T. Matsukawa, T. Sekigawa,
H. Koike and E. Suzuki, National Insititute of
AIST
We propose a
flex-pass-gate SRAM (Flex-PG SRAM), i.e., a FinFET-based SRAM to enhance both
the read and write static noise margins (SNMs) independently. The flip-flop in
the Flex-PG SRAM consists of usual FinFETs while its pass gates consist of
double-“independent”-gate FinFETs, four-terminal-FinFETs. A TCAD simulation
revealed that the Flex-PG SRAM increases the read SNM by 70 mV even when its
6-sigma tolerance is ensured, without the cell size penalty and decrease in the
write SNM.
3.5
11:45
am
Simple
Statistical Analysis Techniques to Determine Minimum Sense Amp Set
Times, R.
Houle, IBM
Simple
statistical analysis techniques are described, involving a relatively small
number of actual circuit simulations, to accurately determine the minimum
required sense amp set time for memory designs. Techniques to generate and
evaluate the statistical distributions for signal development, leakage and sense
amp asymmetry are discussed with important implications to sense amp
design.
Session 4 – Compact Models for
Advanced
CMOS
Technologies
Pine
Ballroom, Monday Morning, September 17
Chair: Brian Chen
Co-Chair
:
Two invited
papers present next-generation compact models of advanced SOI and multiple gate
MOSFETs, followed by a regular paper on characterization and modeling of 65nm
copper interconnect resistance.
10:00
am
Introduction
4.1
10:05
am
PSP-SOI: A
Surface Potential Based Compact Model of Partially Depleted SOI MOSFETs (INVITED
PAPER), W. Wu,
X. Li, G. Gildenblat, Arizona State University, G. Workman, S. Veeraraghavan, C.
McAndrew, Freescale Semiconductor, R. van Langevelde, Philips, G. Smit, D.
Klaassen, A. Scholten NXP Semiconductors and J. Watts,
IBM
This paper
reports recent progress on partially depleted (PD) SOI modeling using a surface
potential based approach. The new model, called PSP-SOI, is formulated within
the framework of the latest industry standard bulk MOSFET model PSP. In addition
to its physics-based formulation and scalability inherited from PSP, PSP-SOI
captures SOI specific effects by including a floating body simulation
capability, a parasitic bipolar model, and self-heating. A nonlinear body
resistance is included for modeling body-contacted SOI devices. The PSP-SOI
model has been extensively tested on several PD/SOI technologies.
4.2
10:55
am
Charge-Based
Compact Modeling of Multiple-Gate MOSFET (INVITED PAPER), B.
Iniguez, A. Lazaro, H. Abd El Hamid, O. Moldovan, B. Nae, URV, J. Roig, LAAS and
D. Jimenez, UAB
We present new
compact modeling techniques which have been applied for different types of
multiple-gate MOSFETs. Long channel models are obtained by deriving a unified
charge control model from the solution the 1-D Poisson’s equation. Scalable
models for the short-channel effects have been developed by solving the 2-D or
3-D Poisson’s equation. We observed a very good agreement with numerical
simulations of the characteristics of different multiple-gate devices. We also
extended our compact models to the high frequency operation.
4.3
11:45
am
Characterization,
Modeling and Extraction of Cu Wire Resistance for 65 nm
Technology, N. Lu,
M. Angyal, G. Matusiewicz, V. McGahay and T. Standaert,
IBM
We present an
innovative and comprehensive approach to characterize and model interconnect
resistance. We measured and analyzed Cu wire resistance data for multiple wire
widths on 10 BEOL levels at multiple temperatures and, with SEM cross-section
data, extracted all model parameters in IBM 65nm technology. The extracted SPICE
wire resistance model includes the congregated effects of surface scattering,
grain boundary scattering and surface roughness. New behavior of wire resistance
is reported for the first time.
Session 5 – Oversampling A/D
Converters
Cedar
Ballroom, Monday Morning, September 17
Chair:
Co-Chair: Un-Ku Moon
This session
highlights recent advances in oversampling ADCs including dynamic range
improvements for both bandpass and lowpass modulators and improved tolerance for
analog imperfections.
10:00
am
Introduction
5.1
10:05
am
A 63-mA 112/94-dB
DR IF Bandpass Delta-Sigma Modulator with Direct Feed-forward and Double
Sampling, T.
Yamamoto, M. Kasahara and T. Matsuura, Renesas Technology
Corp.
We developed a
10.7-MHz IF bandpass discrete-time 4th-order 4-bit delta-sigma modulator for
AM/FM car radio tuners. Using direct feed-forward and double sampling, we have
achieved a dynamic range (DR) of 112 dB in the 3-kHz AM bandwidth (BW) and a DR
of 94 dB in the 200-kHz FM BW. The modulator occupies 3 mm2, in 0.15
µm CMOS technology, and draws 63 mA of current.
5.2
10:30
am
A Delta-Sigma
Modulator with a Widely Programmable Center Frequency and 82-dB Peak
SNDR, K.
Yamamoto, A. Chan Carusone and F. Dawson,
A 4-bit
fourth-order delta-sigma modulator with a widely programmable center frequency
is presented. Novel methods for quantizing and implementing the digitally
programmable modulator coefficients enable performance comparable to
state-of-the-art discrete-time fixed-frequency modulators at any center
frequency from dc to 0.31fs in steps of 0.0052fs. The 0.18-µm 1.8-V CMOS
prototype consumes 115 mW at a sampling frequency of 40 MHz. The peak SNDR and
SNR over a 310-kHz bandwidth are 82 dB and 86 dB respectively.
5.3
10:55
am
A 94dB SFDR 78dB
DR 2.2MHz BW Multi-bit Delta-Sigma Modulator with Noise Shaping
DAC, J. Chen
and Y.P. Xu, National University of Singapore
A 5th-order
multi-bit lowpass delta-sigma modulator employs a proposed noise shaping dynamic
element matching (NSDEM) technique to remove DAC non-linearity error. Unlike
most existing DEMs trading SNR for SFDR, the proposed technique improves both
SFDR and SNR. The noise shaping is incorporated in the first integrator of the
loop filter without any additional analog circuitry. The fabricated modulator
chip achieves 94dB SFDR and 78dB DR in 2.2MHz BW and meets the ADSL2+
specifications.
5.4
11:20
am
A 18mW CT
Sigma-Delta Modulator with 25MHz Bandwidth for Next Generation Wireless
Applications, X. Chen,
Y. Wang, G. Temes, Oregon State University, Y. Fujimoto, P. Lo Ré, Y. Kanazawa,
Sharp Corp., J. Steensgaard, Esion LLC
The design of a
wideband low-power continuous-time (CT) Delta-Sigma modulator is presented in
this paper. A modified feed-forward architecture is proposed to realize the
low-power loop filter as well as cancel the out-of-band peaking in the signal
transfer function. Several high-speed low-power design techniques are used in
the circuits. The modulator achieves 60 dB dynamic range (DR) within 20 MHz
signal bandwidth, and 55 dB DR within 25 MHz signal bandwidth. Clocked at 400
MHz, the modulator consumes only 10 mA current from a 1.8 V supply.
5.5
11:45
am
Multi-Bit Sigma
Delta ADC with Reduced Feedback Levels, Extended
A novel second
order sigma delta modulator (SDM) with 5-bit quantizer has been proposed with simplified DAC arrays,
high-order truncation noise shaping for increased tolerance to analog
imperfections, and extended dynamic range for a maximum input signal swing of up
to -0.45dBFS. With truncation
filter and pseudo SDM in the DSP, the truncation and saturation errors are
compensated through the DAC arrays and the DSP. The design was fabricated in 0.18µ Dual
Gate Oxide (DGO) process. A SNDR
(Signal-to-Noise-and–Distortion Ratio) of 98.4 dB and a SNR (Signal-to-Noise
Ratio) of 108-dB were measured for a 31.25-KHz signal bandwidth at 8-MHz
sampling frequency with a power consumption of about 14.7 mW.
Session 6 – Advances in Programmable
Devices
Oak
Ballroom, Monday Afternoon, September 17
Chair:
Co-Chair:
Programmable
devices are everywhere: from consumer products to high-security
applications. This session
highlights novel architectures, new CAD techniques, and innovative technologies
that make these systems possible.
1:30
pm
Introduction
6.1
1:35 pm
Coarse-Grained
Reconfigurable Image Stream Processor for Digital Still Cameras and
Camcorders, J. C.
Chen, S.-Y. Chien,
A 345Mpixels/s
coarse-grained reconfigurable image stream processor (CRISP) is proposed and
implemented with 5mm2 area in 0.18µm CMOS technology for the image
pipelines of digital still cameras and video camcoders. The novel CRISP
architecture with scalable reconfigurable stage processing elements and
reconfigurable interconnection could achieve high processing speed at low cost,
while satisfying the flexibility and performance requirements of high-end image
preprocessing for 10M-pixel scale still cameras and 1920x1080
camcorders.
6.2
2:00
pm
CAD Techniques
for Power Optimization in Virtex-5 FPGAs, S.
Gupta, J. Anderson, L. Farragher and Q. Wang, Xilinx,
Inc.
We consider
dynamic power dissipation in FPGAs and present CAD techniques for dynamic power
reduction. The proposed techniques, comprising power-aware placement, routing,
and a novel post-routing transformation, are applied to optimize the power
consumed by industrial designs implemented in the Xilinx Virtex-5 FPGA. Board-level power measurements on a
suite of industrial designs show that the techniques reduce power by 10%, on
average.
6.3
2:25
pm
Flash-based Field
Programmable Gate Array Technology with Deep Trench Isolation, K.J.
Han, N. Chan, S. Kim, B. Leung, V. Hecht, B. Cronquist, Actel, D. Shum, A.
Tilke, L. Pescini, M. Stiftinger and R. Kakoschke,
Infineon
A highly scalable
flash-based Field Programmable Gate Array (FPGA) technology has been achieved
with Deep Trench Isolation (DTI).
The DTI allows for a reduced cell size and enables Independent Pwell
(IPW) operation. The IPW allows the
Fowler-Nordheim (FN) Uniform Channel Program and Erase (UCPE) with less than
±10V. Additionally, the IPW
approach allows a greater flexibility in the array bias scheme reducing the gate
disturb during programming and eliminating all Gate-Induced Drain Leakage (GIDL)
conditions. Characterization of a
FPGA cell and 0.5 Mbit array with 90nm design rules is demonstrated with
excellent electrical characteristics.
6.4
2:50
pm
Analysis of Data
Remanence in a 90nm FPGA, T. Tuan,
T. Strader and S. Trimberger, Xilinx, Inc.
FPGAs are
increasingly used in military applications where security is paramount. In this
paper, we study data remanence in modern FPGAs using a custom 90nm FPGA designed
for this test. The effects of temperatures, architecture, memory topology, and
power off methods are analyzed. We find remanence properties in FPGAs to depend
on architecture and data content. To our knowledge, this is the first study of
data remanence in FPGAs and in deep-submicron ICs.
3:15 pm -
Break
Session 7 – Emerging Wireless
Applications
Fir
Ballroom, Monday Afternoon, September 17
Chair
:
Co-Chair
: Earl McCune
Progress in
achieving high levels of integration is presented for single chip solutions in
satellite TV, WiMax-WiBRO, GPS, and RFID applications, using a variety of
process technologies.
1:30
pm
Introduction
7.1
1:35
pm
A
Single-Conversion SiGe BiCMOS Satellite TV LNB Front-End Using an Image Reject
Mixer and a Calibrated Full-Rate VCO, A.
Maxim, M. Gheorghe, D. Smith, Maxim, Inc.
A
fully-integrated satellite TV down-converter was realized in a 0.18 µm SiGe BiCMOS process that provides both
70GHz fT NPN HBTs used for the main signal path and 0.18 µm CMOS FETs used for the frequency
synthesizer reference clock path and LC-VCO frequency calibration circuitry. A
low phase-noise, low tuning gain 10GHz LC-VCO that covers both low and high
Ku-bands was realized by combining a 30% discrete steps frequency calibration
with a 2% continuous frequency tuning. Offset-biased accumulation MOS varactors
provide a virtually constant tuning gain by summing shifted C(V) curves that are
uniformly distributed over the entire control voltage range. The on-chip
synthesizer loop filter eliminates the sensitivity to off-chip noise and spur
coupling. Mixer’s noise was reduced by using an image-reject architecture that
attenuates the thermal noise contribution from the image frequency. The LNB
performance includes: <6dB noise figure, 18dBm output IP3, -106dBc/Hz phase
noise at 100KHz offset, <0.4 rms total integrated phase noise,
1.7x1.5mm2 die area and 125mA bias current from a 3.3V
supply.
7.2
2:00
pm
A Low Power, High
Performance BiCMOS MIMO/Diversity Direct Conversion Transceiver IC For
WiBro/WiMAX (802.16e) (INVITED PAPER), M.
Locher, M. Tomesen, J. Kuenen, A. Daanen, H. Visser, B. Essink, P.P. Vervoort,
M. Nijrolder, R. Kopmeiners, W. Redman-White, R. Balmford, R. El Waffaoui, NXP
Semiconductors
This paper
describes a MIMO, low power, high performance direct conversion WiBro/WiMAX
802.16e radio transceiver optimized for mobile applications and coexistence with
on-board Cellular and ISM-band systems. It is fabricated in a SiGe BiCMOS
process and achieves a receiver NF of less than 2.5dB aover an operation
frequency of 2.3-2.7GHz. The transmit gain can be digitally tuned over a 75dB
range. The transceiver consumes 65/103mA at a 2.8V supply in OFDMA Rx/Tx modes
respectively.
7.3