Poster Session
Cascade Ballroom, Monday, September 17
3:30 pm – 8:00 pm
(Authors are at the posters from 5:30 pm – 7:00 pm)
MP-01
A Re-configurable 0.5V to 1.2V, 10MS/s to 100MS/s,
Low-Power 10b 0.13um CMOS Pipeline ADC, Y.-J. Kim, H.-C. Choi, S.-W. Yoo, S.-H. Lee,
This work describes a re-configurable 0.5V to 1.2V, 10MS/s to 100MS/s, 10b
two-step pipeline ADC. The prototype ADC in a 0.13 µm CMOS process demonstrates the measured DNL and
INL within 0.35LSB and 0.49LSB, respectively. The ADC with an active die area
of 0.98mm2 shows the maximum SNDR and SFDR of 56.0dB and 69.6dB,
respectively, and a power consumption of 19.2mW at a nominal condition of 0.8V
and 60MS/s.
MP-02
20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard
Digital CMOS Process, P. N. Singh, A. Kumar, C. Debnath and R. Malik,
STMicroelectronics
This paper describes a novel low power 10-bit 125Msps pipelined ADC
implemented in 65nm standard digital CMOS process. Proposed ADC implements
2.5b/stage with amplifier shared between consecutive stages, achieves best in
class FOM of 0.27pJ/step with conversion power of 0.16mW/Msps. The ADC
amplifier employs novel techniques of adaptive biasing and cross coupled
compensation to achieve improved settling behavior with significant power
efficiency. ADC has 0.13mm2 area and 9.26ENOB @125Msps dissipating
20mW power from 1.2v supply.
MP-03
A Low-Power, 6-bit Time-Interleaved SAR ADC Using OFDM
Pilot Tone Calibration, Y. Oh and B. Murmann,
A low-power analog-to-digital converter that exploits communication system
resources for continuous self-calibration is presented. The proposed converter employs
a time-interleaved array of successive approximation register ADCs. The inter-channel
offset mismatches are adjusted by a calibration loop that utilizes the outputs
of the FFT block of an orthogonal frequency division multiplexing (OFDM)
receiver. The 6-bit prototype ADC, fabricated in a 0.18 µm CMOS technology, achieves an SNDR of 35.4dB
with a power consumption of 6.58mW at 200MS/s.
MP-04
A Fourth Order Elliptic Low-Pass Filter with Wide
Range of Programmable Bandwidth, Using Four Identical Integrators, B.
Saeidi, Skyworks Solutions
A new method to implement Elliptic filter with identical integrators and
no derivatives is presented. Using identical capacitor arrays as opposed to
highly spread capacitor arrays of conventional implementation makes Elliptic
filter design with wide range of programmable/tunable bandwidths extremely
simple, time-efficient and accurate. The proposed method also reduces the die
size while realizing Elliptic filter more faithfully. To demonstrate the
method, a fourth order Elliptic filter with nine programmable bandwidths
ranging from 1.1MHz to 17.6MHz is designed. The 1.75mm˛ filter draws 10mA from
3.3V supply at output swing of 4.0Vppd in 0.35µm CMOS process to meet less than
50nV/Hz˝ in-band output-referred noise and SFDR of better than 80dBc.
MP-05
An Idle-Tone Free Dynamic Element Matching Algorithm, M. Keppler and D.
Thelen, AMI Semiconductor
This paper presents a first order noise shaped dynamic element matching (DEM) algorithm. The DEM algorithm was
developed to improve the signal-to-noise
and distortion ratio (SNDR) of a delta-sigma analog to digital converter (ADC). However, it can be
applied to any system utilizing
averaging and a plurality of unit components. Matlab simulations have shown
that the presented algorithm eliminates idle-tones
and provides almost a 30dB improvement in SNDR in a second order delta-sigma ADC.
MP-06
A 65-dB DR 1-MHz BW 110-MHz IF Bandpass Sigma-Delta
Modulator Employing Electromechanical Loop Filter, R.
Yu and Y. P. Xu, National University of Singapore
A 4th-order bandpass Sigma-Delta modulator employing electromechanical
filter as loop filter is proposed. The electromechanical loop filter has the advantages
of low power consumption and accurate center frequency without the need for
tuning. The proposed bandpass Sigma-Delta modulator is implemented in a 0.35 µm
SiGe BiCMOS technology and tested with a
110-MHz SAW filter. When sampled at
440MHz, the prototype chip achieves 65-dB DR and 60-dB peak SNDR in a 1-MHz
signal bandwidth.
MP-07
A Current-mode ADC with Current
Exchanging and Averaging Capabilities by Switching the
Currents and Caluculating Data in the Digital Domain, N.
Yoshii, K. Mizutani and Y. Sugimoto, Chuo University
A 2 V, 25 MS/s, current-mode and pipelined analog-to-digital converter
(ADC) which realizes a 1.5-bit bit-block architecture and uses a front-end current-mode
sample-and-hold (S/H) circuit is described. The input and output currents in a
current-mirror circuit are exchanged at every clock period to obtain the
precise output current without suffering from poor current mismatch. The errors are canceled out by taking the
average of the consecutive digital codes at the output part of the ADC.
MP-08
A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS, Y.-Z. Lin, Y.-T.
Liu and S.-J. Chang, NCKU
A 5-bit flash ADC is fabricated in 0.13-µm CMOS process. Averaging and interpolation
are discussed and analyzed for power reduction. This ADC consumes 180 mW from a
1.2 V supply and occupies 0.16 mm2 area. Operating at 3.2 GS/s, the
ENOB is 4.44 bit and ERBW 1.65 GHz. At 4.2 GS/s, the ENOB is 4.20 bit and ERBW
1.75 GHz. This ADC achieves FOMs of 2.51 and 2.80 pJ/conversion-step at 3.2 and
4.2 GS/s, respectively.
MP-09
A 1.2-V CMOS Limiter / RSSI / Demodulator for Low-IF
FSK Receiver, Y.-C. Chen, Y.-C. Wu, P.-C. Huang,
This paper presents low-voltage low-power limiter, RSSI, and demodulator designs
for a low-IF wireless FSK receiver. The IF is located at 3MHz. The FSK demodulator
is implemented by a delay-locked loop associated with the techniques of digital
offset cancellation and modified phase-frequency detection. The demodulated
data can be recovered with one-clock latency. The circuits in limiter and RSSI
are all pseudo differential to minimize the requirement of the voltage
headroom. Each gain cell with feedforward offset cancellation and common mode
stabilization circuits can make sure its functionality against device mismatch.
The chip uses a standard 0.18 µm CMOS
process. The active area is 0.11mm2. With a single 1.2-V power supply, measurement
results show that the 55dB gain, 15MHz bandwidth limiter and the RSSI consume
1.9mA. The FSK demodulator part consumes 300µA.
MP-10
Temperature Sensor Design in a High Volume
Manufacturing 65nm CMOS Digital Process,
D.
Thermal management (TM) allows the system architect to design a cooling solution
based on real-life power consumption, not peak power. The on-die thermal sensor
circuit, as the core of the TM system, monitors the on-die junction temperature
(Tj). We present a novel high-linearity thermal sensor topology with built-in
circuit support for correction of systematic shifts in the transfer function
correction. Results obtained on the 65nm Pentium®4 Processor demonstrate the feasibility and
effectiveness of the design.
MP-11
Six and Seven Transistor Leakage Suppressed SRAM Cells
with Improved Read Stability, S.
Badrudduza and L. Clark, Arizona State University
Static random access memories with six and seven transistor cells that
maintain full static noise margin during read operation and reside in low
leakage voltage collapsed state when unselected are presented. The memory test circuits are fabricated on a 0.13
µm CMOS process technology. The cells are 11% larger than a conventional SRAM
cell.Measured test results verify the power, speed and usable range of power
supply voltages for the designs.
MP-12
Rapid Estimation of the Probability of SRAM Failure
due to MOS Threshold Variations., S.
Srivastava and J. Roychowdhury, University of Minnesota
Accurate estimation of the effects of threshold variations, in particular
yield loss, is crucial during the design of robust SRAM cells and memory arrays
in deep submicron technologies. We present an efficient technique to calculate
yield loss due to access-time, static noise margin, etc, related failures. Our
method does not rely on Monte-Carlo techniques; instead, it finds the boundary
in Vt (threshold voltage) parameter space
between success and failure regions and uses quick geometrical calculations to
find the yield. The Vt
boundary curve is found efficiently via an Euler-Newton curve
tracing technique, adapted from mixed-signal/RF simulation, that guides
detailed SPICE-level simulation with accurate MOS device models. We compare and
validate the new method against Monte-Carlo style yield estimation, obtaining
superior accuracies and speedups of more than 10 x.
MP-13
A Stable SRAM Mitigating Cell-Margin Asymmetricity
with A Disturb-Free Biasing Scheme, T.
Suzuki, K. Satomi and H. Akamatsu, Matsushita Electric Industrial Co., and H.
Yamauchi, Fukuoka Instute of Technology
A Reduced-Vt SRAM (LVt) cell and a unique disturbe-free biasisng scheme
have been proposed for the low-voltage application. The proposed LVt cell
mitigated the cell-margin asymmetricity and improved the SNM at high z-score
range up to 7σ random-Vt fluctuation at the cell-bias=0.5V. Another unique
disturb-free biasisng scheme canceled the substantial trade-off relationaship between
the cell-margins. The cell/logic bias voltage were reduced to 0.5/0.7V with
higher stability over 6σ Vt fluctuation compared with the conventional
biasing scheme. The operating current was reduced by 31%.
MP-14
Dynamic Data Stability in Low-power SRAM Design, M. Sharifkhani,
S. Jahinuzzaman and M. Sachdev,
SRAM cell stability measurement is traditionally based on ‘static
criteria’ of data stability requiring 3 coincident points in butterfly curves. We
introduce ‘dynamic criteria’ of stability. This enables reducing cell operating
voltage without compromising reliability once cell access-time is less than cell time-constant.
Experimental results of a 40Kb SRAM exploit the dynamic criteria, offering 6
times smaller area overhead compared to recent subthreshold schemes. The SRAM
unit realized in 0.13µm-CMOS consumes 702uW at 100MHz during write-operation
and offers a 27pA/cell leakage.
MP-15
An 8T Subthreshold SRAM Cell Utilizing Reverse Short
Channel Effect for Write Margin and Read Performance Improvement, T.-H. Kim, J. Liu
and C. H. Kim,
We propose a technique for improving write margin and read performance of
8T subthreshold SRAMs by using long channel devices to utilize the pronounced reverse
short channel effect. Simulations show that the proposed cell at 0.2V has a
write margin equivalent to a conventional cell at 0.27V. The Ion-to-Ioff ratio
of the read path also improved from 169 to 271 and a 52% speedup for read was
achieved. The cell area overhead was 20%.
MP-16
Solution to ESD Induced Pocket Isolation Failure in
Multi Well CMOS, T. Ruud, B. Rasmussen, B. Greenwood, and M. Tyler AMIS
An Nepi pocket isolation weakness was identified during ESD qualification
of a multi-well CMOS process. Upon
initial process ESD qualification, inter-domain testing identified leakage
failures in unstressed power supply domains.
This work describes how novel failure analysis techniques identified a
parasitic NPN that was instrumental in creating this unusual failure
signature. Strategic changes to and
placement of ESD protection elements and improved metalization successfully
prevented activation of parasitic bi-polar transistors hence, avoiding
expensive process modifications.
MP-17
Integration of CMP Modeling in RC Extraction and
Timing Flow, H.
Liao, R. Radojcic, Qualcomm, L. Song, N. Jakatdar, Cadence Designs
As technology scaling progresses into 65nm and below nodes, on chip
variation due to Chemical Mechanical Polishing (CMP) becomes relatively larger
and needs to be considered. In this paper, we demonstrate that by incorporating
CMP model in the post layout RC extraction flow, the thickness variations are
reflected more accurately and the capacitance value extracted are different
from results obtained using the polynomial equation. As a result, new timing
violations are detected with CMP modeling.
MP-18
Integrated Inductor Actively Engaging Metal Filling
Rules, J.I. Kim, B. Jung, D. Peroulis,
This paper reports a new strip-patterned integrated inductor that actively
engages metal filling rules leading to reduced manufacturing cost and process-induced
uncertainties while simultaneously maintaining state-of-the-art performance.
The striped inductor consists of parallel horse shoe-shape metal lines in the
foot print of a single-line inductor. The new inductor structure is backed by
experimental and simulated results that demonstrate the design methodology in
the presence of process uncertainties typically not known to the circuit designer.
MP-19
A Wide Range Spatial Frequency Analysis of Intra-Die
Variations with 4-mm 4000 x 1 Transistor Arrays in 90nm CMOS, D.
Levacq, T. Minakawa, M. Takamiya and T. Sakurai, University of Tokyo
In order to investigate the systematic intra-die variations, the intra-die
threshold voltage and on-current variations are measured thanks to 4-mm 4000 x 1
transistor arrays with 1 µm transistor-pitch in a 90nm CMOS technology, achieving the widest spatial distribution
range. The spatial frequency analysis of
the variations indicates that both variations are random across 4 mm.
MP-20
Architecture of Via Programmable Logic using
Exclusive-OR Array (VPEX) for EB Direct Writing, A. Nakamura, M.
Kawaharazaki, T. Fujino, Ritsumeikan
University, M. Yoshikawa, Meijo University
We propose the novel architecture of Via Configurable Logic Device called VPEX which is optimized for Electron Beam
direct writing. The logic element of VPEX consists of complex gate type EXOR
and INV. This element can output 12 logics by changing via1 layout. The speed
performance of VPEX is 1.5 times slower than ASICs but much higher than FPGAs.
We believe that VPEX with EB is the best solution for low-volume production
LSIs.
MP-21
Receiver Offset Cancellation in 90-nm PLD Integrated
SERDES, S.
Maangat, T. Nguyen, W. Wong, S. Shumarayev, T. Tran, T. Hoang and R. Cliff,
Altera Corporation
A wide-range transceiver was designed and fabricated in a 90-nm TSMC CMOS
logic process. Each transceiver channel contains Clock Data Recovery (CDR)
circuit. Voltage offsets in the receive
path degrade the performance of the CDR by
reducing the precision of bit detection and cause duty cycle distortion. Presented in this paper is a methodology to
cancel voltage offsets in the receive path with a soft intellectual property
(IP) core programmed in the PLD.
MP-22
Dual True Random Number Generators for Cryptographic
Applications Embedded on a 200 Million Device Dual CPU SoC, V. von Kaenel and
T. Takayanagi, PASemi
Implementations of a thermal noise and a chaotic True Random Number
Generator are presented. They are embedded in a large commercial SoC. Their
outputs are combined to improve the randomness of the bit stream. The design
goal was to minimize the effect of data dependent noise injected by the
supplies and substrate. The random bit rate is 2Mbit/s and passes the DIEHARD
test suite. The circuit area is 0.21mm2
in a 65nm CMOS process.
MP-23
A 0.22nJ/b/iter 0.13µm Turbo Decoder Chip Using
Inter-Block Permutation Interleaver, C.-C. Wong, C.-H. Tang, M.-W. Lai, Y.-X. Zheng, C.-C.
Lin, H.-C. Chang, C.-Y. Lee and Y.-T. Su,
This paper presents a high speed turbo decoder containing 32 MAP decoders
with an inter-block permutation interleaver.
This network guarantees contention-free property and promise parallel processing
of turbo decoder without performance degradation. In addition, our approach also features a
relocated radix-2*2 ACS structure to reduce the critical path delay. After manufacturing by 0.13µm CMOS process,
the test results show the energy efficiency is 0.22nJ/b/iter in the 160Mb/s
data rate.
MP-24
A 10-Gb/s CMOS Serial-Link Receiver using Eye-Opening
Monitoring for Adaptive Equalization and for Clock and Data Recovery, T. Suttorp and U.
Langmann,
A 10-Gb/s receiver for chip-to-chip communication is presented which
employs an eye-opening monitor for both adaptive equalization and digital clock
and data recovery (CDR). The prototype circuit fabricated in 0.13-µm CMOS
technology consumes about 164 mW at 1.2 V supply voltage and occupies about
0.39 x 0.39 mm2. The CDR fulfills the SONET/SDH jitter tolerance
requirements at a 231-1 PRBS and a BER of < 10E-12.
Successful adaptive equalization for FR4 channels up to 76 cm is also demonstrated.
MP-25
A 1-V, 1.4–2.5 GHz Charge-Pump-Less PLL for a Phase
Interpolator Based CDR, J. Park, Samsung Electronics, J. F. Liu, C. P. Yue,
A 1.4-2.5 GHz charge-pump-less phase locked loop and a linear phase interpolator
with dummy cells to enhance linearity are implemented in 0.13-µm CMOS. The loop
filter with RC integrators and a V-I converter are proposed for achieving wide
frequency range and high linearity in the voltage controlled oscillator under a
low supply voltage. The measured RMS and peak-peak jitters are 4.05 ps and
28.18 ps at 2 GHz, respectively. The measured DNL and INL of the PI are 0.27
LSB and 0.68 LSB, respectively.
MP-26
A 10Gb/s Equalizer with Decision Feedback for High
Speed Serial Links, A. Kiaei, A. Bahai, T. Lee,
A 10Gb/s equalizer using both feedforward and decision-feedback
equalization is designed for high speed serial-links. The chip is implemented
in a standard 0.25µm SiGe BiCMOS technology with 50 GHz peak ft, and packaged
in a commercial LLP package. Using a 4-stage feedforward and 2-tap post-cursor
cancellation, this equalizer achieves a total peak-to-peak jitter of 27ps and
33ps for 10" and 20" of copper traces on FR4, respectively. The
transmitter uses NRZ signaling with no
pre-emphasis.
MP-27
Concurrent Digital Adaptive Decision Feedback
Equalizer for 10GBase-LX4 Ethernet System, C.-S. Lin, Y.-C.
Lin, M.-T. Shiou,
An all digital 3.5Gbps blind Adaptive Decision Feedback Equalizer (ADFE)
is designed for 10GBase-LX4 IEEE 802.3ae standard. It uses 5 parallel
equalization blocks each with 6 taps and 4 taps for each Feed-Forward Equalizer
(FFE) and Feed-Back Equalizer (FBE). This concurrent ADFE has core area of
0.864 × 0.864 mm2 with operation up to 3.5 Gbps using 1.2-V supply
in a 0.13 µm CMOS process.
MP-28
A 2.5 Gbps CMOS Fully Integrated Optical Receiver with
Lateral PIN Detector, W.-Z. Chen and S.-H. Huang,
This paper presents the design of a monolithically integrated CMOS optical
receiver, including a photo detector, a transimpedance amplifier, and a post limiting
amplifier on a single chip. A novel PIN detector is proposed and adopted in
this design without technology modification.
The optical receiver is capable of delivering 420 mVpp to 50 ohm output load and operating up to 2.5 Gbps
without an equalizer. Implemented in a generic 0.18 µm CMOS technology, the
total power dissipation is 138 mW. The chip size is 0.53 mm2.
MP-29
A New Spread Spectrum Clock Generator for SATA Using
Double Modulation Schemes, Y.-B. Hsieh,
A new spread spectrum clock generator (SSCG) using double modulation is presented
in this paper. Not only the divider is varied, but also the voltage controlled
oscillator is modulated. This technique can enhance the modulation bandwidth so
that the effect of EMI suppression is improved and can optimize the jitter
caused by the sigma-delta modulator. In addition, the method of two-path is
applied to reduce the capacitance value such that the total integration can be
achieved. The proposed SSCG has been fabricated in a 0.18 µm CMOS process. The clock of 1.5GHz with down
spread ratio of 0.5% is realized for applications to serial ATA. The 19.63dB
EMI reduction (RBW=10KHz) and 35ps-pp period jitter are achieved in this study.
The size of chip area is 0.44×0.48mm2. The power consumption is
27mW.
MP-30
An Energy-efficient Multi-bit Quaternary Current-mode
Signaling for On-chip Interconnects, V.
Venkatraman and W. Burleson, University of Massachusetts Amherst
We present a multi-bit quaternary current-mode signaling (MQCMS) system
which transmits two digital signals over one interconnect using current levels
and is implemented on a 130nm IBM CMOS process. Measurement results show the
MQCMS system with data rates of 2.3Gb/s/ch to 1.1GB/s/ch and energy of 0.19pJ/b
to 0.57pJ/b for wires between 1mm to 5mm respectively. Measurement results also
show 2x reduction in energy per bit compared to repeaters for a 5mm wire. Overall, MQCMS provides an energy-efficient,
crosstalk noise resilient, on-chip interconnect signaling system with data
rates comparable to conventional repeaters.
MP-31
A 0.6GHz to 2GHz Digital PLL with
A digital PLL employing an adaptive tracking technique and a novel
frequency acquisition scheme achieves a wide tracking range and fast frequency
acquisition. The test chip fabricated in a 0.13µm CMOS process operates from
0.6GHz to 2GHz and achieves better than ±3200ppm frequency tracking range when
the reference clock is modulated with a 1MHz sine wave.
MP-32
A 1V, 1mW, 4GHz Injection-Locked Oscillator for High
Performance Clocking,
L. Zhang, B.
Ciftcioglu and H. Wu,
A new injection-locked oscillator was designed for high performance
clocking purpose. It uses transformer injection and incorporates a switched
capacitor array for digital delay tuning. A 4GHz test chip was implemented in
0.18µm CMOS with four ILOs driven by an H-tree. 5-bit digital deskew achieves
55ps delay tuning range and 1.8ps resolution. Measurement shows that only 30fs cycle-to-cycle
jitter degradation was introduced and no phase noise degradation at frequency
offset up to 600kHz.