Session 6 – Advances in Programmable Devices
Oak Ballroom, Monday Afternoon, September 17
Chair:
Co-Chair:
Programmable devices are everywhere: from consumer products to
high-security applications. This session
highlights novel architectures, new CAD techniques, and innovative technologies
that make these systems possible.
1:30 pm
Introduction
6.1
1:35 pm
Coarse-Grained Reconfigurable Image Stream Processor
for Digital Still Cameras and Camcorders, J.
C. Chen, S.-Y. Chien,
A 345Mpixels/s coarse-grained reconfigurable image stream processor
(CRISP) is proposed and implemented with 5mm2 area in 0.18µm CMOS
technology for the image pipelines of digital still cameras and video
camcoders. The novel CRISP architecture with scalable reconfigurable stage
processing elements and reconfigurable interconnection could achieve high
processing speed at low cost, while satisfying the flexibility and performance
requirements of high-end image preprocessing for 10M-pixel scale still cameras
and 1920x1080 camcorders.
6.2
2:00 pm
CAD Techniques for Power Optimization in Virtex-5
FPGAs, S.
Gupta, J. Anderson, L. Farragher and Q. Wang, Xilinx, Inc.
We consider dynamic power dissipation in FPGAs and present CAD techniques
for dynamic power reduction. The proposed techniques, comprising power-aware placement,
routing, and a novel post-routing transformation, are applied to optimize the
power consumed by industrial designs implemented in the Xilinx Virtex-5
FPGA. Board-level power measurements on
a suite of industrial designs show that the techniques reduce power by 10%, on
average.
6.3
2:25 pm
Flash-based Field Programmable Gate Array Technology
with Deep Trench Isolation, K.J.
Han, N. Chan, S. Kim, B. Leung, V. Hecht, B. Cronquist, Actel, D. Shum, A. Tilke,
L. Pescini, M. Stiftinger and R. Kakoschke, Infineon
A highly scalable flash-based Field Programmable Gate Array (FPGA)
technology has been achieved with Deep Trench Isolation (DTI). The DTI allows for a reduced cell size and
enables Independent Pwell (IPW) operation.
The IPW allows the Fowler-Nordheim (FN) Uniform Channel Program and
Erase (UCPE) with less than ±10V.
Additionally, the IPW approach allows a greater flexibility in the array
bias scheme reducing the gate disturb during programming and eliminating all
Gate-Induced Drain Leakage (GIDL) conditions.
Characterization of a FPGA cell and 0.5 Mbit array with 90nm design
rules is demonstrated with excellent electrical characteristics.
6.4
2:50 pm
Analysis of Data Remanence in a 90nm FPGA, T.
Tuan, T. Strader and S. Trimberger, Xilinx, Inc.
FPGAs are increasingly used in military applications where security is paramount.
In this paper, we study data remanence in modern FPGAs using a custom 90nm FPGA
designed for this test. The effects of temperatures, architecture, memory
topology, and power off methods are analyzed. We find remanence properties in
FPGAs to depend on architecture and data content. To our knowledge, this is the
first study of data remanence in FPGAs and in deep-submicron ICs.
3:15 pm - Break
Session 7 – Emerging Wireless Applications
Fir Ballroom, Monday Afternoon, September 17
Chair :
Co-Chair : Earl
McCune
Progress in achieving high levels of integration is presented for single
chip solutions in satellite TV, WiMax-WiBRO, GPS, and RFID applications, using
a variety of process technologies.
1:30 pm
Introduction
7.1
1:35 pm
A Single-Conversion SiGe BiCMOS Satellite TV LNB
Front-End Using an Image Reject Mixer and a Calibrated Full-Rate VCO, A.
Maxim, M. Gheorghe, D. Smith, Maxim, Inc.
A fully-integrated satellite TV down-converter was realized in a 0.18 µm SiGe BiCMOS process that provides both 70GHz
fT NPN HBTs used for the main signal path and 0.18 µm CMOS FETs used for the frequency synthesizer reference
clock path and LC-VCO frequency calibration circuitry. A low phase-noise, low tuning
gain 10GHz LC-VCO that covers both low and high Ku-bands was realized by combining
a 30% discrete steps frequency calibration with a 2% continuous frequency
tuning. Offset-biased accumulation MOS varactors provide a virtually constant
tuning gain by summing shifted C(V) curves that are uniformly distributed over
the entire control voltage range. The on-chip synthesizer loop filter
eliminates the sensitivity to off-chip noise and spur coupling. Mixer’s noise
was reduced by using an image-reject architecture that attenuates the thermal
noise contribution from the image frequency. The LNB performance includes:
<6dB noise figure, 18dBm output IP3, -106dBc/Hz phase noise at 100KHz offset,
<0.4 rms total integrated phase noise, 1.7x1.5mm2 die area and
125mA bias current from a 3.3V supply.
7.2
2:00 pm
A Low Power, High Performance BiCMOS MIMO/Diversity
Direct Conversion Transceiver IC For WiBro/WiMAX (802.16e) (INVITED PAPER), M.
Locher, M. Tomesen, J. Kuenen, A. Daanen, H. Visser, B. Essink, P.P. Vervoort,
M. Nijrolder, R. Kopmeiners, W. Redman-White, R. Balmford, R. El Waffaoui, NXP
Semiconductors
This paper describes a MIMO, low power, high performance direct conversion
WiBro/WiMAX 802.16e radio transceiver optimized for mobile applications and coexistence
with on-board Cellular and ISM-band systems. It is fabricated in a SiGe BiCMOS
process and achieves a receiver NF of less than 2.5dB aover an operation
frequency of 2.3-2.7GHz. The transmit gain can be digitally tuned over a 75dB
range. The transceiver consumes 65/103mA at a 2.8V supply in OFDMA Rx/Tx modes
respectively.
7.3
2:25 pm
A Low-IF CMOS Simultaneous GPS Receiver Integrated in
a Multimode Transceiver, Y.
Xu, K. Wang, T. Pals, A. Hadjichristos, K. Sahota and C. Persico, Qualcomm,
Inc.
This paper describes a low-IF GPS receiver circuit that operates
simultaneously with WCDMA/CDMA2000 transceivers. The RF front-end circuit
dynamically adjusts the linearity performance based on the instantaneous
transmitting power of the integrated transmitter. The receiver measured
performances are >80dB gain, 2.0dB noise figure, maximum out-of-band IIP3 is
+6dBm. The receiver is fabricated in a 0.18µm RFCMOS process, and draws 36.7mA
at high linearity mode and 27.4mA at low linearity mode using switch mode power
supply.
7.4
2:50 pm
A Single-Chip UHF RFID Reader in 0.18 µm CMOS, W.
Wang, S. Lou, K. Chui, S. Rong, C.-F. Lok, H. Zheng, H.T. Chan, S.W. Man, H.C.
Luong, V.K. Lau and C.-Y. Tsui,
An 860MHz-960MHz UHF RFID reader is designed in 0.18 µm CMOS that fully integrates an RF transceiver
and a digital baseband. Highly reconfigurable mixed-signal baseband
architecture for channel selection filtering is proposed to achieve optimal
power consumption for multi-protocol operation with different system dynamic
ranges and data rates. In the talk mode with LNA bypassed, the RX measures a
sensitivity of –70dBm in the presence of a –5dBm self-interferer. In the listen
mode, LNA is turned on, and RX sensitivity of –90dBm is measured. The TX
achieves output power from –9 to 11dBm with output P-1dB of 10.4dBm.
3:15 pm - Break
Session 8 – Microsystems for BioMedical
Applications
Pine Ballroom, Monday Afternoon, September 17
Chair:
Co-Chair : Sudhir
Aggarwal
A tutorial
on the acquisition of biopotentials is presented
followed by three papers on emerging microsystems for
biomedical applications. These include
circuit innovations in MRI, hearing aid and tactile imaging.
1:30 pm
Introduction
8.1
1:35 pm
A Versatile Integrated Circuit for the Acquisition of
Biopotentials (INVITED PAPER), R.
Harrison,
Electrically active cells in the body produce a wide variety of voltage
signals that are useful for medical diagnosis and scientific
investigation. These biopotentials span
a wide range of amplitudes and frequencies.
We have developed a versatile front-end integrated circuit that can be
used to amplify many types of bioelectrical signals. The 0.6- µm CMOS chip contains 16 fully-differential
amplifiers with gains of 46 dB, 2uVrms input-referred noise, and bandwidths
programmable from 10Hz to 10kHz.
8.2
2:00 pm
A Spectral-Scanning Magnetic Resonance Imaging (MRI)
Integrated System, A.
Hassibi, University of Texas, A. Babakhani and A. Hajimiri, California
Institute of Technology
An integrated spectral-scanning magnetic resonance imaging (MRI) technique
is implemented in a 0.12µm SiGe BiCMOS process. This system is designed for small-scale
MRI applications with non-uniform and low magnetic fields. The system is
capable of generating customized magnetic resonance (MR) excitation signals,
and also recovering the MR response using a coherent direct conversion receiver.
The operation frequency is tunable from DC to 37MHz for wide-band MRI and up to 250MHz for narrow-band MR
spectroscopy.
8.3
2:25 pm
A Real-Time Feedback Controlled Hearing Aid Chip with
Reference Ear Model, S.
Kim, S.J. Lee, N. Cho, S.-J. Song and H.-J. Yoo, KAIST
A real-time hearing aid chip with the reference ear model (REM) and the comparison
processor (COMP) is proposed and implemented. Through the COMP the response
differences between the reference ear model and the impaired ear of the patient
are achieved and processed to compensate the hearing loss of the patient. By
adopting this architecture, the fully internal gain fitting and verification of
the hearing aid with only single initial hearing loss test is implemented. To
reduce the power dissipation and achieve the high flexibility, the preamplifier
which has programmable multi threshold voltages is introduced. The feedback
controlled hearing aid chip is implemented in 0.18 µm CMOS technology, consumes
less than 110 µW and has a die size of 3.7 mm2.
8.4
2:50 pm
Multi-functional Monolithic-MEMS Tactile Imager Using
Flexible Deformation of Silicon IC, H.
Takao, M. Yawata, R. Kodama, K. Sawada and M. Ishida, Toyohashi University of
Technology
In this paper, a novel device technology of multi-functional MEMS tactile imager
using flexible deformation of silicon IC for advanced tactile sensing applications
is investigated. Presently obtained performances of multi-functional tactile
imager with sensing abilities of contact-force, hardness and temperature
distributions are totally discussed for the first time. Finally, total
integration design of multi-functional monolithic tactile imager is presented
considering robustness of the sensor structure under practical use in tactile
applications.
3:15 pm – Break
Session 9 – Test, Characterization, and Jitter of
High-Speed Serial I/O and Clocks
Cedar Ballroom,
Monday Afternoon, September 17
Chair:
Co-Chair : Gordon
Roberts
Characterization, test and jitter measurements are reaching picosecond
resolution for high speed serial links and clock networks.
1:30 pm
Introduction
9.1
1:35 pm
Testing SerDes Beyond 4 Gbps – Changing Priorities
(INVITED PAPER),
After briefly reviewing conventional jitter and jitter tolerance tests for SerDes, this paper shows that ISI is a
dominant source of bit errors above 4 Gbps, and is inadequately tested. We demonstrate the correlation between ISI and
transition-density dependent delay (TDDD) at 3.1 Gbps, and provide detailed 6.25
Gbps silicon results for an undersampling digital BIST that can measure jitter,
TDDD, and other parameters at production speeds with picosecond^sresolution.
9.2
2:00 pm
Challenges and Solutions for Standards-Based Serial 10
Gb/s Backplane Ethernet (INVITED PAPER),
A. Healey, LSI Corporation
The application of Ethernet as a fabric technology in modular platforms
has led to interest in the development of a standard set of physical layer
subsystems to support this practice. Recently, the IEEE 802.3ap-2007 standard,
commonly referred to as Backplane Ethernet, was approved. This standard defines
the electrical performance of the backplane interconnect, transmitters, and
receivers required to support data rates up to 10 Gb/s per channel. This paper
provides an overview of the key specifications for serial 10 Gb/s Backplane
Ethernet and relates the requirements to backplane construction considerations
and link performance trade-offs.
9.3
2:50 pm
2GS/s, 10ps Resolution CMOS Differential Time-to-Digital
Converter for Real-Time Testing of Source-Synchronous Memory Device, K.
Yamamoto, M. Suda and T. Okayasu, Advantest Corporation
A Differential Time-to-Digital Converter (TDC), fabricated in 0.18mm CMOS process,
for source-synchronous device testing is demonstrated. It exhibits a maximum
sampling rate of 2.133GS/s, a variable resolution of 10-40ps, an infinite
measurement range, an INL of 8.5ps(pk-pk), and a jitter of 18.3ps(pk-pk). It is
available to be applied to the jitter histogram measurement without dead-time
because it detects all transition timing continuously. Furthermore, a possible
application of this TDC to ADC or DAC is suggested.
3:15 pm – Break
9.4
3:35 pm
Optimizing Circuit Performance and ESD Protection for
High-Speed Differential I/Os, H.
Sarbishaei, O. Semenov and M. Sachdev,
Impact of ESD protection devices on circuit operation is very important in
gigahertz applications. In this paper, the impact of different ESD protection methodologies
on CML drivers is discussed. ESD protection is provided using MOSFET and SCR
devices. Study of the interaction between driver and ESD protection circuit
shows that jitter is very sensitive to parasitics of ESD protection circuits.
Furthermore, an analysis shows that substrate-triggering has less impact on
jitter compared to gate-coupling
9.5
4:00 pm
Embedded Test Features for High-Speed Serial I/O
(INVITED PAPER), J.
Rearick, Advanced Micro Devices
High-speed serial I/O interfaces are becoming ubiquitous, yet remain very challenging
to test effectively and efficiently (or even at all) during high volume
production. The use of on-chip test and
measurement circuitry to assist or replace external equipment is an emerging
paradigm to address the issue. A brief
survey of these embedded test features and their optimization for HVM support,
plus an overview of the activity of the IEEE P1687 working group, is presented.
9.6
4:25 pm
On-Chip Circuit for Measuring Period Jitter and Skew
of Clock Distribution Networks, K.
Jenkins, IBM TJ Watson Research Center, K. Shepard and Z. Xu, Columbia
University
A circuit for on-chip measurement
of period jitter and skew of clock distribution is described. The circuit uses
a single latch and a voltage-controlled delay element. The circuit is evaluated
in a stand-alone pad frame, where a jitter resolution of about 1 ps is
demonstrated, and is incorporated in a 2 GHz clock distribution network to
obtain on-chip period jitter and clock skew measurement.
9.7
4:50 pm
Mismatch-Tolerant Circuit for On-Chip Measurements of
Data Jitter, K.
Ichiyama, M. Ishida, T. Yamaguchi, Advantest Laboratories, and M. Soma,
University of Washington
A new design for a mismatch-tolerant on-chip data jitter measurement
circuit in 0.11-µm CMOS is experimentally verified in this paper. It utilizes a data-to-clock converter, pulse
generators, and an integrator followed by a sample-&-hold. The circuit’s tolerance to data-rate changes
is verified using 2.5 Gbps and 2.98 Gbps PRBS signals. The jitter gain of the prototype circuit is
also shown to be less sensitive to variations in the supply voltage.
Session 10 – Panel Discussion
Oak Ballroom, Monday Afternoon, September 17
4:00 pm - 5:30 pm
Are Analog Designers Hopeless At Scaling?
Will Digital Designers Eat Their Lunch At 45nm And Below?
Organizer: Sudhir Aggarwal, Adonics Technology
Panel Moderator:
Panelists:
Prof. Boris Murmann
Dr. Marcel Pelgrom
NXP Semiconductor
Prof. B.E. Boser
Dr. Ian Young
Intel
Prof. Peter Kinget
Dr. Bill Krenik
Three decades of relentless device scaling have resulted in
reduction of the MOS transistor length to 45nm. Even shorter channel lengths
can be expected over the coming years. Scaling has provided consistent
improvements in digital circuit density and performance. However, analog
circuit implementations have not been as successful in exploiting scaling for
achieving improvement in performance or density. This raises a question as to
what are the factors limiting analog circuits scaling.
Is it limited by the nature of analog signal processing
requirements? Or it may be that analog designers are hopeless at scaling. Can
analog circuits benefit from digital system integration at and below 45nm? A
panel consisting of experts will deliberate on the possible trends while
providing insight into issues of analog scaling.
Session 11 – Biomedical Sensors
Pine Ballroom, Monday Afternoon, September 17
Chair:
Co-Chair : Ken Szajda
This session presents innovative uses of
integrated circuits for biomedical applications.
3:30 pm
Introduction
11.1
3:35 pm
A 0.18 µm CMOS Capacitve Detection Lab-on-Chip (INVITED PAPER), E.
Ghafar-Zadeh and M. Sawan, Ecole Polytechnique de Montreal
In this paper, we put forward a CMOS-based capacitive interface circuit
for Lab-on-Chip applications. This
simple capacitive detector is implemented in the TSMC 0.18 CMOS process to
which we incorporate microfluidic channels. In addition, we address the
often-neglected challenges of microfluidic packaging for integrated biochemical
sensors by proposing an efficient direct-write microfluidic packaging
procedure. The simulation, fabrication and preliminary measurement results are
also presented and discussed.
11.2
4:25 pm
A 400MHz RF Transceiver for Implantable Biomedical
Micro-Stimulators, E.
Lee, P. Hess, J. Gord, H. Stover and P. Nercessian, Alfred Mann Foundation
A 2.5MB/s, 400MHz RF transceiver was design for implantable biomedical micro-stimulators
in a 0.18µm CMOS process. It consists of a transmitter with an output power of
–4.5dBm and a receiver that can detect input signal at <–95dBm. When one
time slot of 6µs in a ~11ms data frame is used, the transceiver has an
effective bit rate of 1.36kB/s, and consumes ~23µA for receive and ~8µA for
transmit from a 3.6V battery. The total number of stimulators that the system
can support is 852.
11.3
4:50 pm
A Monolithic Bandpass Amplifier for Neural Signal
Processing with 25-Hz Low-Frequency Cutoff, P.
Samsukha and S. Garverick, Case Western Reserve University
A monolithic bandpass amplifier for neural signal recording is
reported. The low-frequency cutoff of
the amplifier is obtained using low-gm feedback and a bias current of 500 pA to
obtain a predictable response without off-chip components or calibration. The measured passband gain is 37.9 dB from 25
Hz to 15 kHz and input-referred noise is 1.04 µV rms, using a power consumption
of 162 µW and a die area of 0.13 mm2 in 0.5-µm CMOS.
11.4
5:15 pm
A Low Power Carbon Nanotube Chemical Sensor System, T.
S. Cho, K.-J. Lee, J. Kong and A. Chandrakasan, Massachusetts Institute of
Technology
This paper presents an energy efficient chemical sensor system that uses
carbon nanotubes (CNT) as the sensor. The room-temperature operation of CNT
sensors eliminates the need for micro hot-plate arrays, which enables the low
energy operation of the system. The sensor interface chip is designed in a 0.18
µm CMOS process and consumes, at maximum, 32 µw;W at 1.83 kS/s conversion rate.
The designed interface achieves 1.34% measurement accuracy over 10 kΩ - 9
MΩ dynamic range. The functionality of the full system, including CNT
sensors, has been successfully demonstrated.
Poster Session
Cascade Ballroom, Monday, September 17
3:30 pm – 8:00 pm
(Authors are at the posters from 5:30 pm – 7:00 pm)
MP-01
A Re-configurable 0.5V to 1.2V, 10MS/s to 100MS/s,
Low-Power 10b 0.13um CMOS Pipeline ADC, Y.-J.
Kim, H.-C. Choi, S.-W. Yoo, S.-H. Lee,
This work describes a re-configurable 0.5V to 1.2V, 10MS/s to 100MS/s, 10b
two-step pipeline ADC. The prototype ADC in a 0.13 µm CMOS process demonstrates the measured DNL and
INL within 0.35LSB and 0.49LSB, respectively. The ADC with an active die area
of 0.98mm2 shows the maximum SNDR and SFDR of 56.0dB and 69.6dB,
respectively, and a power consumption of 19.2mW at a nominal condition of 0.8V
and 60MS/s.
MP-02
20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard
Digital CMOS Process, P.
N. Singh, A. Kumar, C. Debnath and R. Malik, STMicroelectronics
This paper describes a novel low power 10-bit 125Msps pipelined ADC
implemented in 65nm standard digital CMOS process. Proposed ADC implements
2.5b/stage with amplifier shared between consecutive stages, achieves best in
class FOM of 0.27pJ/step with conversion power of 0.16mW/Msps. The ADC
amplifier employs novel techniques of adaptive biasing and cross coupled
compensation to achieve improved settling behavior with significant power
efficiency. ADC has 0.13mm2 area and 9.26ENOB @125Msps dissipating
20mW power from 1.2v supply.
MP-03
A Low-Power, 6-bit Time-Interleaved SAR ADC Using OFDM
Pilot Tone Calibration, Y.
Oh and B. Murmann,
A low-power analog-to-digital converter that exploits communication system
resources for continuous self-calibration is presented. The proposed converter employs
a time-interleaved array of successive approximation register ADCs. The inter-channel
offset mismatches are adjusted by a calibration loop that utilizes the outputs
of the FFT block of an orthogonal frequency division multiplexing (OFDM)
receiver. The 6-bit prototype ADC, fabricated in a 0.18 µm CMOS technology, achieves an SNDR of 35.4dB
with a power consumption of 6.58mW at 200MS/s.
MP-04
A Fourth Order Elliptic Low-Pass Filter with Wide
Range of Programmable Bandwidth, Using Four Identical Integrators, B.
Saeidi, Skyworks Solutions
A new method to implement Elliptic filter with identical integrators and
no derivatives is presented. Using identical capacitor arrays as opposed to
highly spread capacitor arrays of conventional implementation makes Elliptic
filter design with wide range of programmable/tunable bandwidths extremely
simple, time-efficient and accurate. The proposed method also reduces the die
size while realizing Elliptic filter more faithfully. To demonstrate the
method, a fourth order Elliptic filter with nine programmable bandwidths
ranging from 1.1MHz to 17.6MHz is designed. The 1.75mm² filter draws 10mA from
3.3V supply at output swing of 4.0Vppd in 0.35µm CMOS process to meet less than
50nV/Hz½ in-band output-referred noise and SFDR of better than 80dBc.
MP-05
An Idle-Tone Free Dynamic Element Matching Algorithm, M.
Keppler and D. Thelen, AMI Semiconductor
This paper presents a first order noise shaped dynamic element matching (DEM) algorithm. The DEM algorithm was
developed to improve the signal-to-noise
and distortion ratio (SNDR) of a delta-sigma analog to digital converter (ADC). However, it can be
applied to any system utilizing
averaging and a plurality of unit components. Matlab simulations have shown
that the presented algorithm eliminates idle-tones
and provides almost a 30dB improvement in SNDR in a second order delta-sigma ADC.
MP-06
A 65-dB DR 1-MHz BW 110-MHz IF Bandpass Sigma-Delta
Modulator Employing Electromechanical Loop Filter, R.
Yu and Y. P. Xu, National University of Singapore
A 4th-order bandpass Sigma-Delta modulator employing electromechanical
filter as loop filter is proposed. The electromechanical loop filter has the advantages
of low power consumption and accurate center frequency without the need for
tuning. The proposed bandpass Sigma-Delta modulator is implemented in a 0.35 µm
SiGe BiCMOS technology and tested with a
110-MHz SAW filter. When sampled at
440MHz, the prototype chip achieves 65-dB DR and 60-dB peak SNDR in a 1-MHz
signal bandwidth.
MP-07
A Current-mode ADC with Current
Exchanging and Averaging Capabilities by Switching the
Currents and Caluculating Data in the Digital Domain, N.
Yoshii, K. Mizutani and Y. Sugimoto, Chuo University
A 2 V, 25 MS/s, current-mode and pipelined analog-to-digital converter
(ADC) which realizes a 1.5-bit bit-block architecture and uses a front-end current-mode
sample-and-hold (S/H) circuit is described. The input and output currents in a
current-mirror circuit are exchanged at every clock period to obtain the
precise output current without suffering from poor current mismatch. The errors are canceled out by taking the
average of the consecutive digital codes at the output part of the ADC.
MP-08
A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS, Y.-Z.
Lin, Y.-T. Liu and S.-J. Chang, NCKU
A 5-bit flash ADC is fabricated in 0.13-µm CMOS process. Averaging and interpolation
are discussed and analyzed for power reduction. This ADC consumes 180 mW from a
1.2 V supply and occupies 0.16 mm2 area. Operating at 3.2 GS/s, the
ENOB is 4.44 bit and ERBW 1.65 GHz. At 4.2 GS/s, the ENOB is 4.20 bit and ERBW
1.75 GHz. This ADC achieves FOMs of 2.51 and 2.80 pJ/conversion-step at 3.2 and
4.2 GS/s, respectively.
MP-09
A 1.2-V CMOS Limiter / RSSI / Demodulator for Low-IF
FSK Receiver, Y.-C.
Chen, Y.-C. Wu, P.-C. Huang,
This paper presents low-voltage low-power limiter, RSSI, and demodulator designs for a low-IF wireless FSK receiver. The IF is located at 3MHz. The FSK demodulator is implemented by a delay-locked loop associated with the techniques of digital offset cancellation and modified phase-frequency detection. The demodulated data can be recovered with one-clock latency. The circuits in limiter and RSSI are all pseudo differential to minimize the requirement of the voltage headroom. Each gain cell with feedforward offset cancellation and common mode stabilization circuits can make sure its functionality against device mismatch. The chip uses a standard 0.18 µm CMOS