Session 2 – Analog Filters
Oak Ballroom, Monday Morning, September 22
Chair: David Allee Co-Chair: Yusuf Haque
Analog filters using continuous time and switched capacitor techniques with center frequencies up to 28 MHz are demonstrated. Advancements include linearity improvements, new tuning techniques, and lower power dissipation.
Paper 2-1 - 10:05
Automatic Tuning of RC Filters and Fast Automatic Gain Control for CMOS Low-IF Transceiver, T. Oshima, K. Maio, W. Hioe, Y. Shibahara, T. Doi, Hitachi Ltd., Tokyo, Japan
Paper 2-2 - 10:30
OTA Linearity Enhancement Technique for High Frequency Applications with IM3 Below -65dB, A. Lewinski and J. Silva-Martinez, Texas A&M University, College Station, TX
Paper 2-3 - 10:55
A 58dB SNR 6th Order Broadband 10.7 MHz SC Ladder Filter, J. Silva-Martinez*, J. Adut*,** and M. Rocha-Perez*,#, *Texas A&M University, College Station, TX, **Texas Instruments, Dallas, TX and #INAOE and CINVESTAV, Guadalajara, Mexico
Paper 2-4 - 11:20
A 28-MHz Wide-Band Switched-Capacitor Bandpass Filter with High Attenuation, K.W.H. Ng and H.C. Luong, Hong Kong University of Science and Technology, Kowloon, Hong Kong
Paper 2-5 - 11:45
A Power Efficient Channel Selection Filter / Coarse AGC With No Range Switching Transients, Y. Palaskas, Y. Tsividis* and **V. Boccuzzi, Intel Labs, Hillsboro, OR, *Columbia University, New York, NY and **Agere Systems, Allentown, PA
Session 3 – SoC Design, Methodology, and Infrastructure
Fir Ballroom, Monday Morning, September 22
Chair: Henry Chang Co-Chair: Rakesh Patel
This session presents three state-of-the-art SoCs and discusses the design flows used for these multi-million-gate wireline and wireless ICs.
Paper 3-1 - 10:05
The iFlow Design Factory Infrastructure for a 17M-gate, 0.13µm, 333MHz Design, G.-E. Descamps and S. Bagalkotkar, Silicon Access Networks, San Jose, CA
Paper 3-2 - 10:55
Design and Development of the First Single-Chip Full-Duplex OC48 Traffic Manager and ATM SAR SoC, A. Khan+, K. Patel, A. Aurora*, A. Raza*, B. Parruck*, A. Bagchi*, A. Ghosh*, B. Litinsky*, E. Hong*, E. Zhao*, J. Ngo*, K. Ko*, L. Singh*, P. Arnaudov*, P. Wu*, R. Ramakrishnan*, R. Zecharia*, S. Channabasappa*, S. Kumar*, S. Wattal*, T. Wang*, U. Joshi*
Paper 3-3 - 11:20
The Intel® PXA800F Wireless Internet-On-a-Chip Architecture and Design, D. Krishnaswamy, R. Stevens, R. Hasbun, J. Revilla and C. Hagan, Intel Corporation, Folsom, CA
Session 4 – Programmable Logic: New Roads to Low Cost
Pine Ballroom, Monday Morning, September 22
Chair: Vaughn Betz Co-Chair: Steve Wilson
In today's tight economic market, cost is everything. Programmable devices of all stripes are evolving to achieve reductions in silicon, design, and mask costs.
Paper 4-1 - 10:05
SoC Implementation Issues for Synthesizable Embedded Programmable Logic Cores, J.C.H. Wu, V. Aken'Ova, S.J.E. Wilton and R. Saleh, University of British Columbia, Vancouver, Canada
Paper 4-2 - 10:30
Cyclone: A Low-Cost, High-Performance FPGA, P. Leventis*, M. Chan, M. Chan*, D. Lewis*, B. Nouban, G. Powell, B. Vest, M. Wong, R. Xia and J. Costello, Altera Corporation, San Jose, CA and *Altera Corporation, Toronto, Canada
Paper 4-3 - 10:55
Regular Logic Fabrics for a Via Patterned Gate Array (VPGA), K.Y. Tong, V. Kheterpal, V. Rovner, L. Pileggi, H. Schmit and R. Puri*, Carnegie Mellon University, Pittsburgh, PA and *IBM T.J. Watson Research Center, Yorktown Heights, NY
Paper 4-4 - 11:20
Leakage Power Analysis of a 90nm FPGA, T. Tuan and B. Lai*, Xilinx Research Labs, San Jose, CA and *University of California, Los Angeles, Los Angeles, CA
Paper 4-5 - 11:45
Architecture of Datapath-Oriented Coarse-Grain Logic and Routing for FPGAs, A. Ye, J. Rose and D. Lewis, University of Toronto, Toronto, Canada
Session 5 – Timing Recovery
Cedar Ballroom, Monday Morning, September 22
Chair: Jafar Savoj Co-Chair: Vincent Von Kaenel
This session addresses practical issues in the design of multi-gigabit clock and data recovery circuits and presents novel low-power implementations in CMOS technology.
Paper 5-1 - 10:05
Analysis of Timing Recovery for Multi-Gbps PAM Transceivers, C.-K.K. Yang and K.-L.J. Wong, University of California, Los Angeles, CA
Paper 5-2 - 10:30
A 10-Gb/s CMOS Clock and Data Recovery Circuit with an Analog Phase Interpolator, R. Kreienkamp, U. Langmann and C. Zimmerman*, Ruhr Universitaet Bochum, Bochum, Germany and *Toshiba Electronics, Dusseldorf, Germany
Paper 5-3 - 10:55
A 33mW 8Gb/s CMOS Clock Multiplier and CDR for Highly Integrated I/Os, H.-T. Ng, M.-J. E. Lee, R. Farjad-Rad, R. Senthinathan, W. J. Dally*, A. Nguyen, R. Rathi, T. Greer, J. Poulton, J. Edmondson, J. Tran, Velio Communications Inc., Milipitas, CA and *Stanford University, Stanford, CA
Paper 5-4 - 11:20
A 10-Gb/s CMOS Clock and Data Recovery Circiut Using a Secondary Delay-Locked Loop, W. Rhee, H. Ainspan, S. Rylov, A. Rylyakov, M. Beakes, D. Friedman, S. Gowda and M. Soyuer, T.J. Watson Research Center, Yorktown Heights, NY
Session 6 – Modeling for RF Design
Sierra Ballroom, Monday Morning, September 22
Chair: Hong-Ha Vuong Co-Chair: Elliot Gould
This session discusses optimized design and the use of active and passive components for RF applications along with modeling methodology for harmonic/balance and spectral spreading.
Paper 6-1 - 10:05
MOSFET HF Distortion Behavior and Modeling for RF IC Design, T.-Y. Lee and Y. Cheng, Skyworks Solutions, Irvine, CA
Paper 6-2 - 10:30
Non-Linear Transmission Lines for Pulse Shaping in Silicon, E. Afshari and A. Hajimiri, California Institute of Technology, Pasadena, CA
Paper 6-3 - 10:55
Differentially-Shielded Monolithic Inductors, T.S.D. Cheung, J.R. Long*, K. Vaed**, R. Volant**, A. Chinthakindi**, C.M. Schnabel**, J. Florkey**, Z.X. He** and K. Stein**, University of Toronto, Ontario, Canada, *Delft University of Technology, The Netherlands and **IBM Microelectronics, Hopewell Ju
Paper 6-4 - 11:20
A Comparison of Non-Quasi-Static and Quasi-Static Harmonic Balance Implementations for Coupled Device and Circuit Simulation, Y. Hu and K. Mayaram, Oregon State University, Corvallis, OR
Paper 6-5 - 11:45
Analysis of Spectral Spreading in a Phase-Modulated System for 1.75-GHz GSM RF Transmitter Design, H. Shin, B. Walker, D. Pan, J. Dunworth and J. Jaffee, Qualcomm Inc., San Diego, CA
Paper 6-6 - 12:10
Statistical Analysis of Integrated Passive Delay Lines, B. Analui and A. Hajimiri, California Institute of Technology, Pasadena, CA