Monday, September
17 – Wednesday, September 19
Session 1 – Keynote Presentation
Oak Ballroom,
Monday Morning, September 17
8:15 am Welcome and Opening Remarks
Awards Presentations
Keynote Speaker Introduction
8:30 am Keynote Presentation
“The Wireless Revolution Continues:
Can Technology Keep Up with the Challenge?”
Dr. Bill Krenik, Chief Technical Officer for
The exploding market for consumer electronics is creating diverse product
opportunities, with many products demanding unique technology features to
enable successful performance, power-efficiency, size and cost. The wireless
market is a high-growth market, and a critical driver of technology
innovations. Whether creating a cutting-edge mobile phone with the hottest
features or a modest handset required for high-growth emerging economies, a
mobile designer is increasingly more challenged to satisfy product goals with
existing technology. From the perspective of the industry-leading semiconductor
provider entrenched in the wireless space, Bill Krenik,
Chief Technical Officer for TI’s Wireless Terminals
Business Unit, will address the critical technology, process and packaging
challenges and solutions required to meet mobile market requirements for today
and tomorrow.
Session 2 –3D and SiP
Oak Ballroom,
Monday Morning, September 17
Chair: Rakesh Patel
Co-Chair : Ann Rincon
Two invited papers on 3D wireless
high performance interchip communications using capacitive and inductive
interconnect techniques are presented.
In addition, resonant clocking in CMOS is explored for active jitter
deskewing.
10:00 am
Introduction
2.1
10:05 am
3D Capacitive Interconnections for High Speed
Interchip Communication (INVITED PAPER), R.
Canegallo, L. Ciccarelli, P.L. Rolandi, STMicroelectonics, A. Fazzi, L. Magagni, F. Natali, R. Guerrieri
University of Bologna, E. Jung, IZM Fraunhofer, L. Di Cioccio, CEA-LETI
A 3D Interconnection scheme based on capacitive coupling for high speed
chip to chip communication has been implemented in a 0.13 µm CMOS process. This work shows, with a synchronous
approach data transmission at 900MHz with electrodes 15x15 µm2 and energy
consumption of 41fJ/bit. With asynchronous approach we demonstrate with
electrodes 8x8 µm2 a propagation of clock at 1.7GHz and a propagation delay of
420ps for general purpose signal with energy consumption of 80fJ/bit.
2.2
10:55 am
Low-Jitter Active Deskewing Through Injection-Locked
Resonant Clocking, Z. Xu and K. Shepard,
Active deskewing is an important technique for managing variability in
clock distributions but introduces latency and power-supply-noise sensitivity
to the resulting networks. In this paper, we demonstrate how active deskewing
can be achieved with resonant distributions without introducing significant
jitter. The prototype network operates at a nominal 2-GHz frequency in a 0.18µm
CMOS technology with more than 25 pF/mm2 of clock loading.
2.3
11:20 am
Wideband Inductive-coupling Interface for High-performance
Portable System (INVITED PAPER), H. Ishikuro, N. Miura and T. Kuroda,
This paper presents a wideband, low power, and low cost pulse-based inductive-coupling
interface for wireless data transfer in high performance portable devices. General aspects of wireless links are
discussed to understand the position of inductive-coupling technique. Two applications of the inductive-coupling
links are introduced One is a 0.14pJ/b
inter-chip link for System-in-a-Package.
The other is a detachable wireless interface for chip monitoring through
LSI package. Circuit design techniques
for power reduction and an extension of communication range are presented.
Session 3 – Extreme SRAMs
Fir Ballroom, Monday Morning, September 17
Chair: Takashi Akioka
Co-Chair:
These papers explore state-of-the-art SRAMs as well as new structures and
analysis techniques to enable SRAM scaling into future technology generations.
10:00 am
Introduction
3.1
10:05 am
A 550ps Access-Time Compilable SRAM in 65nm CMOS
Technology, L.
Wissel, H. Pilo, C. LeBlanc, X. Wang, S. Lamphier and M. Fragano, IBM
A fixed-configuration custom SRAM macro with a highly-scalable
architecture was used as the basis for an ASIC SRAM compiler. The 256Kb
fixed-configuration uses dynamic circuitry [1] and other design techniques, and
has been demonstrated in silicon to have an access time of 550ps. The
compilable SRAM extends the column mux options, and can be compiled from 2Kb to
1.1Mb. Novel circuitry is used for efficient redundancy implementation in both
the row and column dimensions.
3.2
10:30 am
A Disturb Decoupled Column Select 8T SRAM Cell, V. Ramadurai, R.
Joshi and R. Kanj, IBM
This paper presents a novel 8T SRAM cell that provides a way to eliminate
the column select read disturb scenario. The 8T cell is then used in
conjunction with a sense-amp based architecure that minimizes read disturb to
selected cells. Fabricated hardware
resuls and simulation of this architecture show improvements of cell Vddmin
over traditional 6T cells by more than 150mV for 90nm PD/SOI technology.
3.3
10:55 am
Canary Replica Feedback for Near-DRV Standby VDD
Scaling in a 90nm SRAM, J.
Wang and B. Calhoun, University of Virginia
Canary bitcells act as monitors in a feedback architecture to sense the proximity
to the Data Retention Voltage (DRV) for SRAM bitcells during standby voltage
scaling. This approach implements aggressive standby VDD scaling by tracking
PVT variations and gives the flexibility to tradeoff between reliability and
leakage power savings. A 90nm SRAM test chip confirms the function of this
closed-loop approach. Power savings improve by up to 30x compared with the
conventional guard-banding approach.
3.4
11:20 am
Flex-Pass-Gate SRAM Design for Static Noise Margin
Enhancement Using FinFET-Based Technology, S. O'uchi, M. Masahara, K. Sakamoto, K.
Endo, Y.X. Liu, T. Matsukawa, T. Sekigawa, H. Koike and E. Suzuki, National
Insititute of AIST
We propose a flex-pass-gate SRAM (Flex-PG SRAM), i.e., a FinFET-based SRAM
to enhance both the read and write static noise margins (SNMs) independently.
The flip-flop in the Flex-PG SRAM consists of usual FinFETs while its pass
gates consist of double-“independent”-gate FinFETs, four-terminal-FinFETs. A
TCAD simulation revealed that the Flex-PG SRAM increases the read SNM by 70 mV
even when its 6-sigma tolerance is ensured, without the cell size penalty and
decrease in the write SNM.
3.5
11:45 am
Simple Statistical Analysis Techniques to Determine
Minimum Sense Amp Set Times, R. Houle, IBM
Simple statistical analysis techniques are described, involving a
relatively small number of actual circuit simulations, to accurately determine
the minimum required sense amp set time for memory designs. Techniques to
generate and evaluate the statistical distributions for signal development,
leakage and sense amp asymmetry are discussed with important implications to
sense amp design.
Session 4 – Compact Models for Advanced
CMOS Technologies
Pine Ballroom, Monday Morning, September 17
Chair: Brian Chen
Co-Chair :
Two invited papers present next-generation
compact models of advanced SOI and multiple gate MOSFETs, followed by a regular
paper on characterization and modeling of 65nm copper interconnect resistance.
10:00 am
Introduction
4.1
10:05 am
PSP-SOI: A Surface Potential Based Compact Model of
Partially Depleted SOI MOSFETs (INVITED PAPER), W.
Wu, X. Li, G. Gildenblat, Arizona State University, G. Workman, S.
Veeraraghavan, C. McAndrew, Freescale Semiconductor, R. van Langevelde,
Philips, G. Smit, D. Klaassen, A. Scholten NXP Semiconductors and J. Watts, IBM
This paper reports recent progress on partially depleted (PD) SOI modeling
using a surface potential based approach. The new model, called PSP-SOI, is formulated
within the framework of the latest industry standard bulk MOSFET model PSP. In
addition to its physics-based formulation and scalability inherited from PSP,
PSP-SOI captures SOI specific effects by including a floating body simulation
capability, a parasitic bipolar model, and self-heating. A nonlinear body
resistance is included for modeling body-contacted SOI devices. The PSP-SOI
model has been extensively tested on several PD/SOI technologies.
4.2
10:55 am
Charge-Based Compact Modeling of Multiple-Gate MOSFET
(INVITED PAPER), B.
Iniguez, A. Lazaro, H. Abd El Hamid, O. Moldovan, B. Nae, URV, J. Roig, LAAS
and D. Jimenez, UAB
We present new compact modeling techniques which have been applied for different
types of multiple-gate MOSFETs. Long channel models are obtained by deriving a
unified charge control model from the solution the 1-D Poisson’s equation.
Scalable models for the short-channel effects have been developed by solving
the 2-D or 3-D Poisson’s equation. We observed a very good agreement with
numerical simulations of the characteristics of different multiple-gate devices.
We also extended our compact models to the high frequency operation.
4.3
11:45 am
Characterization, Modeling and Extraction of Cu Wire
Resistance for 65 nm Technology, N.
Lu, M. Angyal, G. Matusiewicz, V. McGahay and T. Standaert, IBM
We present an innovative and comprehensive approach to characterize and
model interconnect resistance. We measured and analyzed Cu wire resistance data
for multiple wire widths on 10 BEOL levels at multiple temperatures and, with
SEM cross-section data, extracted all model parameters in IBM 65nm technology.
The extracted SPICE wire resistance model includes the congregated effects of surface
scattering, grain boundary scattering and surface roughness. New behavior of
wire resistance is reported for the first time.
Session 5 – Oversampling
A/D Converters
Cedar Ballroom, Monday Morning, September 17
Chair:
Co-Chair: Un-Ku Moon
This session highlights recent advances in
oversampling ADCs including dynamic range improvements for both bandpass and
lowpass modulators and improved tolerance for analog imperfections.
10:00 am
Introduction
5.1
10:05 am
A 63-mA 112/94-dB DR IF Bandpass Delta-Sigma Modulator
with Direct Feed-forward and Double Sampling, T. Yamamoto, M.
Kasahara and T. Matsuura, Renesas Technology Corp.
We developed a 10.7-MHz IF bandpass discrete-time 4th-order 4-bit
delta-sigma modulator for AM/FM car radio tuners. Using direct feed-forward and
double sampling, we have achieved a dynamic range (DR) of 112 dB in the 3-kHz
AM bandwidth (BW) and a DR of 94 dB in the 200-kHz FM BW. The modulator
occupies 3 mm2, in 0.15 µm CMOS technology, and draws 63 mA of
current.
5.2
10:30 am
A Delta-Sigma Modulator with a Widely Programmable
Center Frequency and 82-dB Peak SNDR, K. Yamamoto, A. Chan Carusone and F. Dawson,
A 4-bit fourth-order delta-sigma modulator with a widely programmable
center frequency is presented. Novel methods for quantizing and implementing
the digitally programmable modulator coefficients enable performance comparable
to state-of-the-art discrete-time fixed-frequency modulators at any center frequency
from dc to 0.31fs in steps of 0.0052fs. The 0.18-µm 1.8-V CMOS prototype
consumes 115 mW at a sampling frequency of 40 MHz. The peak SNDR and SNR over a
310-kHz bandwidth are 82 dB and 86 dB respectively.
5.3
10:55 am
A 94dB SFDR 78dB DR 2.2MHz BW Multi-bit Delta-Sigma
Modulator with Noise Shaping DAC, J.
Chen and Y.P. Xu, National University of Singapore
A 5th-order multi-bit lowpass delta-sigma modulator employs a proposed
noise shaping dynamic element matching (NSDEM) technique to remove DAC
non-linearity error. Unlike most existing DEMs trading SNR for SFDR, the
proposed technique improves both SFDR and SNR. The noise shaping is
incorporated in the first integrator of the loop filter without any additional
analog circuitry. The fabricated modulator chip achieves 94dB SFDR and 78dB DR
in 2.2MHz BW and meets the ADSL2+ specifications.
5.4
11:20 am
A 18mW CT Sigma-Delta Modulator with 25MHz Bandwidth
for Next Generation Wireless Applications, X.
Chen, Y. Wang, G. Temes, Oregon State University, Y. Fujimoto, P. Lo Ré, Y.
Kanazawa, Sharp Corp., J. Steensgaard, Esion LLC
The design of a wideband low-power continuous-time (CT) Delta-Sigma
modulator is presented in this paper. A modified feed-forward architecture is
proposed to realize the low-power loop filter as well as cancel the out-of-band
peaking in the signal transfer function. Several high-speed low-power design
techniques are used in the circuits. The modulator achieves 60 dB dynamic range
(DR) within 20 MHz signal bandwidth, and 55 dB DR within 25 MHz signal
bandwidth. Clocked at 400 MHz, the modulator consumes only 10 mA current from a
1.8 V supply.
5.5
11:45 am
Multi-Bit Sigma Delta ADC with Reduced Feedback Levels,
Extended
A novel second order sigma delta modulator (SDM) with 5-bit quantizer has
been proposed with simplified DAC
arrays, high-order truncation noise shaping for increased tolerance to analog
imperfections, and extended dynamic range for a maximum input signal swing of
up to -0.45dBFS. With truncation filter
and pseudo SDM in the DSP, the truncation and saturation errors are compensated
through the DAC arrays and the DSP. The
design was fabricated in 0.18µ Dual Gate Oxide (DGO) process. A SNDR (Signal-to-Noise-and–Distortion Ratio)
of 98.4 dB and a SNR (Signal-to-Noise Ratio) of 108-dB were measured for a 31.25-KHz
signal bandwidth at 8-MHz sampling frequency with a power consumption of about
14.7 mW.