Custom Integrated Circuits Conference

On Monday afternoon, September 17, CICC will offer a Panel Discussion titled: Are analog designers hopeless at scaling? Will digital designers eat their lunch at 45nm and below? Session 10 - Panel Discussion Oak Ballroom, Monday Afternoon, September 17 4:00 pm - 5:30 pm Organizer: Sudhir Aggarwal Panel Moderator: Colin McAndrew Panelists: Prof. Boris Murmann, Stanford University Dr. Marcel Pelgrom, NXP Semiconductor, Europe Prof. B.E. Boser, University of California, Berkeley Dr. Ian Young, Intel Prof. P. Kinget, Columbia University Dr. Bill Krenik, Texas Instruments Three decades of relentless device scaling have resulted in reduction of the MOS transistor length to 45nm. Even shorter channel lengths can be expected over the coming years. Scaling has provided consistent improvements in digital circuit density and performance. However, analog circuit implementations have not been as successful in exploiting scaling for achieving improvement in performance or density. This raises a question as to what are the factors limiting analog circuits scaling. Is it limited by the nature of analog signal processing requirements? Or it may be that analog designers are hopeless at scaling. Can analog circuits benefit from digital system integration at and below 45nm? A panel consisting of experts will deliberate on the possible trends while providing insight into issues of analog scaling.