Phase-locked loops (PLLs) are essential building blocks in all digital, analog, and radio-frequency integrated circuits (ICs). The noise, power, and area of PLLs determine many of the key performance parameters in all such ICs. This tutorial describes the fundamental principles and concepts of PLL design. After reviewing the operation of a simple type-1 PLL and the characteristics of its building blocks, the operating and design principles of a charge-pump PLL will be discussed in detail. Phase noise analysis using a small-signal model will be described and noise-bandwidth-power tradeoffs will be presented. Existing and emerging techniques to alleviate these tradeoffs will be briefly discussed.

This lecture provides design techniques for advanced analog PLLs. It builds on the previous lecture by further explaining the key properties of the charge pump PLL that have made it so attractive as the topology of choice. Possible alternatives to achieve a less design intensive implementation while still obtaining the required performance will be examined. More advanced design possibilities such as high gain phase detectors, sampled and switched resistor loop filter topologies, and switched capacitor frequency acquisition circuits will be presented. The talk will conclude by showing results from a recent example that utilizes these concepts to achieve a low power and area PLL implementation targeted to a MEMS-based oscillator circuit.

This lecture provides an explanation of the fractional-N PLL as an extension of the integer-N PLL. It builds on previous lectures by explaining the additional ideas and issues associated with fractional-N PLLs relative to integer-N PLLs. Topics include a self-contained overview of delta-sigma modulation, tradeoffs associated with quantization noise shaping order and PLL bandwidth, non-ideal effects of particular concern in fractional-N PLLs, spurious tone generation mechanisms and mitigation techniques, and recently developed techniques to enhance fractional-N PLL performance. Many of the concepts are presented in the context of fractional- N PLL CMOS IC case studies supported by measurement results.

Traditional PLL techniques using a charge-pump PLL require a design flow and circuit techniques, which are quite analog and area intensive. At times, high performance analog PLL designs utilize process technologies that are either incompatible with the bulk digital processor and memory circuits, or simply do not allow for aggressive area/power scaling as the process nodes continue to shrink. This tutorial explains the design concepts of a digitally controlled oscillator (DCO)-based all-digital phase locked loop (ADPLL) architecture for frequency synthesis in wireless RF applications. Techniques to avoid analog tuning, to achieve fine frequency resolution, seamless integration of ripple cancellation, wider modulation bandwidths, faster settling time using gear-shifting, and compensation of analog-digital inter-conversion imperfections through digital signal processing means will be presented. The tutorial will conclude with a description of multiple generations of ADPLL architectures.