We will present a unified view of wireless receivers and transmitters, from the perspective of bandpass signal processing. This brings to light the strengths and limitations of a particular architecture, and allows the circuit designer to specify the components for a successful realization. Moving beyond classic architectures such as time-continuous single and dual conversion, we will discuss the recent use of discrete-time signal processing in both wireless receivers and transmitters. This makes it possible to develop flexible architectures that can adapt to various modulations and channel bandwidths, and thus enable the long-held vision of a software-defined radio.

The front end of every modern receiver consists of an LNA and mixer. The gain, distortion and noise of these two blocks collectively determine many of the key performance parameters of the entire receiver. This short course will begin with an examination of noise models for passive elements and for MOSFETs. The implications of these models for amplifier noise performance will be studied next, in the context of the IEEE standard representation of noisy two-ports. The impedance-matching conditions for optimum noise will be understood to conflict generally for those that maximize power gain. Further tradeoffs with distortion and power consumption will be studied as well, for both narrowband and broadband topologies. The noise performance of mixers may be understood with the same fundamentals as for amplifiers, with the addition of some knowledge of time-varying system behavior. Representative mixer topologies will be examined for their noise, conversion gain and linearity performance. The properties and limitations of the Jones/Gilbert mixer will be contrasted with those of voltage-mode switching mixers, with a focus on how best to accommodate process scaling trends.

Despite dramatic advances in device speed, RF synthesizer design continues to present interesting challenges. This tutorial describes the principles of phase-locked synthesizer design for RF transceivers. Following a review of properties and limitations of charge-pump phase-locked loops, we analyze the sources of phase noise and sidebands in a PLL environment. Next, we deal with integer-N synthesizers and present various methods of alleviating the trade-off between the loop bandwidth and the output sideband level. We then describe fractional-N synthesizers and various noise-shaping techniques that minimize the output phase noise while providing a wideband loop. Last, we consider a number of hybrid synthesizer architectures.

Power amplifiers are one of the most challenging of all RF building blocks. They operate at close to the fundamental limits of the semiconductor technology, but must also maintain outstanding linearity. Their dc power consumption is often the limiting factor in battery life for mobile devices. The tutorial later addresses the evolution of power amplifier architectures, as well as the design of power amplifier building blocks and challenges for monolithic integration with other RF functions.