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Technical
Program
Educational Sessions
Keynote Address
Conference Luncheon
Panel Discussions


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Following is the 2007 Educational Session Program
EDUCATIONAL SESSIONS
Sunday, September 16
Chairperson: Laurence Nagel, Omega Enterprises
Educational Session 1
Mixed-Signal SOC Design Methodology
Oak Ballroom, Sunday, September 16
Organizer: Laurence Nagel, Omega Enterprises
Co-Organizer: Henry Chang, Designer’s Guide Consulting
8:00 am - 9:50 am
E1-1 Top-down Design Methodology
Scott Shelton, Cadence Analog Design Services
Mixed-signal design at the SOC level necessitates a top-down mixed signal design methodology to meet today's project schedules
with successful end products. This technical discussion examines methods for successfully handling the analog and digital domain
interactions in large complex ICs with today's tools; crafting and executing a simulation strategy which efficiently verifies functionality
and performance; and efficiently modeling at appropriate levels of abstraction. The discussion is presented within the context of actual
designs by some of Cadence's internal design teams, and examines how they have shaped and melded the methodologies as presented.
Given the diverse skill sets and multiple IP vendors garnered for SOCs, the structure and management of these design teams throughout the
various project stages is explored as well. The session covers these topics through the complete design cycle, from project kickoff to IP block
delivery for integration or SOC tapeout.
10:00 am - 12:00 pm
E1-2 High-Performance Energy-Efficient Digital Design Technologies for Nanoscale SOC
Ram Krishnamurthy, Intel
This presentation examines some of the prominent barriers to high-performance and energy-efficient digital design in the
sub-65nm CMOS regime and outlines new paradigm shifts necessary for next-generation SOC digital design and methodologies.
Emerging trends in SOC industry including special-purpose multimedia/communication accelerators, networks-on-chip, co-processor
arrays, and reconfigurable DSP and their associated power-performance trade-offs are reviewed. Energy-efficient data-path and interconnect
circuit techniques, variation-tolerant design methods, static/dynamic supply scaling, ultra-low-voltage circuits, and multi-supply/multi-threshold
design and supply gating methodologies for switching and leakage energy reduction are described. Special purpose hardware accelerators
and SOC building blocks for enabling high performance-per-Watt on specialized DSP tasks such as encryption and media processing are
presented. Many chip design examples and their results will be discussed as part of this presentation.
1:00 pm - 2:50 pm
E1-3 Top-down Design of RF Transceivers using VHDL
Bogdan Staszewski and Khurram Waheed, Texas Instruments
RF transceivers comprise a particularly difficult challenge in SOC design because their proper operation requires correct
interoperability of RF subsystems, analog subsystems, and digital subsystems. This presentation describes the numerous challenges
in the top-down design of a RF transceiver SOC and describes how VHDL simulation is in the design flow. Case studies of RF transceiver
chips designed at Texas Instruments are used to illustrate how the design challenges were overcome to produce working SOCs.
3:10 pm - 5:00 pm
E1-4 Analog Verification
Ken Kundert, Designer’s Guide Consulting
Verification is becoming recognized as one of the most important issues when designing large analog circuits, and as a result design
methodologies are starting to change. This change mirrors a change that occurred in digital design 10-15 years ago. In this presentation I
will show why the problem has become so significant, and what people are doing to control the problem.
Educational Session 2
High-Speed Serial I/O Design Techniques
Fir Ballroom, Sunday, September 16
Organizer: Ramesh Harjani, University of Minnesota
Co-Organizer: Gordon Roberts, McGill University
8:00 am - 9:30 am
E2-1 Introduction to High-speed I/O
Randy Mooney, Intel
I'll discuss the constraints of the design space for microprocessor platforms, then take a look at the state of the technologies
required to deliver bandwidth in these platforms. These technologies include analysis tools, interconnect components, modulation
and equalization choices that fit the constraints, and the various circuits required in silicon. I'll then take a look at future platform
requirements, and the potential solution space to meet those needs.
9:30 am - 11:00 am
E2-2 Introduction to Signal Integrity
Bob Sainati, 3M
The demand for ever increasing data rates in today’s electronic systems requires the use of shorter rise time signals and faster clock
speeds. Both data and clock signals are conveyed using interconnects to carry signals on-chip, on a multilayer pc board, through backplanes
or via cables. This tutorial focuses on the impact of interconnects on high speed digital signals. Here the term interconnect refers not only to
signal traces but packaging, connectors, vias, etc. Shorter rise times, of course, imply wider frequency bandwidths. Many traditional
interconnect design techniques focus on factors such as routing efficiency, mechanical and thermal issues. Because of this, many
interconnect schemes lack the bandwidth necessary to distribute high speed signals faithfully. Likewise faster rise times increase the
probability of significant crosstalk between multiple nets. Similar issues exist with power distribution networks. Short rise time signals
can require the supplying of large amounts of current within a very short time. Improper design of power distribution networks can create
distortion producing supply voltage drops. Finally, the higher frequencies of short rise time signals are much more easily radiated thus
resulting in potential EMI/EMC problems.
Techniques such as the use of microwave measurement techniques (e.g., network analyzers), transmission line theory, microwave
scattering parameter analysis and electromagnetic simulators have been adopted in order to design improved interconnects and power
distribution networks. These techniques all have at least some basis in electromagnetic theory, that is, Maxwell’s equations. Although it is
common to think of digital signals in terms of voltages and currents, ultimately they are a set of (coupled) electric and magnetic fields
surrounding the metallization of signal traces, connector and package pins, via metallization, etc. Many of the issues associated with signal
integrity are a result of the finite velocity of the fields when guided by traces, the propensity of fields to locally store energy in regions where
abrupt changes in geometry, direction, etc. are encountered and the fact that crosstalk and radiation increase because a fixed physical size
becomes electrically larger as the wavelength decreases. The intent of this course is to link the physics of electromagnetic fields to the signal
behavior observed on an interconnect. For instance, quantities such as inductance and capacitance are fundamentally described in terms of
fields. Also guided electromagnetic waves are the foundation of transmission line theory and scattering parameters. This course will not be a
detailed exposition of electromagnetic theory but rather a review of concepts and an application of them to high speed digital signal
interconnect behavior.
11:00 am - 12:00 pm and 1:00 pm - 2:00 pm
E2-3 Jitter Analysis
Mike Li, Wavecrest
In this tutorial presentation, we will first review where the technology is heading to for the multiple Gbps high-speed links
and I/O buses for devices and systems in networks and computers. Second, we will discuss why jitter and signal integrity have
become the major challenges, as well as limiting factors for developing those high-speed, high performance, and more increasingly, high
volume link devices and systems. Third, we will discuss the jitter and signal integrity modeling, simulation, verification and characterization
methodologies for jitter and signal integrity within the context of a serial link. We will cover these ever evolving cutting edge topics from
generic perspective, as well as practical application perspective, with real-world examples from multiple Gbps link technologies of PCI Express,
FB DIMM, and Serial ATA in computer I/Os, and Fibre Channel and Gigabit Ethernet in networks.
2:00 pm - 3:30 pm
E2-4 Circuit/System Aspects of I/O Equalization
Vladimir Stojanovic, Massachusetts Institute of Technology
Today’s high-speed interfaces are limited by the bandwidth of the communication channel, tight power constraints and noise sources
that differ from those in standard communication systems. The wire bandwidth limitations make straight circuit solutions inefficient, and the
power and area constraints make standard digital communication approaches infeasible. Efficient solutions require bridging the fields of digital
communications, optimization, statistical and dynamic system modeling, with system architecture, mixed-signal and digital circuit design.
This tutorial covers the circuit and system design of equalized high-speed I/Os. We start by introducing the basics of channel properties,
modeling, measurements, and communications techniques. We then focus on different link equalization techniques, comparing them both from
system perspective and from the performance of resulting circuit implementations. Some examples will cover trade-offs between transmit
pre-emphasis and decision-feedback equalization, linear analog receiver equalization as well as joint modulation/equalization and
equalization/coding techniques (like PAM4, duobinary and multitone signaling). Implementations of transmitter FIR equalizers, several
DFE receiver topologies and peaking amplifiers will be discussed in detail. Several adaptive techniques for equalizer tuning and link monitoring
will also be presented.
3:30 pm - 5:00 pm
E2-5 Clocking and CDRs
Jafar Savoj – Rambus
High-purity clock generation enables longer reach in wired communication systems. Optical and copper standards set an upper bound
on the noise and distortion that can be added to the signal at the source. This tutorial describes means of efficient clock generation and
distribution in high-performance chips to satisfy requirements imposed by the standards. Clock and data recovery (CDR) circuits are an
integral part of wired communication systems. With the accelerated rate of device scaling in recent decades, CDR architectures have
transitioned from fully analog into mixed-mode and digital implementations. The tutorial later addresses the evolution of CDR architectures,
as well as the design of its building blocks.
Educational Session 3
Low Power Embedded ADC Design
Pine Ballroom, Sunday, September 16
Organizer: Sang-Soo Lee, Pixelplus
Co-Organizer: Shahriar Mirabbasi, University of British Columbia
8:00 am - 9:50 am
E3-1 System Aspects
Thomas Cho, Marvell
Aggressive CMOS scaling in the last couple of decades has enabled powerful DSP engines for many digital communication systems
in both wireless and wired-line applications. But the world is still analog, and the requirements for the analog-to-digital interface circuits are
becoming increasingly stringent not to limit the overall system performance. In addition, A/D converters, which used to be discrete
components on the board in the past, are now being integrated onto an IC together with many other functions for smaller form factors,
bringing new challenges to analog circuit designers. This tutorial will give an overview of both circuit and system level requirements for the
embedded A/D converters used in various wireless/wired-line applications. Practical considerations for system-on-chip environments, such
as on-chip reference generation, noise isolation, low-power/low-voltage designs, testing, and other challenges will also be discussed.
10:10 am - 12:00 pm
E3-2 Pipeline ADC Design
Boris Murmann, Stanford University
Pipelined analog-to-digital converters have evolved as a popular architecture for broadband quantization in applications requiring
8-14 bit resolution and sampling rates up to several hundred MS/s. This lecture discusses the design and implementation
of pipelined ADCs using a top-down approach, ranging from an architecture level analysis to transistor level implementation details.
Specific topics include: (1) Basic operation principle, (2) Redundancy and digital calibration techniques, (3) Error and noise budgeting;
pipeline stage scaling and choice of per-stage resolution, (4) Transistor level circuit implementation; low power techniques such as OTA
sharing and SHA-less front-ends, and (5) Performance survey; recent trends and developments in research.
1:00 pm - 2:50 pm
E3-3 Sigma Delta ADC
Katelijn Vleugels, H-Stream Wireless
In this talk, we will look at the various aspects of Sigma-Delta Analog-to-Digital Converter (ADC) design. We begin with a review
of the basic concepts of Sigma-Delta data converters, followed by an overview of state-of-the art Sigma-Delta ADC implementations. Several
architectures exist, and the optimal architecture heavily depends on the system requirements imposed by the application. The advantages
and challenges of various architectures are discussed next. We then look at the impact of circuit implementation non-idealities on the overall
ADC performance. The talk will conclude with an example of a Sigma-Delta ADC design.
3:10 pm - 5:00 pm
E3-4 Case Study
Stacy Ho, Analog Device
This talk will present case studies on embedded ADC design for mobile handsets. Factors that influence the selection of ADC
architecture, such as power dissipation, wireless standards requirements, and cost, will be discussed. Issues due to the system level
integration of ADCs will be addressed, such as: coexistence with digital baseband and power management blocks, architectural tradeoffs,
reference and clock requirements. The talk will also review published embedded ADCs for wireless applications.
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