I'll discuss the constraints of the design space for microprocessor platforms, then take a look at the state of the technologies required to deliver bandwidth in these platforms. These technologies include analysis tools, interconnect components, modulation and equalization choices that fit the constraints, and the various circuits required in silicon. I'll then take a look at future platform requirements, and the potential solution space to meet those needs.

The demand for ever increasing data rates in today’s electronic systems requires the use of shorter rise time signals and faster clock speeds. Both data and clock signals are conveyed using interconnects to carry signals on-chip, on a multilayer pc board, through backplanes or via cables. This tutorial focuses on the impact of interconnects on high speed digital signals. Here the term interconnect refers not only to signal traces but packaging, connectors, vias, etc. Shorter rise times, of course, imply wider frequency bandwidths. Many traditional interconnect design techniques focus on factors such as routing efficiency, mechanical and thermal issues. Because of this, many interconnect schemes lack the bandwidth necessary to distribute high speed signals faithfully. Likewise faster rise times increase the probability of significant crosstalk between multiple nets. Similar issues exist with power distribution networks. Short rise time signals can require the supplying of large amounts of current within a very short time. Improper design of power distribution networks can create distortion producing supply voltage drops. Finally, the higher frequencies of short rise time signals are much more easily radiated thus resulting in potential EMI/EMC problems.

Techniques such as the use of microwave measurement techniques (e.g., network analyzers), transmission line theory, microwave scattering parameter analysis and electromagnetic simulators have been adopted in order to design improved interconnects and power distribution networks. These techniques all have at least some basis in electromagnetic theory, that is, Maxwell’s equations. Although it is common to think of digital signals in terms of voltages and currents, ultimately they are a set of (coupled) electric and magnetic fields surrounding the metallization of signal traces, connector and package pins, via metallization, etc. Many of the issues associated with signal integrity are a result of the finite velocity of the fields when guided by traces, the propensity of fields to locally store energy in regions where abrupt changes in geometry, direction, etc. are encountered and the fact that crosstalk and radiation increase because a fixed physical size becomes electrically larger as the wavelength decreases. The intent of this course is to link the physics of electromagnetic fields to the signal behavior observed on an interconnect. For instance, quantities such as inductance and capacitance are fundamentally described in terms of fields. Also guided electromagnetic waves are the foundation of transmission line theory and scattering parameters. This course will not be a detailed exposition of electromagnetic theory but rather a review of concepts and an application of them to high speed digital signal interconnect behavior.

In this tutorial presentation, we will first review where the technology is heading to for the multiple Gbps high-speed links and I/O buses for devices and systems in networks and computers. Second, we will discuss why jitter and signal integrity have become the major challenges, as well as limiting factors for developing those high-speed, high performance, and more increasingly, high volume link devices and systems. Third, we will discuss the jitter and signal integrity modeling, simulation, verification and characterization methodologies for jitter and signal integrity within the context of a serial link. We will cover these ever evolving cutting edge topics from generic perspective, as well as practical application perspective, with real-world examples from multiple Gbps link technologies of PCI Express, FB DIMM, and Serial ATA in computer I/Os, and Fibre Channel and Gigabit Ethernet in networks.

Today’s high-speed interfaces are limited by the bandwidth of the communication channel, tight power constraints and noise sources that differ from those in standard communication systems. The wire bandwidth limitations make straight circuit solutions inefficient, and the power and area constraints make standard digital communication approaches infeasible. Efficient solutions require bridging the fields of digital communications, optimization, statistical and dynamic system modeling, with system architecture, mixed-signal and digital circuit design.

This tutorial covers the circuit and system design of equalized high-speed I/Os. We start by introducing the basics of channel properties, modeling, measurements, and communications techniques. We then focus on different link equalization techniques, comparing them both from system perspective and from the performance of resulting circuit implementations. Some examples will cover trade-offs between transmit pre-emphasis and decision-feedback equalization, linear analog receiver equalization as well as joint modulation/equalization and equalization/coding techniques (like PAM4, duobinary and multitone signaling). Implementations of transmitter FIR equalizers, several DFE receiver topologies and peaking amplifiers will be discussed in detail. Several adaptive techniques for equalizer tuning and link monitoring will also be presented.

High-purity clock generation enables longer reach in wired communication systems. Optical and copper standards set an upper bound on the noise and distortion that can be added to the signal at the source. This tutorial describes means of efficient clock generation and distribution in high-performance chips to satisfy requirements imposed by the standards. Clock and data recovery (CDR) circuits are an integral part of wired communication systems. With the accelerated rate of device scaling in recent decades, CDR architectures have transitioned from fully analog into mixed-mode and digital implementations. The tutorial later addresses the evolution of CDR architectures, as well as the design of its building blocks.