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Session 22 - Wireless Networking
Chairman: Earl McCune
Co-Chairman: Andrea Boni
This session addresses practical issues including an invited paper on
ESD design for RF integrated circuits. Additional topics include LNA,
signal generation, and demodulation.
1:30pm - Introduction
22.1 - 1:35pm
ESD Protection Design for RF Integrated Circuits: New Challenges
(Invited)
A.Z. Wang, H.G. Feng, R.Y. Zhan, G. Chen and Q. Wu, Illinois Institute
of Technology, Chicago, IL
Abstract :
The challenge in RF ESD protection circuit design, still a problem in
definition, is to address the complex interactions between the ESD
protection network and the circuit being protected in both directions.
This paper discusses related key factors, e.g., switching and accidental
triggering of ESD protection networks, as well as ESD-induced parasitic
capacitive, resistive, noise coupling and self- generated noise effects.
Evaluation techniques include s-parameter, Q-factor and overall
specification examination. Low-parasitic compact structures are the
solutions to RF ESD protection.
22.2 - 2:25pm
A 1V 0.9dB NF Low Noise Amplifier for 5-6GHz WLAN in 0.18um CMOS
D. Cassan and J. Long, University of Toronto, Toronto, ON, Canada
Abstract :
A low-noise amplifier employing transformer feedback for 5-6GHz WLAN
applications operates from a 1V supply and achieves a measured gain of
14.2dB, noise figure (NF) of 0.9dB, and IIP3 of +0.9dBm, while consuming
16mW. We benchmark the feedback design to a cascode topology fabricated
in the same technology that realizes 14.1dB gain, 1.8dB NF, and IIP3 of
+4.2dBm while dissipating 21.6mW at 1.8V. Both designs are
fully-differential and are implemented in 0.18um CMOS.
22.3 - 2:50pm
A Low-Voltage Multi-GHz VCO with 58% Tuning Range in SOI CMOS
N. Fong, J.-O. Plouchart*, N. Zamdmer**, D. Liu*, L. Wagner**, C. Plett
and G. Tarr, Carleton University, Ottawa, ON, Canada, *IBM T.J. Watson
Research Center, Yorktown Heights, NY and **IBM Microelectronics SRDC,
Hopewell Junction, NY
Abstract :
The low-voltage 3.0-5.6GHz VCO in SOI CMOS features single-loop copper
inductor and band-switching accumulation MOS varactors. This results in
a good phase noise of -120dBc/Hz at 3.0GHz and -114.5dBc/Hz at 5.6 GHz
at 1V VDD, and a wide tuning range of 58.7%. At 0.83V VDD, the VCO
dissipates less than 1mW at 5.6GHz.
22.4 - 3:30pm
A 1.8GHz CMOS Fractional-N Frequency Synthesizer with Randomized
Multi-Phase VCO
C.-H. Heng and B.-S. Song*, University of Illinois, Urbana, IL and
*University of California, San Diego, La Jolla, CA
Abstract :
A synthesizer in 0.6um CMOS with multi-phase VCO exhibits no spurs
resulting from interpolated phase mismatch errors. Phase noise measured
at 1.715GHz is lower than -80dBc within 20kHz loop bandwidth and -118dBc
at 1MHz offset with fractional spur below -70dBc. The chip consumes
140mW at 3.3V and occupies 3.7mmx4.6mm.
22.5 - 3:55pm
A 2MHz GFSK IQ Receiver for Bluetooth with DC-Tolerant Bit Slicer
B.-S. Song, T. Cho*, D. Kang* and S. Dow*, University of California, San
Diego, La Jolla, CA and *Wireless Interface Technologies, Inc., San
Diego, CA
Abstract :
An IQ processor in 0.18u CMOS implements Bluetooth low-IF functions at
2MHz with 7th-order complex Bessel bandpass IF filter, limiter,
quadricorrelator baseband FM demodulator, and differential slope sensing
bit slicer. The sensitivity is -46dBm at 0.1% BER. The chip consumes
50mW at 1.8V and occupies 2mm x 2.8mm.
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Session 23 - Nyquist Converters and Techniques
Chairman: David Nairn
Co-Chairman: Richard Carley
Four papers cover state-of-the-art ADCs for low-voltage performance. In
addition, two papers address mismatch issues and one discusses bandgap
performance.
1:30pm - Introduction
23.1 - 1:35pm
A 1.8V Fully Embedded 10b 160MS/s Two-Step ADC in 0.18um CMOS
M. Clara, A. Weisbauer and F. Kuttner, Infineon Technologies AG,
Villach, Austria
Abstract :
A two-step ADC with interleaved fine conversion achieves 9.1 effective
bits with a sampling frequency of 160MHz. The effective resolution
exceeds 8.5 bits for signal frequencies up to 66MHz. The 10 bit
converter with on-chip driver and reference measures only 1mm2 in a
standard 0.18um CMOS process and consumes 190mW from a single 1.8V
supply. The fully embedded design is targeted at SoC-integration.
23.2 - 2:00pm
A 2.5V 10b 120 MSample/s CMOS Pipelined ADC with High SFDR
S.-M. Yoo, T.-H. Oh, J.-W. Moon, S.-H. Lee and U.-K. Moon*, Sogang
University, Seoul, Korea and *Oregon State University, Corvallis, OR
Abstract :
A 10b multibit-per-stage pipelined ADC incorporating merged-capacitor
switching (MCS) technique achieves better than 53 dB SNDR at 120
MSample/s and 54 dB SNDR and 68 dB SFDR for input frequencies up to
Nyquist at 100 MSample/s. The measured DNL and INL are ±0.40 LSB
and ±0.48 LSB, respectively. The ADC fabricated in a 0.25um CMOS
occupies 3.6 mm2 active die area and consumes 208 mW under a 2.5V power
supply.
23.3 - 2:25pm
A 8-bit 200 MS/s Interpolating/Averaging CMOS A/D Converter
J. Vandenbussche, K. Uyttenhove, E. Lauwers, M. Steyaert and G. Gielen,
Katholieke Universiteit Leuven, Heverlee, Belgium
Abstract :
A 8-bit 200MS/s 4-2 interpolating A/D converter is presented. A novel
input stage was developed to enhance the dynamic performance. Static
performance is enhanced using the averaging technique. The chip has
been fabricated in a standard 0.35 um CMOS process. An INL/DNL of
0.95/0.8 LSB was measured. An SNR figure of 44.3 dB was achieved at low
frequencies; for a 30 MHz input signal an SNR figure of 43 dB was
measured.
23.4 - 2:50pm
Understanding MOSFET Mismatch for Analog Design
P.G. Drennan and C.C. McAndrew, Motorola, Inc., Tempe, AZ
Abstract :
This paper addresses misconceptions about MOSFET mismatch for analog
design. Vt mismatch does not follow a simplistic 1/sqrt(area) law.
Further, Vt and gain factor are not appropriate parameters for modeling
mismatch. A physically based mismatch model can be used to obtain
dramatic improvements in prediction of mismatch. This model is applied
to MOSFET current mirrors to show some non-obvious effects over bias,
geometry, and multiple units devices.
23.5 - 3:30pm
Spatial Averaging and Ordering in Matched Element Arrays
K. Krishna, W. Bright, D. Dye*, K. Muhammad and Y. Hu, Texas
Instruments, Inc., Dallas, TX and *Database Drafting, Inc., Dallas, TX
Abstract :
Spatial gradients often limit the matching accuracy of element arrays in
ADC's and DAC's. We cast the problem of spatial gradients formally and
present a global optimization-based solution that does not require the
gradients to be pre-characterized precisely or limit them to being
linear/quadratic. Si results from a standalone BiCMOS DAC and a CMOS
DAC, part of the industry's first DOCSIS certified cable modem solution,
are presented.
23.6 - 3:55pm
A 2-V 23-uA 5.3-ppm/°C 4th-Order Curvature-Compensated CMOS Bandgap
Reference
K. Leung, P. Mok and C. Leung, The Hong Kong University of Science and
Technology, Hong Kong, China
Abstract :
A 4th-order curvature-compensated CMOS bandgap reference, which uses
high-resistive poly resistor to generate temperature- dependent resistor
ratio, is proposed. The proposed reference can operate down to a 2-V
supply and consumes a maximum supply current of 23uA. A tempco of 5.3
ppm/°C and a line regulation of ±1.25 mV/V are achieved at
2-V supply. The improvement on tempco is about 5 times reduction
compared to the conventional approach.
23.7 - 4:20pm
Low-Voltage Pipelined ADC Using Opamp-Reset Switching Technique
D.-Y. Chang, L. Wu* and U.-K. Moon, Oregon State University, Corvallis,
OR and *Marvell, Sunnyvale, CA
Abstract :
A low-voltage opamp-reset switching technique (ORST) which avoids clock
boosting/ bootstrapping, switched-opamp, and threshold voltage scaling
is presented. The switching technique is applied to the design of a
10-bit 25MSPS pipelined ADC. The prototype ADC demonstrates 55dB SNR,
55dB SFDR, 48dB SNDR at 1.4V power supply. The ADC operated down to 1.3V
power supply (|VTP|=0.9V) with 5dB degradation in performance. Maximum
operating frequency is 32MSPS. The ORST is fully compatible with future
low-voltage submicron CMOS processes.
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Session 24 - Directions in Process and Integration
Chairman: David Sunderland
Co-Chairman: Rich Liu
This session presents papers related to strategic directions in
semiconductor process technology and integration, including challenges
of and alternatives to CMOS scaling. Circuit designers will find these
tutorials valuable in planning future products.
1:30pm - Introduction
24.1 - 1:35pm
Technology Trends and Challenges for CMOS/System LSIs for the Next 10-15
Years (Invited)
S. Kawamura, Advanced Semiconductor Research Center, Tsukuba, Japan
Abstract :
There are a lot of challenges which we will be facing in the next 10 to
15 years in developing a state-of-the-art CMOS technology for system
LSIs. Among them, lithography, gate-stack, shallow junction and
interconnect technologies are major ones. In this paper, these major
challenges as well as "Design Crisis" and "Power Crisis" are discussed
in detail from an ITRS perspective, and some potential solutions are
described to overcome these challenges and crises.
24.2 - 2:25pm
Application-Dependent Scaling Tradeoffs and Optimization in the SoC Era
C. Diaz, M.-C. Chang, T. Ong and J. Sun, TSMC, Taiwan, ROC
Abstract :
Several physical phenomena in highly scaled CMOS technology have now
become first order elements affecting electrical behavior of transistor
characteristics. Effects such as STI mechanical stress, direct tunneling
in gate dielectrics, gate line-edge roughness, and others, have
significant influence on device characteristics. This paper elaborates
on these effects to exemplify the need for closer interaction between
circuit design and process development teams in order to push out
application-dependent scaling limits. The paper also highlights the need
for further efforts in the areas of circuit-level device modeling.
24.3 - 2:50pm
Modularized Low Temperature LNO/PZT/LNO Ferroelectric
Capacitor-Over-Interconnect (COI) FeRAM for Advanced SOC (ASOC)
Application
S. Lung, D. Lin, S. Chen, G. Weng, C. Liu*, S. Lai, C. Tsai, T. Wu* and
R. Liu, Macronix International, Hsinchu, Taiwan, ROC and *National
Tsing-Hua University, Hsinchu, Taiwan, ROC
Abstract :
Embedded FeRAM module is achieved by a low temperature
capacitor-over-interconnect (COI) process. A conductive perovskite
LaNiO3 (LNO) bottom electrode is used as seed layer, the crystallization
temperature of in-situ sputter deposited PZT is greatly reduced from
600°C to 350°C-400°C. LNO's near-perfect lattice match with
PZT allows PZT to growth epitaxially at low temperature. When LNO is
used as top electrode of the ferroelectric capacitor, the fatigue
performance is greatly improved. The COI LNO/PZT/LNO FeRAM structure
achieved by this low temperature process is completely modular and is
ideal for advanced Cu/low- K SOC application.
24.4 - 3:30pm
High Speed, Low Power, Optoelectronic InP-Based HBT Integrated Circuits
(Invited)
M. Sokolich, HRL Laboratories LLC, Malibu, CA
Abstract :
The next generation of fiber optic communication systems will require
circuits operating at 50 GHz clock rates. InP-based Heterojunction
Bipolar Transistors (HBTs) are ideally suited for the relatively low
integration levels but high speed and low power required in
optoelectronic transceivers. We review material, device and circuit
issues related to InP HBT and the significant challenge that exists
because communication system requirements are approaching the
performance limits of high speed technologies.
24.5 - 4:20pm
Sea of Leads (SoL) Characterization and Design for Compatibility with
Board-Level Optical Waveguide Interconnection
M. Bakir, H. Reed, A. Mule, P. Kohl, K. Martin and J. Meindl, Georgia
Institute of Technology, Atlanta, GA
Abstract :
Sea of leads (SoL) is a novel ultra-high density wafer-level packaging
technology. Microwave two-port measurements on SoL are comparable to
flip-chip packages indicating that the compliant leads do not degrade
electrical performance. Moreover, physical design rules describing SoL
design compatibility with board-level optical signal distribution via
waveguides are derived.
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Session 25 - Modeling for Signal Integrity
Chairman: Steffen Rochel
Co-Chairman: Jamil Kawa
This session focuses on modeling and measurement techniques aimed at
characterizing signal integrity in circuits. Presentations cover IR
drop, substrate noise, and lossy interconnect.
1:30pm - Introduction
25.1 - 1:35pm
A Comprehensive Geometry-Dependent Macromodel for Substrate Noise
Coupling in Heavily Doped CMOS Processes
D. Ozis, T. Fiez and K. Mayaram, Oregon State University, Corvallis, OR
Abstract :
An accurate substrate noise coupling macromodel for heavily doped CMOS
processes is presented. The model is based on Z parameters that are
scalable with contact separation and size. Extensive experimental
validations of the model have demonstrated that the modeled Z parameters
are most often accurate to within 2-8%.
25.2 - 2:00pm
Modeling Substrate Noise Generation in CMOS Digital Integrated Circuits
M. Nagata, T. Morie and A. Iwata, Hiroshima University,
Higashi-Hiroshima, Japan
Abstract :
A time-series divided parasitic capacitance model provides a general way
of modeling substrate noise generation in CMOS digital circuits.
Simulated substrate noise from a 0.25-um z80 micro-controller is
consistent with 200-ps 100-uV resolution measurements in wave-shapes
validated for up to 125-MHz clock frequency and shows the peak-amplitude
error of < 2% against supply-voltage scaling from 2.5 V to 1.6 V.
25.3 - 2:25pm
The Effect of Supply and Substrate Noise on Jitter in Ring Oscillators
N. Barton, D. c, T. Fiez and K. Mayaram, Oregon State University,
Corvallis, OR
Abstract :
In this paper it is found through measurements, simulations and
equations that differential and single-ended ring oscillators have
comparable performance when subjected to the same deterministic noise.
Both topologies are shown to have a greater sensitivity to supply noise
than substrate noise. The measurements agree strongly with the
simulations and equations.
25.4 - 2:50pm
Passive Closed-Form Time-Domain Macromodels for On-Chip Distributed RC
Interconnects
A. Dounavis, R. Achar and M. Nakhla, Carleton University, Ottawa, ON,
Canada
Abstract :
This paper presents a closed-form passive time-domain macromodeling
algorithm for multiport distributed RC interconnect networks. The
method offers an efficient means to discretize RC distributed
interconnects compared to the conventional lumped discretization while
preserving the passivity of the macromodel. In the proposed method,
coefficients describing the discrete time-domain macromodel are computed
using closed-form matrix rational approximation of exponential matrices
and can be computed a priori. The proposed model is suitable for
inclusion in general purpose circuit simulators such as SPICE and
overcomes the mixed frequency/time simulation difficulties encountered
during transient analysis.
25.5 - 3:30pm
Delay and Power Model for Current-mode Signaling in Deep Submicron
Global Interconnects
R. Bashirullah, W. Liu and R. Cavin*, North Carolina State University,
Raleigh, NC and *Semiconductor Research Corporation, Research Triangle
Park, NC
Abstract :
New closed-form expressions of delay and power dissipation for
current-mode signaling over distributed RC lines are derived. The
expressions exhibit an accuracy that is within 5% for a wide range of
parameters. Based on these formulations, a comparison between
voltage-mode repeater insertion technique and current-mode signaling
over long global deep submicron interconnects is presented.
25.6 - 3:55pm
A Comprehensive Study of Energy Dissipation in Lossy Transmission Lines
Driven by CMOS Inverters
P. Heydari, S. Abbaspour* and M. Pedram*, University of California,
Irvine, CA and *University of Southern California, Los Angeles, CA
Abstract :
In this paper, new formulations for the energy dissipation of lossy
transmission lines driven by CMOS inverters are provided, and a new
performance metric for the energy optimization under the delay
constraint is proposed. The energy formulations are obtained by using
approximated expressions for the driving-point impedance of lossy
coupled transmission lines which itself is derived by solving
Telegrapher's equations. A comprehensive analysis of energy is performed
for a wide variety range of the gate aspect-ratios of the driving
transistors. To accomplish this task, two stable circuits that are
capable of modeling the transmission line for a broad range of
frequencies are synthesized. Experimental results show that the energy
calculated using these equivalent circuits are almost equal to the one
calculated by solving the more complicated transmission line equations
directly. Next, using a new performance metric the effect of geometrical
variations of interconnect and the driver on the energy optimization
under the delay constraint is studied. The experimental results verify
the accuracy of our models.
25.7 - 4:20pm
Measurement Results of On-Chip IR-Drop
K. Kobayashi, J. Yamaguchi and H. Onodera, Kyoto University, Kyoto,
Japan
Abstract :
This paper describes measurement results of on-chip IR-drop. An IR-drop
measurement circuit is implemented in an LSI. It can sense the voltage
drop of a power node to alter a reference voltage and clock timing. A
measured waveform can be obtained automatically with using the Shmoo
plot functionality of an LSI tester. Measuring two different nodes along
a VDD line, differential IR-drop waveforms can be successfully obtained
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