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Session 18 - SoC Design Methodologies
Chairman: Michele Taliercio
Co-Chairman: Thomas Zimmermann
This session discusses IP, Bus, EMI, and packaging constraints which
impact SoC realization. Complementing this are two real-life
applications covering voice telephony and MP3.
8:30am - Introduction
18.1 - 8:35am
A Design Methodology for Low EMI-Noise Microprocessor with Accurate
Estimation-Reduction- Verification
H. Tsujikawa, K. Shimazaki, S. Hirano, M. Ohki, T. Yoneda and H. Benno,
Matsushita Electric Industrial Co., Ltd., Kyoto, Japan
Abstract :
The main objective of our work is to develop a total solution for
dramatically reducing Electromagnetic Interference noise in high-
performance LSI microchips at the design stage through unifying
estimation, reduction, and verification. This innovative methodology has
been proven in the successful design of a 32-bit microprocessor with
very low EMI noise.
18.2 - 9:00am
Design Integration, DFT, and Verification Methodology for an MPEG 1/2
Audio Layer 3 (MP3) SoC Device
B. Birkl, B. Hooser, M. Janssens, F. Lenke and V. Vorisek, Motorola,
Munich, Germany
Abstract :
The SoC design and integration methodology of a MP3 decoder is
discussed. Based on state of the art techniques for chip implementation,
verification and Design For Test the challenge was to absolutely
minimize risk and problem areas. It was proven that the implementation
of a complex SoC is possible within 8 weeks.
18.3 - 9:25am
A Design Methodology for Integrating IP into SoC Systems
P. Coussy, A Baganne and E. Martin, Universite de Bretagne Sud, Lorient,
France
Abstract :
Successful integration of IP/VC blocks requires a set of view that
provides the appropriate information for each IP Block through the
design flow for an IP-integration system. In this paper, we present a
methodology of IP integration in a System-on a chip (SOC) design, that
exploits both IP designer and SOC integrator constraints. First, we
describe a method to extract and specify IP functional and timing
constraints (I/O sequence transfer constraints) from the IP core.
Second, we propose a modeling style of the integration constraints and a
technique for merging them with IP constraints. This technique allows
the specification and design of an optimized IP interface unit required
for IP-Socketization. The synthesis output is synthesizable VHDL RT of
the interface, a detailed Bus- Functional model of the IP core towards
Cosimulation.
18.4 - 10:05am
A Voice Processing and Control Module for Cable Telephony Applications
J. Nabicht, J. Pitz, P. Siniscalchi, C. Betty, S. Maggiotto, D.
Richardson, S. DeSoto, S. Sridharan, S. Vemulapalli, K. Downs, D. Gata,
A. Dweik, D. Guidry, K. Muskoff, B. Beckham and G. Westphal, Texas
Instruments, Inc., Dallas, TX
Abstract :
An IF-baseband multi-chip module, fabricated in 3.3V 0.35um mixed-signal
and 1.8V 0.18um digital CMOS, provides OQPSK demodulation with carrier
recovery, memory and control, voice-companding CODECs, and SLIC
interfaces (SIs) for a CATV telephony distribution system. The die area
of the mixed-signal IC is 84.9mm2 and 15.2mm2 for the digital IC. The
power dissipation is 660mW.
18.5 - 10:30am
NECoBus: A High-End SoC Bus with a Portable and Low-Latency
Wrapper-Based Interface Mechanism
K. Anjo, A. Okamura, T. Kajiwara*, N. Mizushima, M. Omori and Y. Kuroda,
NEC Corporation and *NEC Micro Systems Ltd., Kanagawa, Japan
Abstract :
An NECoBus, a wrapper-based bus architecture designed for creating
portable yet high-throughput SOCs, is described. The wrapper- based bus
implementation techniques are newly developed to remove the latency
penalty: retry encapsulation, write-buffer switching, early bus request
and converter-based multiple bit-width connection. The first
implementation of the 32/64 bit NECoBus targeted at 200-MHz operation
using the 0.13-um CMOS processes is described. Evaluation results
demonstrate a 16% throughput improvement, and a 15% and 40% read/write
latency reduction by the developed techniques.
18.6 - 10:55am
System-on-Chip (SoC) Requires IC & Package Co-Design and Co-Verification
A. Fontanelli, S. Arrigoni, D. Raccagni and M. Rosin,
STMicroelectronics, Agrate Brianza, Italy
Abstract :
System-on-chip's first-time silicon success demands that the IC and its
hosting package be designed and verified as a single whole. For this IC
and package co-design and co-verification to be successful, however,
three ingredients are required: a change in methodology, the
availability of a new category of EDA tools, and a major shift in the
profile of the designers and engineers involved.
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Session 19 - Analog Techniques
Chairman: David Allee
Co-Chairman: Tatsuji Matsuura
This session covers significant advances in compensation methods for
multistage amplifiers, and genetic algorithms and optimization
techniques for improving filter performance.
8:30am - Introduction
19.1 - 8:35am
Active-Feedback Frequency Compensation for Low-Power Multi-Stage
Amplifiers
H. Lee and P. Mok, The Hong Kong University of Science and Technology,
Clear Water Bay, Hong Kong
Abstract :
This paper describes a novel active-feedback frequency compensation
(AFFC) technique for low-power multi-stage amplifiers. With a
high-speed active feedback block, the proposed compensation technique
significantly improves both the frequency and the transient responses of
the amplifier. Implemented by a standard 0.8um CMOS process, a
three-stage AFFC amplifier achieves 100dB gain, 4.5MHz gain-bandwidth
product, 65° phase margin and 1.5V/us slew rate with 0.4mW power
consumption when driving a 100pF capacitive load.
19.2 - 9:00am
Nested Feed-Forward Gm-Stage and Nulling Resistor Plus Nested-Miller
Compensation for Multistage Amplifiers
X. Peng and W. Sansen, Katholieke Universiteit, Leuven, Belgium
Abstract :
A new frequency-compensation topology (NGRNMC) is proposed, which
improves the frequency and transient responses of multistage amplifiers.
Comparisons are made to demonstrate the advantages of the topology. A
three-stage fully-differential NGRNMC amplifier is fabricated,
evidencing the experimental results. Criterions are proposed to
accurately evaluate amplifiers implemented in different operating
conditions.
19.3 - 9:25am
Three Stage Amplifier with Positive Feedback Compensation Scheme
J. Ramos and M. Steyaert, Katholieke Universiteit, Leuven, Belgium
Abstract :
A CMOS opamp that can drive large capacitive loads is presented. The
technique employs a positive feedback compensation (PFC) to improve
frequency response as compared to nested Miller compensation (NMC),
allowing the circuit to occupy less silicon area and straightforward
design. At 1.5 V, the circuit dissipates 275 uW, has more than 100 dB
gain, a gain bandwidth of 2.7 MHz and 1.0 V/us average slew rate while
driving a 130 pF load.
19.4 - 10:05am
A High Gain CMOS Operational Amplifier with Negative Conductance Gain
Enhancement
J. Yan and R. Geiger, Iowa State University, Ames, IA
Abstract :
A fully differential CMOS operational amplifier using a negative
conductance gain enhancement technique is presented. The amplifier was
fabricated in an AMI 0.5 um CMOS process with an active area of 0.17
mm2. With a 3 Volts supply, a DC gain of more than 80dB was measured.
The gain exceeded 60 dB for a 240mV output swing.
19.5 - 10:30am
A Noninvasive Channel-Select Filter for a CMOS Bluetooth Receiver
A. Zolfaghari and B. Razavi, University of California, Los Angeles, CA
Abstract :
A fourth-order filter incorporates a method of suppressing interferers
without filtering the desired signal, relaxing the trade-offs between
noise, linearity, and power dissipation. Designed for the baseband of a
2.4-GHz receiver and fabricated in a 0.25 um CMOS technology, the filter
exhibits an input-referred noise of 17 nV/rtHz while dissipating 2 mW
from a 2.5-V supply.
19.6 - 10:55am
An AI-Calibrated IF Filter: A Yield Enhancement Method with Area and
Power Dissipation Reductions
M. Murakawa, T. Adachi*, Y. Nino*, E. Takahashi, Y. Kasai, K. Takasuka*
and T. Higuchi, AIST, Japan and *Asahi Kasei Microsystems, Japan
Abstract :
We have developed an LSI for Gm-C IF filters, attaining (1) a 63%
reduction in filter area, (2) a 38% reduction in power dissipation,
compared to existing commercial products, and (3) a yield rate of 97%.
The developed chip is calibrated within a few seconds by a Genetic
Algorithm; an efficient AI technique for difficult optimization
problems.
19.7 - 11:20am
A 1.2Gbps SOI-BiCMOS Write Driver for Hard Disk Drives
H. Yoshizawa, Y. Kobayashi, M. Yoshinaga, Y. Ookuma, K. Maio and K.
Irikura*, Hitachi, Ltd., Tokyo, Japan and *Hitachi ULSI System Co.,
Ltd., Tokyo, Japan
Abstract :
A voltage-type write driver for a +5/-5V preamplifier is described. With
full-time or partial impedance matching by maximizing the driving
voltage up to the power source, a good rise/fall time and smooth
settling are achieved. Designed in 0.35um SOI-BICMOS, it has
demonstrated a rise time as short as 0.34ns with more than 150mA
peak-to-peak write current at the data transfer rate of 1.2Gbps.
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Session 20 - Multi Gigabit Systems and Circuits
Chairman: Jafar Savoj
Co-Chairman: Johan Van Der Tang
Addressing the need for high data-rate networks, this session focuses on
circuits and systems for multi-gigabit optical and backplane
communications.
8:30am - Introduction
20.1 - 8:35am
A 10Gbase Ethernet Transceiver (LAN PHY) in a 1.8V 0.18um SOI/CMOS
Technology
T. Yoshimura, K. Ueda, J. Takasoh, Y. Wada, T. Oka, H. Kondoh, O. Chiba,
Y. Azekawa and M. Ishiwaki, Mitsubishi Electric Corporation, Itami,
Japan
Abstract :
In this paper, we present a 10Gbase Ethernet Transceiver that is
suitable for the 10Gbit Ethernet applications. The 10Gbase Ethernet
Transceiver LSI, which contains the high-speed interface and the fully
integrated IEEE 802.3ae compliant logics, is fabricated in a 0.18um
SOI/CMOS process and dissipates about 2.9W at 1.8V supply.
20.2 - 9:00am
A 2.5 Gbps CMOS Optical Receiver Analog Front-End
W.-Z. Chen and C.-H. Lu, National Central University, Chung-Li, Taiwan,
ROC
Abstract :
This paper describes the design of a 3 V, single chip optical receiver
analog front-end . Fabricated in a 0.35 um CMOS technology, this IC
contains a TIA with 54.5 dB conversion gain, f(-3dB) of 2.5 GHz, and a
limiting amplifier with a conversion gain of 42 dB, f(-3dB) of 2.3 GHz.
The TIA is DC coupled to the limiting amplifier. The measured eye
diagram meet OC-48 transition mask.
20.3 - 9:25am
An Adaptive PAM-4 5Gb/s Backplane Transceiver in 0.25um CMOS
J. Sonntag, J. Stonick, J. Gorecki, B. Beale, B. Check, X.-M. Gong, J.
Guiliano, K. Lee, B. Lefferts, D. Martin, U.-K. Moon, A. Sengir, S.
Titus, G.-Y. Wei, D. Weinlader and Y. Yang, Accelerant Networks, Inc.,
Beaverton, OR
Abstract :
A 5Gcb/s transceiver is described, which uses PAM-4 signalling and
continuously adaptive transmit based equalization across typical FR-4
backplanes for total distances of up to 50 inches through two sets of
backplane connectors. The 17mm2 device, implemented in a 0.25um CMOS
process, consumes 1.2W from 2.5V and 3.3V supplies.
20.4 - 10:05am
The Role of Monolithic Transmission Lines in High-Speed Integrated
Circuits (Invited)
B. Razavi, University of California, Los Angeles, CA
Abstract :
This paper describes the role of transmission lines amenable to
integration in VLSI technologies and their important circuit
implications. First, an overview of microstrips, coplanar lines, and
striplines is given and their performance limitations are quantified.
Next, modeling and simulation issues are addressed and the role of
transmission lines as circuit elements is discussed. Finally, examples
of circuits that benefit from monolithic transmission lines are
presented.
20.5 - 10:55am
Single Reference Continuous Rate Clock and Data Recovery from 30MBit/s
to 3.2GBit/s
J.-P. Frambach, R. Heijna and R. Krosschell, Philips Semiconductors,
Nijmegen, The Netherlands
Abstract :
Today's networks encompass a myriad of bit rates, both new appearing as
well as legacy ones. To cover all these bit rates, a continuous rate
chip-set was developed, containing a continuous rate Clock and Data
Recovery, capable of recovering any bit rate between 30 Mbit/s and 3.2
Gbit/s. While using only one single reference frequency, a frequency
acquisition loop, based on a fractional-N divider and a Frequency Window
Detector, provides 4.8 Hz frequency resolution. A built-in PRBS
generator provides for high frequency testing.
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Session 21 - DSP for Communications
Chairman: Elliot Gould
Co-Chairman: Bryan Ackland
Designers need high-performance, low-power DSP to build next-generation,
high-speed data-communication systems. This session describes new
architectures for 3G terminals and basestations, along with a
high-performance crossbar switch.
8:30am - Introduction
21.1 - 8:35am
Integrated Circuits for 3GPP Mobile Wireless Systems (Invited)
C. Nichol and M. Cooke, Bell Labs, Lucent Technologies, North Ryde,
Australia
Abstract :
This paper describes the architecture of integrated circuits for
base-band processing in 3rd Generation (3G) mobile wireless systems.
Wideband CDMA receiver functions including the RAKE, rate de/matching,
channel de/interleaving, channel de/coding and multi- user detection are
described. Silicon implementations of a 3GPP channel decoder and also a
multi-user base-band signal processor are presented. The High Speed
Downlink Packet Access (HSDPA) system - providing downlink data rates in
excess of 10 Mbps and the 20 Mbps Multiple Input/Multiple Output (MIMO)
extensions are also described. The architecture of a 21.6 Mbps MIMO
HSDPA receiver for mobile terminals with 2 or 4 antennas is shown that
uses the V-BLAST MIMO detection algorithm.
21.2 - 9:25am
A 80 Mb/s Low-power Scalable Turbo Codec Core
A. Giulietti, B. Bougard, V. Derudder, S. Dupont, J.-W. Weijers and L.
Van der Perre, IMEC, Leuven, Belgium
Abstract :
This paper presents a convolutional full-duplex turbo codec core based
on innovative solutions for low-power, high speed and scalability. The
design has a final throughput of 80.7 Mb/s, a decoding latency of 10us
and an estimated power consumption of less than 50 nJ/bit. It has been
implemented as a 14.7 mm2 CMOS 0.18um core.
21.3 - 10:05am
600Mhz DSP for Baseband Processing in 3G Base Stations
T. Wolf, D. Hocevar, A. Gatherer, P. Geremia* and A. Laine*, Texas
Instruments, Inc., Dallas, TX and *Texas Instruments, Inc., Nice, France
Abstract :
A 1.2V 600Mhz 4800MIPS DSP is a solution for baseband processing in 3G
base stations. It is based upon a partitioning of the workload between a
DSP core and two flexible forward error correction coprocessors. This
allows the DSP to handle a larger number of channels and/or to
incorporate advanced algorithms.
21.4 - 10:30am
A Low-Power W-CDMA Demodulator using Specially-Designed Micro-DSPs
H. Igura, M. Hirata*, J. Yamada, M. Yamashina and S. Ono*, NEC
Corporation, Kanagawa, Japan and *NEC Networks, Yokohama, Japan
Abstract :
This paper presents the architecture of a demodulator developed for
W-CDMA digital baseband processing. The demodulator features micro-DSPs
specially designed for it and a variety of power-lowering and
area-saving techniques such as detailed clock control, reduction of
unnecessary signal transition and data compression. These features give
the demodulator much lower power consumption and smaller size than a
conventional one.
21.5 - 10:55am
Piece-wise Parabolic Interpolation for Direct Digital Frequency
Synthesis
A. Eltawil and B. Daneshrad, University of California, Los Angeles, CA
Abstract :
A compact architecture for direct digital frequency synthesis (DDFS) is
presented. The computation of the sinusoidal values is performed by a
parabolic interpolation structure, which stores only interpolation
coefficients in the Read-Only Memory (ROM). The ROM size is consistently
less than 1 Kbits for SFDR values up to 85 dBc.
21.6 - 11:20am
FLEXBAR: A Crossbar Switching Fabric with Improved Performance and
Utilization
J. Chang, S. Ravi* and A. Raghunathan*, Stanford University, Palo Alto,
CA and *NEC USA, Inc., Princeton, NJ
Abstract :
Flexbar proposes a novel hardware enhancement to improve the performance
and utilization of a crossbar. For a network switch, latency reduces by
upto 70% and throughput of highly loaded ports increases by over 100%.
A full-custom design in 0.35-micron CMOS technology requires marginal
area and performance overheads (4.47% and 8.23%,respectively).
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