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Session 9 - Application Specific Signal Processors
Chairman: Ram Krishnamurthy
Co-Chairman: Masataka Matsui
High-performance signal processing forms the core of many real-world
applications. This session describes advances shown in encryption,
forward error correction (FEC), imaging, and MPEG2.
8:30am - Introduction
9.1 - 8:35am
A 2.29 Gbits/sec, 56 mW Non-Pipelined Rijndael AES Encryption IC in a 1.8V, 0.18um CMOS
Technology
H. Kuo, I. Verbauwhede and P. Schaumont, University of California, Los Angeles, CA
Abstract :
An ASIC for the Rijndael encryption algorithm includes a non-pipelined
encryption data path with an on-the-fly key schedule data path. At
1.8V, the IC runs at 125MHz resulting in a throughput of 2.29Gbits/sec
and 56mW. At 1.95V, the chip operates up to 154MHz with an equivalent
throughput of 2.8Gbits/sec and 82mW.
9.2 - 9:00am
Burst Mode: A New Acceleration Mode for 128-bit Block Ciphers
Y. Mitsuyama*, Z. Andales*,***, T. Onoye** and I. Shirakawa*, *Osaka
University, Osaka, Japan, **Kyoto University, Kyoto, Japan and ***University of the Philippines at Los Banos, Laguna, Philippines
Abstract :
"Burst mode", which improves encryption throughput without compromising
it's security, is a new cipher mode for 128-bit block ciphers. We
investigate it's HW/SW codesign, to be implemented as an accelerator
core running in parallel with a software-based block cipher.
Implementation results show that the accelerator core raises the speed
of software AES by four times.
9.3 - 9:25am
Single-chip FEC Codec LSI using Iterative CSOC Decoder for 10 Gb/s Long-haul Optical
Transmission Systems
K. Seki, K. Mikami, M. Baba, A. Katayama*, H. Tanaka, Y. Hara, M. Kobayashi and
N. Okada, NEC Corp., Kanagawa Japan and *NEC Engineering, Ltd., Kanagawa, Japan
Abstract :
This paper describes a 10 Gb/s throughput FEC (Forward Error Correction)
codec LSI for long-haul optical transmission systems. The FEC codec
uses concatenated Reed-Solomon(255,239) and Convolutional Self
Orthogonal Code (CSOC). In order to improve the error correction
capability, the FEC code applies iterative CSOC decoding. As a result,
the FEC codec provides 8.0 dB net coding gain at 1E-12 corrected bit
error rate with 25% redundancy. Due to the low complexity of CSOC, the
codec achieves a low power consumption of 3.59 W and a low gate count of
1.32 Mgates using 0.18 um CMOS technology.
9.4 - 10:05am
A Vector DSP for Imaging
J. Redford, B. Bersack, M. Moniz, F. Huettig and D. Fitzgerald,
ChipWrights Inc., Newton, MA
Abstract :
The CW4011 is an SoC containing a DSP with a novel vector architecture.
It exploits the parallelism and narrow data typical of image processing
to gain high performance at a low cost and power. It contains eight
32-bit datapaths all working off of a single instruction. It can do 16
16-bit MACs/cycle, and also four 32-bit memory accesses per cycle to 128
KB of on-chip memory. It also contains a serial datapath for handling
low-performance code and OS functions. The chip also includes memory,
video, and IO interfaces on an industry-standard bus. It is built in
0.18 um, is 7.8 x 6.8 mm, runs at 200 MHz (worst-case) and draws less
than 500 mW. This gives the best cost-performance of any processor on
the market for imaging applications.
9.5 - 10:30am
A Single-Chip MPEG-2 Codec Based on Customizable Media Microprocessor
S. Ishiwata, T. Yamakage, Y. Tsuboi, T. Shimazawa, T. Kitazawa, S.
Michinaka, K. Yahagi, H. Takeda, A. Oue, T. Kodama, N. Matsumoto, T.
Kamei, T. Miyamori, G. Ootomo and M. Matsui, Toshiba Corporation,
Kanagawa, Japan
Abstract :
A single-chip MPEG2 MP@ML codec, integrating 3.8M gates on 72mm2 die, is
described. It has heterogeneous multiprocessor architecture in which six
microprocessors with the same instruction set but different
customization execute specific tasks such as video, audio etc.
concurrently. The microprocessor, developed for digital media
processing, provides various extensions such as VLIW one and DSP one
inherent in its architecture. Making full use of the extensions, the
chip executes video, audio and system encoding and decoding concurrently
in real time.
9.6 - 10:55am
An Ultra Low Power, Realtime MPEG2 MP@HL Motion Estimation Processor
Core with SIMD Datapath Architecture Optimized for Gradient Descent
Search Algorithm
M. Miyama, O. Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato,
J. Miyakoshi, K. Hashimoto, S. Komatsu*, M. Yagi**, M. Morimoto**, K.
Taki** and M. Yoshimoto, Kanazawa University, Kanazawa, Japan, *The
University of Tokyo, Japan and **Kobe University, Japan
Abstract :
This paper describes a motion estimation (ME) processor core for
realtime, MP@HL video encoding. It is being fabricated with 0.13um CMOS
technology and contains approximately 7 M-transistors on 4.50mm x 3.35mm
area. The estimated power consumption is less than 100mW at 81MHz@1.0V.
It features a Gradient Descent Search (GDS) algorithm that drastically
reduces the required computation power to 7GOPS, an optimized SIMD
datapath architecture that decreases the clock frequency and the
operating voltage, and a low power 3-port data cache SRAM with a
write-disturb-free cell array arrangement. The core can be applicable
to a portable HDTV codec system.
9.7 - 11:20am
A Low-power Highly-Integrated MPEG1/2 Audio Layer 3 (MP3) Decoder for
CD-based Systems
H. Cloetens, R. Hahn, B. Hooser and F. Lenke, Motorola, Munich, Germany
Abstract :
The system design and chip implementation aspects of a MP3 decoder chip
suitable for CD-based systems is discussed. This innovative architecture
addresses low-power requirements for portable applications. The
implementation uses a synthesizable System- on-a-Chip approach. The chip
has been fabricated in 0.18um CMOS technology and up to 80 hours of
playtime is achieved.
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Session 10 - Oversampled Data Converters
Chairman: Pat Rakers
Co-Chairman: Douglas Garrity
This session comprises papers describing low-power and multi-bit
techniques for the development of oversampled analog-to-digital
converters for lowpass and bandpass applications.
8:30am - Introduction
10.1 - 8:35am
Delta-Sigma Data Converters for Wireless Transceivers (Special
educational session)
Ian Galton, University of California, San Diego
Abstract :
Not available at this time.
10.2 - 9:25am
An 80MHZ 8th-Order Bandpass Delta-Sigma Modulator with a 75DB SNDR for
IS-95
T. Salo, S. Lindfors* and K. Halonen, Helsinki University of
Technology, Hut, Finland and *Aalborg University, Aalborg, Denmark
Abstract :
An 8th-order cascade bandpass delta-sigma modulator is implemented using
only two Opamps and operates at a sampling frequency of 80MHz. The
circuit can be used in an IF-receiver to combine frequency
downconversion with A/D-conversion. The measured peak SNDR is 75dB for a
1.25MHz bandwidth (IS-95) and the circuit consumes 37mW@3.0V.
10.3 - 10:05am
Digital Techniques for Improved Delta-Sigma Data Conversion (Invited)
J. Silva, X. Wang, P. Kiss, U. Moon and
G. Temes, Oregon State University, Corvallis, OR
Abstract :
Two digital techniques are described in this tutorial, both aimed at
improving the accuracy of delta-sigma data converters. The first one
corrects adaptively for mismatch errors in a MASH ADC, while the other
acquires and then corrects for the nonlinearity of the internal multibit
DAC used in the ADC.
10.4 - 10:55am
A Multi-Bit Sigma-Delta ADC for Multi-Mode Receivers
M. Miller and C. Petrie, Motorola, Schaumburg, IL
Abstract :
A 2.7-volt sigma-delta modulator with 6-bit quantizer is fabricated in
0.18um CMOS. High linearity is achieved using dynamic element matching
and quantizer offset chopping. Sampling at 46MHz, the part achieves
70dB SNR over 1.92MHz and dissipates 50mW. Sampling at 23MHz, the part
achieves 92dB SNR over 18kHz and consumes 30mW.
10.5 - 11:20am
Sub-Sampling Sigma-Delta Modulator for Baseband Processing
S. Chandrasekaran and W. Black, Iowa State University, Ames, IA
Abstract :
A Sigma-Delta modulator has been developed for baseband processing in a
Direct Conversion Receiver (DCR). A second-order SD modulator with a
sub-sampling mixer, inside the feedback loop, downconverts the incoming
RF signals directly to baseband, digitizes them and attenuates noise as
well as interferers. A prototype was fabricated in TSMC 0.25u process
for use in a cdma2000 transceiver. SNR of 37 dB was measured for 1Vpp
single-ended inputs at 500MHz, at a sampling rate of 100 MHz. Further
measurements are in progress.
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Session 11 - Modeling for RF Design
Chairman: Larry Nagel
Co-Chairman: Colin McAndrew
Key issues in RF design are noise and integrated inductors. This
session covers RF noise, analysis of the effect of noise on oscillators,
and improved models and designs for on-chip inductors.
8:30am - Introduction
11.1 - 8:35am
MOSFET Modeling for Low Noise, RF Circuit Design (Invited)
M.J. Deen, C.-H. Chen and Y. Cheng*, McMaster University, Hamilton, ON,
Canada and *Conexant Systems, Newport Beach, CA
Abstract :
In this paper, high frequency (HF) AC and noise modeling of MOSFETs for
low noise, radio frequency (RF) integrated circuit (IC) design are
discussed. Scalable parasitic model and the Non-Quasi-Static (NQS) model
are discussed and verified with the measured data. For the noise
modeling, extracted noise sources of MOSFETs in 0.18 um CMOS process and
from RF noise measurements are presented. Finally, the design
consideration including selection of device size, bias condition and
design of the device geometry are discussed.
11.2 - 9:25am
Modeling the Gate-Related High-Frequency and Noise Characteristics of
Deep-Submicron MOSFETs
R. Kraus and G. Knoblinger*, University of Bundeswehr Munich, Neubiberg,
Germany and *Infineon Technologies AG, Munich, Germany
Abstract :
The presented compact model considers the following high-frequency and
noise effects at the gate of MOS transistors: real part of input
impedance, non-quasistatic charge variations and induced gate noise with
correlation to the drain noise. A model equation of the induced gate
noise is developed for MOSFETs with very short channel lengths.
11.3 - 10:05am
Virtual Damping in Oscillators
D. Ham and A. Hajimiri, California Institute of Technology, Pasadena, CA
Abstract :
This paper presents a new point of view of oscillator noise, bringing
transparent insight into the phase noise. This work successfully
bridges fundamental physics of noise and existing oscillator phase noise
theories and reveals the equivalence of the phase noise and the Einstein
relation. A novel concept of virtual damping is developed utilizing an
ensemble of oscillators as a measure of phase noise. The explanation of
the linewidth narrowing through virtual damping results in a clear
definition of loaded and unloaded quality factors of an oscillators.
The validity of this new approach is verified by excellent experimental
agreement.
11.4 - 10:30am
Frequency-Independent Equivalent Circuit Model for On-Chip Spiral
Inductors
Frequency-Independent Equivalent Circuit Model for On-Chip Spiral
Inductors
Abstract :
A wide-band, physical and scalable 2-pi equivalent circuit model for
on-chip spiral inductors is developed. Using frequency-independent RLC
elements, it accurately captures R(f) and L(f) characteristics beyond
the self-resonant frequency. This new model is fully compatible with
both AC and transient analysis. Verification with measurement data
demonstrates excellent scalability for a wide range of inductor
configurations.
11.5 - 10:55am
Modeling and Optimization of Inductors with Patterned Ground Shields for
a High Performance Fully Integrated Switched Tuning VCO
F. Rotella and J. Zachan, Conexant Systems, Inc., Newport Beach,
CA
Abstract :
Pattern ground shield inductors have been shown to improve the
performance of on-chip inductors by reducing the impact of the resistive
substrate. This paper optimizes these inductors by separating the
capacitive component and inductive component. The trade- offs are
characterized and modeled. An optimized design is developed to improve
the performance of a voltage controlled oscillator using a switched
capacitor architecture.
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Session 12 - Receiver Architectures
Chairman: Oliver Werther
Co-Chairman: Francesco Svelto
Highly integrated direct, dual and low IF receiver architectures used in
wireless applications are discussed in this session. Also covered are
techniques to improve key parameters (e.g., image rejection and
2nd-order nonlinearity).
8:30am - Introduction
12.1 - 8:35am
Dual Mixer Downconversion Architecture Using Complex Mixing Signals:
Enabling Solutions for Software Defined Radios (Invited)
T. Manku, C. Snyder, M. Ting, Y. Ling, J. Khajehpour, B. Kung and L.
Wong, SiRiFIC Wireless Corporation, Waterloo, ON, Canada
Abstract :
A dual mixer architecture using complex mixing functions to perform RF
downconversion is described. This architecture eliminates the need for
the image-re ject and IF filters present in the heterodyne architecture,
while achieving better LO leakage, 1/f noise, and second-order intercept
performance than the direct conversion architecture. This architecture,
implemented in a 1.8 V, 0.18 um CMOS process, achieves a maximum IIP2 of
85 dBm, a baseband 1/f noise corner frequency of less than 100 kHz, a
LO-RF leakage equaling -138 dBm, and an operating frequency ranging from
400 MHz to 2.5 GHz.
12.2 - 9:25am
A Quadrature Direct Digital Downconverter
P. Vancorenland, P. Coppejans, W. De Cock, M. Steyaert and
Katholieke Universiteit Leuven, Belgium
Abstract :
A quadrature direct digital downconverter integrating a continuous time
delta-sigma noise shaping loopfilter with a quadrature bandpass
characteristic is presented. Through the integration of mixers in the AD
converter, RF input signals in the range 0.3 - 1.6 GHz can be
downconverted to 2 digital I and Q streams with a 2 MHz banwdidth
centered around 4 MHz. The converter, integrated in a 0.25um CMOS
technology consumes 14 mW from a 2V supply.
12.3 - 10:05am
A Direct Conversion Receiver for the 3G WCDMA Standard
R. Gharpurey, N. Yanduru, F. Dantoni, P. Litmanen, G. Sirna, T.
Mayhugh, C. Lin, I. Deng, P. Fontaine and F. Lin, Texas Instruments,
Inc., Dallas, TX
Abstract :
A highly integrated direct-conversion receiver that satisfies
requirements of the third generation Wideband Code Division Multiple
Access (WCDMA) mobile phone standard is described. The receiver IC
includes the front-end low-noise amplifier, down-conversion mixers,
channel select filters, baseband variable gain amplifiers, and the
entire frequency synthesizer, including the voltage controlled
oscillator, buffers and phase-locked loop.
12.4 - 10:30am
Analysis and Optimization of IIP2 in CMOS Direct Down-Converters
D. Manstretta and F. Svelto, University of Pavia, Pavia, Italy
Abstract :
Two mechanisms are responsible for second order inter-modulation in CMOS
down-converters: RF self-mixing and device non- linearity and
mismatches. An intuitive model and analytical expressions are provided
for both of them. A down-converter prototype, drawing 3.2 mA from a 1.8
V supply, part of a fully integrated 0.18um CMOS UMTS receiver
front-end, shows 66 dBm IIP2 and 16 dBm IIP3.
12.5 - 10:55am
A Monolithic CMOS Low-IF Bluetooth Receiver
W. Sheng, B. Xia, A. Emira, C. Xin, S.T. Moon, A. Valero-
Lopez and E. Sanchez-Sinencio, Texas A&M University, College Station
Abstract :
A fully integrated low-IF 0.35um CMOS Bluetooth receiver is presented.
The receiver consists of a RF front end, a PLL, an active complex
filter, a GFSK demodulator and a frequency offset cancellation circuit.
The experimental results show a -82 dBm sensitivity at 1e-3 BER, -10 dBm
IIP3 and 15 dB noise figure.
12.6 - 11:20am
A Self-Calibration Technique for Mismatches in Image-Reject Receivers
M. Elmala and S. Embabi*, Texas A&M University, College Station, TX and
*Texas Instruments, Inc., Dallas, TX
Abstract :
This paper presents a modified image-reject Weaver architecture. The
design automatically calibrates for phase and gain mismatches that limit
the performance of image-reject receivers. On-line or off-line
calibrations are possible without using any calibrating tone. An
experimental 0.35um CMOS prototype RF front-end operating at 1.8GHz
achieves an image rejection ratio of 59dB.
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