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Session 5 - Innovations in Programmable Logic: Architectures and Applications
Chairman: Steve Wilton
Co-Chairman: Trevor Bauer
What do chess, virtual silicon, and analog circuitry have in common?
Programmable logic can do it all.
2:00pm - Introduction
5.1 - 2:05pm
An Architecture for a Programmable Mixed-Signal Device
M. Mar, B. Sullam and E. Blom, Cypress
MicroSystems, Inc., Bothell, WA
Abstract :
An architecture for one of the first mixed-signal field-programmable
system-on-a-chip (FPSOC) is presented. The FPSOC integrates an 8-bit
microcontroller, flash memory, SRAM, programmable analog and digital
blocks, and on-chip clock generation. Programmable interconnect allows
analog and digital blocks to be combined to form a wide variety of
functional modules.
5.2 - 2:30pm
Nearest Neighbour Interconnect Architecture in Deep Submicron FPGAs
A. Roopchansingh and J.
Rose, University of Toronto, Toronto, ON, Canada
Abstract :
Several commercial FPGA architectures provide fast connections between
adjacent logic blocks that decrease the best-case delay between circuit
elements with the goal of increasing overall performance. This paper
explores the architecture of these Nearest Neighbour (NN) interconnects
to determine topologies, quantities and distances that are best for
performance and area. We show that certain architectures can achieve a
7.4% performance improvement at the cost of a 6.3% increase in total
FPGA area when fully populated. We also show that a 6.4% improvement
can be achieved for a more modest cost of 3.8% increase in area.
5.3 - 2:55pm
PipeRench: A Virtualized Programmable Datapath in 0.18 Micron
Technology
H. Schmit, D.
Whelihan, A. Tsai, M. Moe, B. Levine and R. Taylor, Carnegie Mellon University, Pittsburgh, PA
Abstract :
PipeRench is a programmable datapath that virtualizes hardware through
self-managed dynamic reconfiguration. The chip is implemented in 0.18
micron CMOS, has 3.65 million transistors and runs at 120MHz. Power
consumption is measured for both static and virtual hardware
configurations. Virtual hardware only requires 30% more power.
5.4 - 3:35pm
The Architecture of Dual-Mode FPGA Embedded System Blocks
E. Lin and S. Wilton, University of
British Columbia, Vancouver, BC, Canada
Abstract :
Unused on-chip memories can be valuable when they are used to implement
logic. This paper explores how different memory architecture parameters
affect the ability to implement logic in dual-mode FPGA Embedded System
Blocks. We show that the optimum memory should be 32 or 64 bits deep
and 16 bits wide.
5.5 - 4:00pm
An FPGA Based Move Generator for the Game of Chess
M. Boule and Z. Zilic, McGill University,
Montreal, PQ, Canada
Abstract :
This paper details the architecture of an FPGA chess-move generator. The
design is based on Deep Blue's move generator. The inherent differences
between ASICs and FPGAs imply many design changes. We present
improvements that exploit important FPGA features (lookup-table based
logic, routing resources, distributed and block RAM).
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Session 6 - Design Approaches for Testability and Reliability
Chairman: Mark Young
Co-Chairman: Mike Zachariah
The importance of designing for test and reliability is the focus of
papers in electrostatic discharge, burn-in, timing measurement, and
soft-errors.
2:00pm - Introduction
6.1 - 2:05pm
A Deep Sub-Micron Timing Measurement Circuit Using a Single-Stage
Vernier Delay Line
A. Chan
and G. Roberts, McGill University, Montreal, PQ, Canada
Abstract :
On-chip timing and jitter measurement is one of the major challenges in
recent years for characterizing high-speed analog and mixed- signal
circuits. Although the Vernier Delay Line (VDL) method is a common
approach to provide high timing resolution, its performance is limited
by differential non-linearity timing errors created by component
mismatches. In this paper, a single-stage VDL approach is proposed in an
attempt to reduce element-matching requirements.
6.2 - 2:30pm
A Burn-In Tolerant Dynamic Circuit Technique
A. Alvandpour, R. Krishnamurthy, S. Borkar, A. Rahman
and C. Webb, Intel Corporation, Hillsboro, OR
Abstract :
Time, cost and efficiency of burn-in test are severely impacted by the
required functionality of leaky sub-130nm dynamic circuits during the
burn-in. In this paper, we present an efficient keeper technique, which
is active during the burn-in, and inactive at normal operating
condition. As a consequence, dynamic circuits remain functional at
burn-in, without relaxing the maximum burn-in condition, and without any
significant performance degradation at normal operating conditions.
Compared to the conventional technique, and at the same level of burn-in
robustness, up to 17% higher performance has been observed at normal
operating condition across 2-to-6 ways dynamic gates in a projected
100nm technology.
6.3 - 2:55pm
Managing Soft Errors in ASICs
L. Wissel, S. Pheasant, R. Loughran, C. LeBlanc and B. Klaasen, IBM
Microelectronics, Essex Junction, VT
Abstract :
Although the industry has long known about soft errors, customer
awareness and concern about soft errors has recently increased.
Advances in customer education, estimatin techniques, and materials
quality assist an ASIC designer in reducing soft-error system fails.
6.4 - 3:35pm
High Voltage Tolerant ESD Design for Analog Applications in Deep Submicron CMOS
Technologies
C.-H. Chen, Y.-K. Fang, C.-C. Tsai*, S. Tu*, M.K.L. Chen* and M.-C.
Chang*, National Cheng Kung University, Tainan, Taiwan, ROC and *TSMC,
Hsinchu, Taiwan, ROC
Abstract :
A new high voltage tolerant (HVT) ESD design adopts one forward biased
P+/N-Well diode in series of one stacked NMOS to reduce the total
capacitance and maintain the high ESD performance is proposed and
implemented by 0.18um CMOS technologies. The measured HBM and MM ESD
levels of the HVT pin exceed 6KV and 550V, respectively, while the
measured input capacitance is only 250fF.
6.5 - 4:00pm
The Embedded SCR NMOS and Low Capacitance ESD Protection Device for Self-Protection
Scheme and RF Application
J.-H. Lee, Y.-H. Wu, K.-R. Peng, R.-Y. Chang, T.-L. Yu and T.-C. Ong, TSMC,
Hsin-Chu, Taiwan, ROC
Abstract :
Inserting the N-Well and P+ diffusion into the drain region of NMOS
transistor, the embedded SCR NMOS (ESCR NMOS), without changing any DC
I-V characteristics of NMOS, and a very low capacitance (~50fF) ESD
protection (LCESD) device are developed successfully for output pad and
input pad, respectively.
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Session 7 - Advances in Embedded Memory
Chairman: Sreedhar Natarajan
Co-Chairman: Cormac O'Connell
This session describes novel memory architectures including 1T
capacitor-less DRAM, molecular memory, and low-power sequential- access
memory. Also featured are ROM-compression algorithms for continuous
data and self-adaptive FLASH programming.
2:00pm - Introduction
7.1 - 2:05pm
A Simple 1-Transistor Capacitor-Less Memory Cell for High Performance
Embedded DRAMs
P. Fazan*,**, S. Okhonin**, M. Nagoga** and J.-M. Sallese**,
*Innovative Silicon Solutions, Le Landeron, Switzerland and **Swiss
Federal Institute of Technology, Lausanne, Switzerland
Abstract :
A new compact memory architecture is proposed for embedded DRAM cells.
By exploiting the floating body effect of partially depleted SOI
devices, a one-transistor memory cell can be integrated in a pure logic
SOI technology without adding any process step. The data retention,
device operation principles and reliability make it ideal for high
performance embedded DRAM applications while reducing the cell area by a
factor of two.
7.2 - 2:30pm
An Interpolating Sense Circuit for Molecular Memory
Y. Nishida and W. Liu, North Carolina State
University, Raleigh, NC
Abstract :
Presented herein is a novel sensing circuit for multi-state molecular
memory technologies. The circuit employs an interpolating sensing scheme
to achieve low power dissipation and high speed sensing of molecular
memory cells. A novel "reference level offset reduction" circuit
technique is used to reduce the current thresholder's offset to nearly
zero. Our interpolation sensing circuit consists of two sense amplifiers
and two interpolators. At 2.5V, the total current for the amplifiers and
interpolators is 587uA and 161uA, respectively. The interpolator
exhibits an overall rise time of 41ns and fall time of 56ns in TSMC
0.25-um process.
7.3 - 2:55pm
A 16kb 1T1C FeRAM Testchip Using Current-Based Reference Scheme
J. Siu, Y. Eslami, A. Sheikholeslami, P. Gulak, T. Endo* and S.
Kawashima*, University of Toronto, Toronto, ON, Canada and *Fujitsu
Laboratories, Ltd., Atsugi, Japan
Abstract :
A 16kb 1T1C FeRAM testchip is designed and fabricated in a 0.35um FeRAM
process. The testchip uses a reference generation scheme that balances
fatigue evenly between memory cells and reference cells, hence providing
the 1T1C cell with 2T2C robustness to fatigue. The testchip achieves an
access time of 62ns at 3V.
7.4 - 3:35pm
Low-Power Sequential Access Memory Design
J.-S. Moon, W. Athas*, P. Beerel and J. Draper**, University of Southern
California, Los Angeles, CA, *Apple Computer, Inc., Cupertino, CA and
**University of Southern California, Marina del Rey, CA
Abstract :
This paper presents the design and evaluation of a sequential access
memory (SAM) that provides low power and high performance by replacing
address decoders with special locally-communicating sequencers. A test
chip containing one 16x16-b SAM and one 64x16-b SAM (consisting of four
16x16-b banks) has been designed, fabricated, and evaluated using a
0.25-um CMOS process. With a clock frequency of 40MHz at 1.2V, the
measured worst-case read power dissipations for the 16x16-b SAM and the
64x16-b SAM are 344uW and 358uW respectively, demonstrating power
dissipation that is largely independent of SAM size.
7.5 - 4:00pm
A Self Adaptive Programming Method with 5 mV Accuracy for Multi-level
Storage in FLASH
L. Engh, A. Kordesch and C.-M. Liu, Winbond Electronics Corporation
America, San Jose, CA
Abstract :
Multi-level storage memory system uses a self-adaptive method that
improves the cell model with each successive program cycle, and
accommodates cell variations and noise. An accuracy of 5 mV is achieved
within eight cycles, which total 125ms. Algorithm control circuits
occupy 1 mm2 of area in a 0.5 um SSI FLASH process.
7.6 - 4:25pm
A ROM Compression Method for Continuous Data
B.-D. Yang and L.-S. Kim, KAIST, Daejeon, Korea
Abstract :
The ROM compression method for continuous data uses a region select ROM
compression algorithm storing only regions including data after dividing
into many small regions and a quantization ROM and error ROM compression
algorithm dividing data into quantized data and errors. Using these
algorithms, 40-60% ROM size reductions are achieved.
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Session 8 - Low Power Circuits and I/O
Chairman: Takayasu Sakurai
Co-Chairman: Thaddeus Gabara
Microprocessors, filter, and flip-flop designers will appreciate the
low-power and high-performance solutions discussed in this session,
which also describes AC coupling for high-density I/O circuits.
2:00pm - Introduction
8.1 - 2:05pm
High-performance and Low-power Challenges for Sub-70nm Microprocessor
Circuits (Invited)
R. Krishnamurthy, A. Alvandpour, V. De and S. Borkar, Intel
Corporation, Hillsboro, OR
Abstract :
Not available at this time.
8.2 - 2:55pm
A New Reduced Clock-Swing Flip-Flop: NAND-type Keeper Flip-Flop (NDKFF)
M. Tokumasu, H.
Fujii, M. Ohta, T. Fuse and A. Kameyama, Toshiba Corporation, Kanagawa, Japan
Abstract :
A new reduced clock-swing flip-flop is proposed. This features simple
configuration, which does not have additional clock drivers or
additional n-wells. Compared with the hybrid-latch flip-flop, 52% of the
flip-flop power and 64% of the clocking power are saved in the case of
0.25um CMOS technology.
8.3 - 3:35pm
4 Gbps High-Density AC Coupled Interconnection (Invited)
S. Mick, J. Wilson and P. Franzon, North
Carolina State University, Raleigh, NC
Abstract :
AC coupled interconnects enable low-power, very-high-density,
multigigabit-per-second communication data rates between integrated
circuits. When realized with inductive coupling elements and a novel
physical structure, AC coupled interconnection can provide
interconnection densities and data rates that surpass all currently
available interconnection schemes.
8.4 - 4:25pm
A Low Power Adaptive Filter Using Dynamic Reduced 2's-Complement
Representation,
Z. Yu, M.-L. Yu*, K. Azadet* and A.N. Willson, University of California,
Los Angeles, CA and *Agere Systems, Holmdel, NJ
Abstract :
By conditionally disabling MSB signal transitions in a data-path, and
doing so dynamically, according to signal magnitude, all the attractive
properties of two's-complement numbers are retained while an over 32%
power savings is achieved in an adaptive filter IC. The technique can
be employed in other DSP applications.
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