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Session 1 - Plenary Session
1.1 - 8:00am
Welcome/Opening Remarks
Awards Presentations
Keynote Speaker Introduction
Jeff Oppold, General Chairman
Abstract :
The general chairman makes introductory remarks for CICC 2002, presents
awards for CICC 2001, and introduces the keynote speaker.
1.2 - 8:20am
Keynote Address
"Smart Management of ASIC Requirements and Technology (SMART)"
C. King, President & CEO, AMI Semiconductor
Abstract :
Complex issues such as time-to-market, productivity, cost, performance
and power continue to challenge the semiconductor industry. Today the
focus is on finding the best overall solution to fit individual
applications and to meet specific market needs. Many applications
require and benefit from the highly advanced system-on-a-chip designs
enabled by the unprecedented silicon potential of ever-shrinking
technologies. For example, high-performance graphics processors in
computers and game systems have evolved to extreme examples of
integration, but are very specific to a given architecture. Routers and
datapath systems, on the other hand, must be configurable to different
I/O and network requirements and are benefiting from a combination of
medium-density ASICs, standard products and FPGAs where the same
"leading-edge" technology is not essential. Today's engineers are
striving to balance the tradeoffs of these two approaches to find the
smartest overall solution. What will the impact of this SMART mind set
be on the semiconductor industry in the year 2002 and beyond?
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Session 2 - Reconfigurable Hot SoCs
Chairman: Jim Lipman
Co-Chairman: Ric Williams
Following an invited reconfigurable-logic tutorial are two papers on
embedded configurable-processor designs. One paper describes unique
code-decompression circuits to reduce code size while the other combines
an extensible core with an embedded FPGA.
10:00am - Introduction
2.1 - 10:05am
Reconfigurable Logic in SoC Systems (Invited)
J. Greenbaum, Chameleon Systems, Inc., San Jose, CA
Abstract :
Reconfigurable logic, that is digital circuits with run-time
programmable interconnect and logic operations, are now appearing as
blocks in commercial System-on-a-Chip (SoC) ICs. Available both for
integration on custom SoCs and as user programmable blocks in off-the-
shelf products, reconfigurable logic is used in a wide a variety of
roles which mirror its use in the board-level systems which SoCs
replace. These roles include glue logic, I/O protocol machines, and
high-speed computation.
2.2 - 10:55am
1-Cycle Code Decompression Circuitry for Performance Increase of
Xtensa-1040-based Embedded Systems
H. Lekatsas, J. Henkel and V. Jakkula, NEC USA, Inc., Princeton, NJ
Abstract :
Code compression is known to be an effective technique to reduce the
instruction memory size of an embedded system. However, code compression
can also be very effective in increasing the processor-to-memory
bandwidth and hence provide increased system performance. In this paper
we describe our design of the world's first running prototype of a
1-cycle code decompression circuitry that decompresses Xtensa 1040
instructions on-the-fly. The circuitry is a stand-alone unit that does
not require any modifications on the Xtensa 1040 processor core. We
observed an average code size reduction of about 35% of programs running
on the system and an average of 45% of performance increase due to the
increased bandwidth and memory hierarchy effects.
2.3 - 11:20am
A Reconfigurable System featuring Dynamically Extensible Embedded
Microprocessor, FPGA and Customisable I/O
M. Borgatti, F. Lertora, B. Foret and L. Cali, STMicroelectronics, Agrate Brianza, Italy
Abstract :
A system-chip targeting image and voice processing and recognition
application domains is implemented as a representative of the potential
of using programmable logic in system design. It features an embedded
reconfigurable processor built by joining a configurable and extensible
processor core and a SRAM-based embedded FPGA. Application-specific
bus-mapped coprocessors and flexible I/O peripherals and interfaces can
also be added and dynamically modified by reconfiguring the embedded
FPGA. The architecture of the system is discussed as well as the design
flows for pre- and post-silicon design and customisation. The silicon
area required by the system is 20mm2 in a 0.18um CMOS technology. The
embedded FPGA accounts for about 40% of the system area.
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Session 3 - Modeling and Optimization Techniques
Chairman: Yuhua Cheng
Co-Chairman: Hidetoshi Onodera
Join this session for new modeling and design methodology ideas for
high-speed interconnects, noise and delay optimization, compact model
compilation, and multi-objective generic optimization techniques for
analog/RF circuits.
10:00am - Introduction
3.1 - 10:05am
Loop-based Interconnect Modeling and Optimization Approach for Multi-GHz
Clock Network Design
X. Huang, P. Restle*, T. Bucelot*, Y. Cao and T.-J. King, University of
California, Berkeley, CA and *IBM T.J. Watson Research Center, Yorktown
Heights, NY
Abstract :
An efficient loop-based interconnect modeling methodology is proposed
for multi-GHz clock network design. High frequency effects, including
inductance and proximity effects are captured. The results are validated
through comparisons with electromagnetic simulations and measured data
taken from a Power4 chip.
3.2 - 10:30am
A Signal Integrity-Driven Buffer Insertion Technique for Post-Routing
Noise and Delay Optimization
K. Chakraborty, D. Long, J. Fishburn, K. Singhal*, L. Ye* and C. Ortiz*,
Agere Systems, Murray Hill, NJ and *Allentown, PA
Abstract :
This paper presents a novel algorithm for combining signal-integrity
analysis with buffer insertion for noise and delay optimization after
place-and-route.
3.3 - 10:55am
ADMS - Automatic Device Model Synthesizer
L. Lemaitre, C. McAndrew* and S. Hamm**, Motorola,
Geneva, Switzerland and *Tempe, AZ and **Austin, TX
Abstract :
This paper presents ADMS, a CAD tool that supports automatic synthesis
of device compact models in SPICE simulators. ADMS takes as input
Verilog-AMS compact model descriptions and C code that conforms to SPICE
simulator interfaces. Various compact models have been implemented into
proprietary and commercial spice simulators using ADMS.
3.4 - 11:20am
Watson: A Multi-Objective Design Space Exploration Tool for Analog and
RF IC Design
B. De Smedt and G. Gielen, Katholieke Universiteit, Leuven, Belgium
Abstract :
Through the use of multi-objective genetic optimization and radial basis
functions fitting, a novel method has been developed which presents to
the designer the hypersurface of Pareto-optimal design points. For the
first time it is now possible to characterize the design space
boundaries of a circuit topology over a broad range of design
specifications, all within transistor-level accuracy. This technique is
illustrated with the presentation of the design space for two different
types of circuits: a Miller-compensated operational transconductance
amplifier, and an LC-tank voltage-controlled oscillator.
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Session 4 - Copper Wired Communications
Chairman: Dave Rich
Co-Chairman: Sang-Soo Lee
This session addresses trends in DSL and wired-communications systems,
focusing on ICs for analog-line interfaces and data- synchronization
applications.
10:00am - Introduction
4.1 - 10:05am
Integration and System Design Trends of ADSL Analog Front Ends and
Hybrid Line Interfaces (Invited)
S.-S. Lee, LSI Logic, San Jose, CA
Abstract :
This paper provides an overview of integration trends and circuit design
challenges for ADSL AFEs and hybrid line interfaces. Line driver
technologies and line receiver design issues are discussed with emphasis
on the tradeoff between noise and linearity. Finally, design challenges
for highly integrated ADSL modem chipset with minimal external
components are addressed.
4.2 - 10:55am
A Central Office Combined ADSL-VDSL Line Driver Solution in .35um CMOS
T. Piessens and M.
Steyaert, Katholieke Universiteit, Leuven, Belgium
Abstract :
A central office ADSL-VDSL line driver in a .35um 3.3 V CMOS technology is presented. The chip has a missing tone power ratio
(MTPR) over 55 dB driving ADSL signals and can deliver VDSL downstream signals with a bandwidth of 8.6 MHz and an out-of-
band PSD of -103 dBm/Hz. The power efficiency is 47% for 100 mW ADSL signals with a crest factor of > 5.
4.3 - 11:20am
A 6MHz-130MHz DLL with a Fixed Latency of One Clock Cycle Delay
H.-H. Chang, J.-W. Lin and S.-I.
Liu, National Taiwan University, Taipei, Taiwan, ROC
Abstract :
Not available at this time.
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