CICC 2002 Conference: Panel Discussions

Design Challenges in Wireless LANs

Session 15 - Afternoon Panel Session
Grand Caribbean Ballroom III
Tuesday, May 14, 2:00 pm - 4:00 pm

Organizers:
David Rich, Lafayette College
Jim Lipman, TechOnLine

Moderator:
Jim Lipman, TechOnLine

Panelists:
Johan Akesson, Ericsson Technology
Eric Hansen, Innovative Wireless Technologies
Cormac O'Connell, SiGe Semiconductor Inc.
Reza Rofougaran, Broadcom
David Su, Atheros Communications
Bruce Tuch, Agere System

Bluetooth and 802.11 wireless network systems have become commercial
realities, with products currently shipping. However, the designer's job is far from finished. Both standards are evolving to higher data rates and lower power consumption. Furthermore, for products to ship in significant volume designers need to reduce the cost of building wireless LANs.

Come hear experts summarize the current state and next generation of the WLAN standards. Our panelists will discuss whether 802.11 and Bluetooth are complementary or competitive technologies. Designers who have developed chips for these systems will discuss issues involved in designing custom ICs for low-cost wireless LAN applications. These issues will include:

• The process technology required for building competitive systems. Can designs be completed in standard CMOS or do you need specialized technologies such as SOI and SiGe bipolar?
• The optimal system architectures for low-cost realizations of wireless LANs.
• The potential of using similar architectures to implement both a Bluetooth and 802.11 system.
• The level of integration that can be achieved between the RF and baseband digital processor along with the ability to move RF passive components from the PC board to the chip.
• The importance of involving circuit designers in the standard-setting process to insure low-cost system realization of wireless LANs.

Will the Next Great Killer Technology Application Please Stand Up!!

Session 16 - Evening Panel Session
Grand Caribbean Ballroom III
Tuesday, May 14, 8:00 pm

Organizers:
Brian Fitzgerald, ChipWrights, Inc.
Rakesh Kumar, Technology Connexions

Moderator:
Rakesh Kumar, Technology Connexions

Panelists:
Brian Fitzgerald, CEO, ChipWrights, Inc.
Doug Palmer, CTO, Path One Networks
Ali Hajimiri, CalTech
David Bursky, Editor, Electronic Design Magazine
Robert Guernsey, Director of Silicon Technology Strategy, IBM Microelectronics

Everyone talks about the next 'killer app', the thing that will change the face of technology and in many ways, the direction of our careers. Or has it been the other way around? That is to say; the technology facilitates the killer app, thereby creating the next great leap in high tech.

What technologies on the drawing board have the potential to fundamentally change our industry and, ultimately, obsolete the very semiconductor electronics in which we are all expert. Will we feel a 'rift in the force', a killer technology that disrupts our very livelihood , or will the progress be 'more of the same'?

And how about the customers, the consumers of new technology? What problem do they really want us to solve for them? Without them, isn't a new technology only going to become the latest 'technological monument' to its inventor and nothing more?

Who will lead the charge in the new millennium? Will it be the industry leaders with their R & D? Or will it be a few of the many masses of high-tech startups that will rise to the top. And how about the economy of this past year; is that affecting innovation?

Come listen to what a panel of experts have to say. The panelists are a blend of people with varied backgrounds from the semiconductor industry who will try to shed light on this important issue.

What are the opinions of the panel members? What is your opinion?

Can Scaling Continue at the Same Rate Below 0.1um? What is the End of CMOS... and What is Next?

Session 17 - Evening Panel Session
Grand Caribbean Ballroom IV
Tuesday, May 14, 8:00 pm

Organizers:
Rich Liu, Macronix International Ltd.
Sreedhar Natarajan, Texas Instruments Inc.

Moderator:
Sreedhar Natarajan, Texas Instruments Inc.

Panelists:
Shekhar Borkar, Director of Circuit Research Lab, Intel Corporation
Dr. Dennis Buss, VP of Silicon Technology Dev., Texas Instruments
Steve Hillenius, Director of Device & Module R&D, Agere Systems
Seiichiro Kawamura, Executive Director, AIST
Jagdish Pathak, President, Sub Micron Circuits Inc.
Dr. Krishna Sarawat, Professor, Stanford University

In the last decade we have seen an acceleration in the rate of scaling. While the need for improving performance and lowering the cost per function continue to be strong driving forces, there are many technological and application challenges that threaten to disrupt this scaling curve. Direct-tunneling gate leakage current will start dominating the total standby current in SRAM and interconnects are not going to scale down with technology. Will these compromise future low-power and high-performance applications? Feature sizes are already well below lithography wavelengths--will new lithography tools and photoresist development schedules meet the future challenges? The cost of masks is already escalating and will become prohibitive for ASICs in the future. How will this change the shape of the custom IC market? The power supply voltage is scaling toward a sub-one-volt regime-- how will this affect the mixed-signal devices? Finally, will the prohibitive cost of 300-mm fabs and technology development drive toward more consolidation and foundry-based process and manufacturing? Will this change the landscape from a score of large integrated IC houses to numerous smaller fabless design houses?