CICC 2002 Ed Sessions: Session 3

High-Performance and Low-Voltage Design Challenges and Techniques

Organizer: Ram Krishnamurthy, Intel Corporation
Co-organizer: Sreedhar Natarajan, Texas Instruments

E3-1
Low-power Circuits & XScale
Larry Clark, Intel Corporation
8:00-9:50

Low-power circuit design is increasing in importance with the proliferation of battery-powered devices and increasingly difficult integrated circuit thermal management. This tutorial will provide an overview of low-power design including process selection, circuit and logic design techniques, clocking, voltage scaling, dynamic voltage adjustment, and leakage management. Examples of techniques used in the industry, as well as details of those used in the XScale Microarchitecture(TM) will be discussed. The XScale microprocessor is capable of operation at 800MHz dissipating 900mW down to 200MHz dissipating 50mW and is capable of changing frequency and voltage on the fly. Standby power of 100uW is enabled by leakage suppression circuitry while retaining state. Application needs and the efficacy of power reduction approaches in addressing them will also be described and compared. Issues with future process scaling and the resulting power implications will conclude the tutorial.

E3-2
Leakage Control & Leakage Tolerant Circuits
Prof. Kaushik Roy, Purdue University
10:10-12:00

This tutorial presents advanced challenges and solutions for leakage control and leakage tolerant VLSI systems. Circuit and CAD techniques for leakage control and tolerance, e.g., stacked CMOS with gated-Vdd, Multiple-Vt, Dynamic-Vt, MTCMOS, VTCMOS, and SCCMOS techniques and their bulk and SOI implementations are discussed. Ultra-low-voltage digital subthreshold logic techniques and some of their medical applications, e.g., bursty vs. non-bursty modes are described.

E3-3
SOI Design Challenges
Andrew Marshall, Texas Instruments
1:00-2:50

Silicon-on-insulator (SOI) material has become an increasingly popular technology for IC design and manufacturing. Performance improvement, reduced power, component isolation and an increase in circuit density are some of the obvious benefits. Many of these advantages, however, have trade-offs , including bipolar leakage effects of the SOI MOS devices, thermal issues, transistor matching difficulties and the history and kink effects for some SOI technologies.

A brief overview of the SOI process is given and a comparison is made between SOI and bulk material. The challenge of modeling SOI devices is explored and some concepts for successful SOI circuit layout are introduced, including a review of various options for the reduction of thermal self-heating effects. Following discussion of digital design techniques, SOI feasibility to SRAM and DRAM memory designs is considered. In addition analog circuit design techniques are discussed. By way of conclusion, low-power design and trends in SOI development are addressed.

E3-4
Low-power Memory Design
Dr. Betty Prince, Memory Strategies International Inc.
3:10-5:00

This session will review issues for low-power memory design including the trend toward portable systems; reliability in nanometer scale geometries; managing high speed operation in standalone memories such as DDR DRAMs and SRAMs; and controlling high speed, heat generating operations in integrated memories such as cache and CAM. Methodology discussed will include reducing power consumption in the memory peripheral circuitry and in the array architecture, and managing memory mode to minimize power. Power issues with non-volatile memories will also be discussed such as use of high-voltage generators on chip.