CICC 2002 Ed Sessions: Session 1

Advanced RF: From Devices to Systems

Organizer: Francesco Svelto, Università di Pavia
Co-organizer: Larry Nagel, Omega Enterprises

E1-1 - RF Performance and Modeling of CMOS Devices
Dirk B.M. Klaassen, Philips Research Laboratories
8:00-9:50

Continuous down-scaling of CMOS process technologies has resulted in a strong improvement of the RF performance of MOS devices. Consequently, CMOS has become a viable option for analog RF applications and RF system-on-a-chip. In order to allow for versatile RF circuit design in CMOS technologies, a number of issues, which traditionally get little or no attention in compact MOS modeling for digital or low-frequency analog circuit design, have to be taken into account: impedances and power gain, output impedance and bulk resistance, input impedance and gate resistance, non-quasi-static (or transit time) effects, power gain, noise, 1/f (or flicker) noise, thermal noise, induced gate noise and distortion.

This presentation focuses on the discussion of these issues for CMOS devices, while in addition an overview will be given of the present state-of-the-art of compact modeling. This part will be followed by a discussion, using both simulations and measurements of layout effects on the RF performance of CMOS devices. Finally, the performance and modeling of passive devices such as varicaps (or varactors) and inductors will be discussed.

E1-2 - RFIC Receiver Circuits
John R. Long, Delft University of Technology
10:10-12:00

This lecture addresses the design of RFIC receiver circuits in CMOS and BiCMOS technologies from antenna to base-band. Major IC building blocks such as low-noise preamplifiers, down-converting mixers, voltage-controlled oscillators, image-reject down-converters and frequency scalers are considered. Technology evaluation for RF performance, selection of an appropriate circuit topology and the relationship between the circuit and systems specifications as preliminary steps in the design process are outlined. The advantages and limitations of on-chip inductors, transformers and other passives available for RFIC work are discussed. Issues in modeling, simulation and circuit design based on the passive and active components available in standard IC design kits and tools are highlighted within the context of each building block. Co-integration and evaluation of receiver blocks are described, with emphasis on topics such as physical layout, package parasitics, off-chip matching, test fixturing and chip evaluation at RF.

E1-3 - Key Issues in Transmitter Blocks
Earl McCune, Tropian Inc.
1:00-2:50

This presentation will focus on higher order issues for transmitter blocks not generally seen in textbooks. These are grouped into three areas: 1) effects of error sources in quadrature modulators and demodulators, 2) issues with on-channel RF signal processing (direct conversion/modulation), and 3) successful implementation of RF circuitry in the presence of local digital CMOS.

E1-4 - From RF System to Silicon
Asad A. Abidi, University of California, Los Angeles
3:10-5:00

Expertise in RF circuits traditionally concentrates on the design and optimization of individual circuit blocks, such as better amplifiers, mixers, or oscillators. Yet in the context of single-chip transceivers, the importance of the right architecture of receiver or transmitter usually has a much greater impact on performance and power consumption than improvements in any given circuit. Without sufficient thought to the architecture, even the best circuits may lead to an inferior end result. The practical problems of on-chip interconnections and buffering at RF are often overlooked.

In this presentation, we will use various examples to show this process at work. The examples include an adaptive 2.4 GHz linear receiver for wireless LAN, a 900 MHz receiver and transmitter for GSM, and a 900 MHz very low power receiver for paging usage.