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Session 23 - Interface Issues and Clock Generation
Chairman: Tadahiro Kuroda
Co-Chairman: Takayasu Sakurai
Included papers cover high-performance DLLs for clock
generation, high-speed interface circuits, and other
specialized I/O circuits.
1:30pm - Introduction
23.1 - 1:35pm
Clock Generator Using Factorial DLL for Video
Applications
J.-B.. Begueret, Y. Deval, O. Mazouffre, A. Spataro, P. Fouillat, E.
Benoit* and J. Mendoza*, University of Bordeaux, Talence, France and
*STMicroelectronics, Grenoble, France
Abstract :
This paper presents a clock generator dedicated to
front-end processors for LCD and PLASMA video
applications. The topology is based on a factorial DLL,
which can support all kind of standards (VGA to SXGA).
Fabricated in a 2.5-V 0.25um 6-metal CMOS VLSI process
from STMicroelectronics, the maximum rms measured jitter
is 17 ps.
23.2 - 2:00pm
A Fast-Lock Mixed-Mode DLL Using a 2-b SAR Algorithm
G-K.
Dehng, J-W. Lin and S-I. Liu, National Taiwan University, Taipei,
Taiwan, ROC
Abstract :
In this paper, a fast-lock mixed-mode DLL (MMDLL) is
presented. The digital part of the MMDLL utilizes a 2-b
SAR algorithm to achieve short lock time compared to the
conventional RDLL, CDLL and SARDLL, while the analog
part helps to reduce the static phase error and improve
the output clock jitter.
23.3 - 2:25pm
An ESD Protection Circuit for Mixed-Signal ICs
H. Feng. K.
Gong and A.Z. Wang, Illinois Institute of Technology, Chicago, IL
Abstract :
(not available)
23.4 - 2:50pm
7V Tristate-Capable Output Buffer Implemented in Standard
2.5V CMOS Process
V. Prodanov and V. Boccuzzi, Bell Labs, Lucent
Technologies, Murray Hill, NJ
Abstract :
(not available)
23.5 - 3:15pm
Shared Data Line Technique for Doubling the Data Transfer
Rate per Pin of Differential Interfaces
F. Hatori, S. Kousai and Y.
Unekawa, Toshiba Corporation Semiconductor Company, Kawasaki, Japan
Abstract :
A technique for almost doubling the data rate per pin of
the differential interfaces has been proposed. In this
technique the number of the differential transmission
lines between transmitter LSI and the receiver LSI are
shared with adjacent buffers to increase the transfer
rate per pin. Data rate of 1.1Gbps/pin has been
achieved.
23.6 - 3:40pm
A 2 GB/S High Speed Link with Differential Simultaneous
Bi-Directional IO
D. Cecchi, C. Hanson and C. Preuss, IBM Server Group,
Rochester, MN
Abstract :
(not available)
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Session 24 - Wireless Subsystems and Components
Chairman: John Van Saders
Co-Chairman: Earl McCune
Issues ranging from the impact of software radio on
component requirements to technology choices are
covered. Also included are papers covering system-level
issues, functional blocks, and RF components.
1:30pm - Introduction
24.1 - 1:35pm
Solutions for Highly Integrated Future Generation Software
Radio Basestation Transceivers (Invited)
A. Splett, H-J. Dressler, A.
Fuchs, R. Hofmann, B. Jelonnek, H. Kling, E. Koenig and A. Schultheiss,
Siemens AG, Ulm, Germany
Abstract :
This paper discusses transceiver technologies for future
mobile radio basestations. Software radio technology
places demanding requirements on both bandwidth and
dynamic range. Recent progress in delta-sigma
digital-to-analog converters is reported in which
multi-carrier CDMA signals can be directly converted to
RF with sufficient dynamic range for 3rd generation
mobile communications systems.
24.2 - 2:25pm
An Integrated RF Transceiver for DECT Application
S.
Cosentino, P. Filoramo, A. Granata, M.Marletta, G. Martino, R.
Pelleriti, F. Torrisi, M. Paparo, G. Cosentino, P. Vita and G.
Palmisano*, STMicroelectronics, Catania, Italy and *Università di
Catania, Catania, Italy
Abstract :
An integrated transceiver for DECT application is
presented which fully meets the ETSI approval tests. The
receiver is based on an image rejection architecture and
a direct-modulation is used for the transmitter. The IC
includes the PLL and integrated VCOs. It was fabricated
in a high performance 20-GHz silicon bipolar technology.
24.3 - 2:50pm
An IF FSK Demodulator for Bluetooth in 0.35um CMOS
H.
Darabi, S. Khorram, B. Ibrahim, M. Rofougaran and A. Rofougaran,
Broadcom Corporation, El Segundo, CA
Abstract :
An FSK demodulator intended for use in Bluetooth is
implemented in a 0.35um CMOS process. The entire
demodulator, integrated as a part of a low-IF receiver
with 2 MHz intermediate frequency, consumes 3 mA from
2.7 V supply. The required signal-to-noise ratio (SNR)
for 0.1% bit error rate (BER) is about 18 dB.
24.4 - 3:15pm
A 900 MHz, 0.9 V Low-Power CMOS Downconversion Mixer
C. Debono, F. Maloberti* and J. Micallef**, University
of Pavia, Pavia, Italy and *Texas A&M University,
College Station, TX and **University of Malta, Msida,
Malta
Abstract :
A low-voltage, low-power mixer operating at a supply
voltage of 0.9 V while consuming 4.7 mW is presented.
The circuit achieves the multiplication using current
mode processing. Moreover, non-conventional differential
pairs that don't require current tail generators are
utilized. The circuit has been fabricated in a standard
double-poly, triple-metal 0.35um CMOS process having a
threshold voltage of 0.6 V. Measurement results for 900
MHz and 800 MHz input signals indicate that the circuit
has an IIP3 of 3.5 dBm, a 1-dB compression point of -8
dBm and a noise figure of 13.5 dB.
24.5 - 3:40pm
A Comparison of CMOS and SiGe LNA's and Mixers for Wireless
LAN Application
X. Li, T. Brogan, B. Myers and K.K. O*, Intersil
Corporation, Palm Bay, FL and *University of Florida, Gainesville, FL
Abstract :
2.4-GHz CMOS LNA and mixer for high performance Wireless
LAN chipset fabricated in a 0.25um foundry digital CMOS
process were compared to the SiGe bipolar circuits using
the same topology and almost identical schematic. The
CMOS circuits were housed in the same package with the
same pinout, and tested on the same PC board under the
similar bias conditions as those for the SiGe bipolar
circuits. CMOS LNA and mixer can match the SiGe
performance with a 15 to 20% increase in power
consumption, and a direct migration from bipolar to CMOS
can be realized without major changes in circuits and
systems.
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Session 25 - Techniques Enabling IP Integration
Chairman: Thomas Zimmermann
Co-Chairman: Iraj Masarati
Design methodologies and a simulation framework to
integrate IP on a System-on-Chip are essential. This
session addresses new concepts that embed system-level
IP, standards and techniques for IP scalability.
1:30pm - Introduction
25.1 - 1:35pm
Interface Socket Design Methodology to Generate Embedded
DRAM Macros
R. Haga, T. Kaneko, A. Nakayama, S. Miyano, H. Takenaka, K.
Numata, H. Koinuma, T. Hojo, A. Sato, T. Kouchi, K. Mimoto, M. Tazawa,
T. Ohkubo, T. Andou and T. Amano, Toshiba Corporation, Kawasaki, Japan
Abstract :
A new design methodology for embedded DRAM is
introduced. The DRAM macro consists of common DRAM core
and interface socket. Splitting the DRAM macro into
common DRAM core and interface socket widens the
reconfigurability of the functions of the macro. An
experimental chip consists of 12M-bit DRAM core and
synchronous interface socket was developed with 0.18um
technology.
25.2 - 2:00pm
A Mixed-Signal, Functional Level Simulation Framework Based
on SystemC for System-on-a-Chip Applications
T.E. Bonnerud, B. Hernes* and T. Ytterdal*, Norwegian
Institute of Science and Technology, Trondheim, Norway
and *Nordic VLSI, Trondheim, Norway
Abstract :
In this paper, we describe a mixed-signal simulation
framework based on the SystemC C++ class libraries. By
adding an analog extension to SystemC, we have developed
a modular functional level simulation environment that
achieves comparable accuracy to MATLAB. We illustrate
the usability of the framework by presenting the results
of an investigation of the properties of a background
calibration technique for pipelined analog-to-digital
converters.
25.3 - 2:25pm
A Design Environment for High Throughput, Low Power
Dedicated Signal Processing Systems
W.R. Davis, N. Zhang, K. Camera, F.
Chen, D. Markovic, N. Chan, B. Nikolic and R.W. Brodersen, University of
California at Berkeley, Berkeley, CA
Abstract :
A hierarchical automated design flow for low-energy
direct-mapped signal processing integrated circuits is
presented. A modular framework based on a combined
Simulink and floorplan description drives automatic
layout generation. The flow is demonstrated on the
subsystems of CDMA and OFDM receivers and a 300k
transistor test-chip.
25.4 - 2:50pm
RTL Morphing: Making IP-Reuse Work in System-on-a-Chip
Designs
S. Yamashita, H. Chikata, Y. Onishi, N. Kato, T. Hiyama* and K.
Yano, Hitachi, Ltd., Tokyo, Japan and *Kanagawa, Japan
Abstract :
The proposed RTL morphing enables true IP-reuse design
through flexible control of RTL structure under the
changes in performance requirements or delay
constraints. The use of RTL morphing reduces the design
period of a time-to-market pressured SoC by two months
with 18% operating frequency improvement.
25.5 - 3:15pm
Cooperative Voltage Scaling (CVS) Between OS and
Applications for Low-Power Real-Time Systems
Y. Shin, H. Kawaguchi and
T. Sakurai, University of Tokyo, Tokyo, Japan
Abstract :
(not available)
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Session 26 - IC Process Technology for the Communications Revolution
Chairman: David Sunderland
Co-Chairman: Amjad Obeidat
Ever-increasing demand for bandwidth requires circuits
operating in the multi-GHz range. This session focuses
on scaling CMOS and SiGe BICMOS technologies, and the
integration of on-chip inductors.
1:30pm - Introduction
26.1 - 1:35pm
Silicon-Germanium BiCMOS Technology and CAD Environment for
2-40 GHz VLSI Mixed-Signal ICS (Invited)
S. Subbanna, L. Larson+, G. Freeman, D. Ahlgren, K.
Stein, C. Dickey*, J. Mecke*, A. Rincon*, P. Bacon**,
R. Groves, M. Soyuer***, D. Harame*, J. Dunn*, D.
Rowe++, W. Chon++, D. Herman*** and B. Meyerson***, IBM
Microelectronics, Hopewell Junction, NY and *Essex
Junction, VT and **Lowell, MA and ***IBM Research
Division, Yorktown Heights, NY and +IBM Research Center
of Excellence, Encinitas, CA and ++Sierra Monolithics,
Redono Beach, CA
Abstract :
SiGe BiCMOS technology provides a stable, ultra-high
performance, semiconductor technology capable of
supporting large mixed-signal VLSI circuit designs for a
variety of emerging communications applications. This
technology has been wedded to a CAD system that supports
a variety of high-performance circuit designs,
mixed-signal circuit block re-use, and the ability to
accurately predict circuit performance at the highest
frequencies. This paper will summarize the progress this
technology has made in recent years in moving from the
research laboratory into a production environment.
26.2 - 2:25pm
A 10 GHz SiGe BiCMOS Phase-Locked-Loop Frequency
Synthesizer
B-U.H Klepser, M. Schlolz and W. Klein, Infineon
Technologies, Munich, Germany
Abstract :
A SiGe BiCMOS Phase-Lock-Loop Circuit is presented. A
maximum operational frequency of 10 GHz and a current
consumption of 7.6 mA, i.e 17 mW is demonstrated. For a
9 mW low power version, a maximum frequency of 4.7 GHz
is determined. This demonstrates the speed and power
advantage of the SiGe BiCMOS technology for wireless
communications.
26.3 - 2:50pm
Driving CMOS into the Wireless Communications Arena with
Technology Scaling
K.W.J. Chew, S.-F.S. Chu and C.C.C. Long*, Chartered
Semiconductor Manufacturing Ltd., Singapore and *Institute of
Microelectronics, Singapore
Abstract :
This paper provides a review of the impact of technology
scaling on the radio-frequency (RF) performance of CMOS
devices. The major active and passive elements are
presented. Unity current gain frequency and unity power
gain frequency of greater than 50 GHz and 60 GHz
respectively have been achieved with the 180 nm
transistors. The minimum noise figure is less than 1.5
dB at 2.45 GHz for gate lengths of 250 nm and below. The
flicker noise spectra of thin- and thick-gate
transistors have risen by an order of magnitude due to
the effects of scaling and nitridation. Quality factors
(Q) close to 10 and Q-enhancement of greater than 50% at
2.45 GHz have been achieved using 2um thick top
aluminimum metal on circular stacked coil inductors.
26.4 - 3:15pm
A Completely Integrated 2GHz VCO with Post-Processed Cu
Inductors
J.W.M. Rogers, V. Levenets, C.A. Pawlowicz, N.G. Tarr, T.J.
Smy and C. Pett, Carleton University, Ottawa, Canada
Abstract :
A simple post-processing technique allowing Cu inductors
to be added to integrated circuits is presented. The
inductors use a 4um thick Cu layer, and are formed over
a 9um thick polyimide dielectric. VCOs with Cu
inductors gave a phase noise of -106 dBc/Hz at 100 kHz
offset from a 2 GHz carrier. In contrast, an identical
control circuit with Al inductors gave a phase noise of
only -101 dBc/Hz at 100kHz offset from a 1.8 GHz carrier
and had higher power consumption.
26.5 - 3:40pm
Micromachined High-Q Inductors in 0.18um Cu Interconnect
Low-K CMOS
H. Lakdawala, X. Zhu, H. Luo, S. Santhanam, L.R. Carely and
G.K. Fedder, Carnegie Mellon University, Pittsburgh, PA
Abstract :
Spiral inductors fabricated in a 0.18um Cu interconnect
low-K dielectric process suspended 100um above the
substrate with sidewall oxide removed are described. A
maskless micromachining process compatible to copper
interconnect CMOS has been developed. Inductor quality
factors of greater than 7 were obtained at 5.5 GHz.
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