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Session 19 - Modeling for RF Design
Chairman: Larry Nagel
Co-Chairman: Kathleen Krisch
RF design requires accurate models of active and passive
components. This session presents novel work on
modeling RF CMOS, noise, power transistors, and
transformers.
8:30am - Introduction
19.1 - 8:35am
When Do We Need Non-Quasistatic CMOS RF-Models?
E. Gondro,
O. Kowarik, G. Knoblinger* and P. Klein*, University of Bundeswehr,
Neubiberg, Germany and *Infineon Technologies AG, Munich, Germany
Abstract :
This paper presents criteria for the onset of NQS
effects derived from time transient device simulations
and S-parameter measurements. For the first time it has
been proved that e.g. a 10 um NMOS transistor can be
described up to 27 MHz and a 0.2 um device up to 46 GHz
by the quasistatic approach while the accuracy of the
description of the inversion layer charge is still 99 %.
19.2 - 9:00am
Methology of Self-Heating Free Parameter Extraction and
Circuit Simulation for SOI CMOS
H. Nakayama, P. Su*, C. Hu*, M.
Nakamura, H. Komatsu, K. Takeshita and Y. Komatsu, Sony Corporation,
Atsugi, Japan and *University of California, Berkeley, CA
Abstract :
Novel SOI Model parameter extraction methodology is
proposed and demonstrated for a 0.18um SOI technology.
In this methodology, prior to parameter extraction, the
current loss due to SHE is added back to dc IV data. Dc,
ac, and transient simulation results using this
technology show good agreement with measurement data.
19.3 - 9:25am
Comparative Low Frequency Noise Analysis of Bipolar and MOS
Transistors Using an Advanced Complementary BiCMOS
Technology
J.A.
Babcock, B. Loftin, P. Madhani, X. Chen, A. Pinto and D.K. Schroder*,
Texas Instruments, Freising, Germany and *Arizona State University,
Tempe, AZ
Abstract :
1/f noise in both bipolar and MOS transistors is
compared using CBiCMOS technology on thick film SOI.
For MOS devices, a new relationship for 1/f noise is
given which allows intuitive insight when comparing
technologies. Bipolar transistors indicate an order of
magnitude lower noise level when compared to MOSFETs
under similar drive currents and active area conditions.
19.4 - 10:05am
A New Analytical Model for High Frequency MOSFET Noise
S.
Donati Guerrieri, F. Bonani, G. Ghione and M.A. Alam*, Politecnico Di
Torino, Torino, Italy and *Bell Labs, Lucent Technologies, Murray Hill,
NJ
Abstract :
A new analytical model for high frequency MOSFET noise
is presented and validated against numerical
physics-based 2D noise simulations, both for long and
short gate devices. The noise model can be readily
implemented into standard compact models. The impact of
the high field diffusivity behavior on drain noise is
discussed.
19.5 - 10:30am
Experimental Study on MOSFETs Flicker Noise Under Switching
Conditions and Modelling in RF Applications
Z. Zhang and J. Lau, Hong
Kong University of Science and Technology, Hong Kong, China
Abstract :
The flicker noise mechanism under switching conditions
is studied. Experimental results show that the baseband
flicker noise is a superposition of upconverted gate
flicker noise at each harmonic of the output current.
Methods to reduce the flicker noise are discussed. Based
on the measured results, the large signal flicker noise
model for RF applications under switching conditions is
proposed and validated by simulations and measurements.
With the proposed model, the noise performance of a
single-balanced gilbert mixer for direct conversion
applications is analysed and discussed.
19.6 - 10:55am
A New Dynamic, Self-Consistent Electro-Thermal Model of
Power HBTs and a Novel Interpretation of Thermal Collapse Loci in
Multi-Finger Devices
F. Cappelluti, F. Bonani, S. Donati Guerrieri, G.
Ghione, M. Peroni*, A. Cetronio* and R. Graffitti*, Politecnico di
Torino, Torino, Italy and *Alenia Marconi Systems, Rome, Italy
Abstract :
A self-consistent dynamic electro-thermal model for
power HBTs is presented coupling a circuit-oriented
electrical model fitted on experimental data with a full
frequency domain thermal model. Self-consistency is
achieved through Harmonic Balance analysis. A new
interpretation is proposed for the thermal collapse loci
of such devices in terms of bifurcations.
19.7 - 11:20am
Modeling of Monolithic Lumped Planar Transformers up to 20
GHz
D. Kehrer, W. Simbürger*, H-D. Wohlmuth* and A. L. Scholtz,
šInstitute für Nachrichtentechnik und Hochfrequenztechnik, Vienna,
Austria and *Infineon Technologies AG, Munich, Germany
Abstract :
A new method for characterization of monolithic lumped
planar transformers is proposed in this paper. A lumped
low-order equivalent model is derived from the physical
layout using a new expression for the substrate loss.
Two transformers are considered in detail, showing
excellent agreement between simulation and measurement.
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Session 20 - Innovations in SOC Applications and Technologies
Chairman: Jim Lipman
Co-Chairman: Nitin Deo
Insights into process technologies and advanced
system-level design methodologies lay the foundation for
five consumer and communication SoC applications.
8:30am - Introduction
20.1 - 8:35am
Successful Modular Process Technology for System-on-a-Chip
Applications (Invited)
W.T. Cochran, Lucent Technologies, Orlando, FL
Abstract :
By traditional standards, virtually all state-of-the-art
technology offerings are modular. Keys to successful
development of modular process technology are reviewed.
Examples of modular process technology usage for the
VLSI system chips are given. Cost/benefit issues are
examined and the future of modular process technology
and system-on-a-chip design is explored.
20.2 - 9:25am
A System-on-Chip for Pressure-Sensitive Fabric
M. Sergio,
N. Manaresi, M. Tartagni, R. Canegallo* and R. Guerrieri, University of
Bologna, Bologna, Italy and *STMicroelectronics, Milan, Italy
Abstract :
This paper presents a mixed-signal system-on-chip (SOC)
for decoding the pressure exerted over a large piece of
smart fabric. The image map of the pressure applied over
the fabric surface is achieved by detecting the
capacitance variation between rows and columns of
conductive fibers patterned on the two opposite sides of
an elastic layer, like synthetic foam. The SOC approach
allows to reduce design time maintaining the flexibility
to accommodate for different sensor sizes and to perform
some image enhancement such as fixed pattern noise
compensation and gamma correction. The chip has been
designed in a 0.35um 5LM CMOS process to work at 40MHz,
3.3V power supply, in a fully reconfigurable arrangement
of 128 rows and columns. The core area is 32 mm2.
20.3 - 10:05am
A Single Chip Terminal Solution for High-End Telephone
Applications
V. Nair, M. Erdmann, S. Mishra, J. Povazanec, A. Shaligram
and H-C. Feng, Infineon Technologies, Singapore
Abstract :
The single chip telephone IC, INCA, integrates all the
functions necessary for a digital voice and data
terminal. Key feature of the chip is a smart acoustic
echo cancellation and suppression algorithm. Different
digital interfaces allow connection to a variety of
devices. The INCA is a 0.35(, 3.3V CMOS device.
20.4 - 10:30am
A One Chip Super Graphic CPU with Direct Unified Memory
Controller Suitable for Car Information and Control
System
Y.
Nakatsuka, T. Shimomura, Y. Morita, K. Takami, M. Joh, M. Narita, K.
Yamagishi*, Y. Okada* and J. Satoh*, Hitachi, Ibaraki-ken, Japan and
*Tokyo, Japan
Abstract :
(not available)
20.5 - 10:55am
A 99-mm2, 0.7-W, Single-Chip MPEG-2 422P@ML Video,
Audio, and System Encoder with a 64-Mbit Embedded DRAM
for Portable 422P@HL Encoder System
S. Kumaki, H. Takata, Y. Ajioka, T. Ooishi, K. Ishihara,
A. Hanami, T. Tsuji, Y. Kanehira, T. Watanabe, C.
Morishima, T. Yoshizawa, H. Sato*, S-I. Hattori*, A.
Koshio**, K. Tsukamoto and T. Matsumura, Mitsubishi
Electric Corp., Hyogo, Japan and *Kanagawa, Japan and
**Kyoto, Japan
Abstract :
A scalable single-chip 422P@ML MPEG-2 video, audio, and
system encoder LSI for portable 422P@HL system is
described. The encoder LSI is implemented using 0.13um
embedded DRAM technology. It integrates 3-M logic gates
and 64-Mbit DRAM in an area of 99-mm2. The power
consumption is suppressed to 0.7-Watts by adopting a low
power DRAM core. It performs real-time 422P@ML video
encoding, audio encoding, and system encoding with no
external DRAM. Furthermore, the encoder LSI realizes a
422P@HL video encoder with multi-chip configuration, due
to its scalable architecture. This results in a PC-card
size 422P@HL encoder with lowest power consumption for
portable HDTV codec system.
20.6 - 11:20am
The First Near Zero-IF RX, 2-Point Modulation TX CMOS
SOC Bluetooth Solution
C. Dürdodt1,**, M. Friedrich1, C. Grewing1, M. Hammes1,
A. Hanke1, S. Heinen1, J. Oehm1, D. Pham-Stäbner1, D.
Seippel1, D. Theil* and S. van Waasen1, 1Infineon
Technologies AG, Düsseldorf, Germany and *University of
Dortmund, Germany and **University of Bochum, Germany
Abstract :
The proposed new low cost concept for a "CMOS System On
Chip (SOC) Bluetooth Solution" is called
"BlueMoonSingle". The BlueMoonSingle includes the
Baseband-Part as well as the RF-Part of a Bluetooth
system. Aspects of the analog/digital RF-Part of the
BlueMoonSingle are introduced.
20.7 - 11:45am
C++ Based System Design of a 72 Mb/s OFDM Transceiver for
Wireless LAN (Invited)
D. Verkest, W. Eberle, P. Schaumont, B.
Gyselinckx and S. Vernalde, IMEC, Leuven, Belgium
Abstract :
This paper describes the system-level design process of
a 72 Mb/s OFDM transceiver for 5 GHz wireless-LAN
realized in 0.18um CMOS. Starting from a high-level C++
specification and using a set of class libraries,
architectural trade-offs can be easily explored.
Automated HDL-code generation creates the link to
standard synthesis tools.
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Session 21 - Analog Techniques
Chairman: Yusuf Haque
Co-Chairman: Jose Cruz-Albrecht
Following an overview of behavioral simulation are
papers covering implementations of a high-speed driver,
transconductors, and circuits for sub-1V operation.
8:30am - Introduction
21.1 - 8:35am
Behavioral Modeling of Analog and Mixed Signal ICs: Case
Studies of Analog Circuit Simulation Beyond SPICE
(Invited)
A. Abidi,
University of California, Los Angeles, CA
Abstract :
Modern analog microsystems on a chip are too
heterogeneous to be conveniently simulated by SPICE.
Increasingly, simulators offer the ability to simulate
SPICE-like constructs with abstract behavioral models.
We report on experience with behavioral models in the
development and verification of A/D Converters, Disk
Drive Read Channels, and Frequency Synthesizers.
21.2 - 9:25am
A SOI-BiCMOS 800Mbps Write Driver for Hard Disk Drives
N.
Fujii, M. Kuraishi, T. Mochizuki, S. Irikura and T. Hirose, Hitachi,
Ltd., Tokyo, Japan
Abstract :
A current-driver write driver for a +5/-5 V preamplifier
is described in this paper. This IC, which incorporates
RC load for harmonic oscillation to enlarge the voltage
swing across the head and Super Push-Pull Logic (SPL),
drives the write driver with a good rise/fall time. This
write driver, built with a 0.35um SOI-BiCMOS process,
has demonstrated a rise-time as short as 0.45 ns with a
160 mA peak-to-peak output write current.
21.3 - 10:05am
A Transimpedance Amplifier With DC-Coupled Differential
Photodiode Current Sensing For Wireless Optical
Communications
B. Zand,
K. Phang and D.A. Johns, University of Toronto, Toronto, Ont., Canada
Abstract :
A transimpedance amplifier with differential dc-coupled
photodiode current sensing was integrated in a standard
0.35um CMOS. It achieves 33Kohm transimpedance gain and
a bandwidth of 255 MHz with a 2pF photodiode
capacitance. This design exhibits 40dB power supply
rejection ratio and an average input noise of 6.8
pA/rtHz. Power dissipation is 30mW from a 3V supply.
21.4 - 10:30am
A 3.3V Transconductor in 0.35um CMOS with 80dB SFDR up to
10MHz
U. Chilakapati, T. Fiez* , A. Eshraghi**, Innocomm Wireless, San
Diego, CA, *Oregon State University, Corvallis, OR and **IBM
Microelectronics, Lowel, MA
Abstract :
A CMOS transconductor uses resistors at the input and an
OTA in unity-gain feedback to achieve 80dB SFDR for
3.6Vpp differential inputs up to 10MHz. The
transconductance core dissipates 10.56mW from a 3.3V
supply and occupies 0.4mm2 in a 0.35um CMOS process.
21.5 - 10:55am
Band-Gap References for Near 1-V Operation in Standard
CMOS Technology
A. Pierazzi, A. Boni and C. Morandi, University of
Parma, Parma, Italy
Abstract :
This paper presents two novel implementations of the
current-mode band-gap reference (BGR) which support the
very low supply voltages of the near future CMOS
technologies, without resorting to special devices.
Moreover the problem of the start-up of low-voltage BGRs
is discussed and a simple solution which guarantees
correct start-up over process, supply voltage and
temperature variations is proposed. The band-gap
references were implemented in a conventional 0.35um
CMOS technology and provides an output voltage of about
500 mV.
21.6 - 11:20am
A 0.9V, 0.5uA Rail-to-Rail CMOS Operational Amplifier
T. Stockstead and H. Yoshizawa*, Gain Technology,
Phoenix, AZ and *Seiko Instruments Inc., Chiba, Japan
Abstract :
A 0.9V, 0.5uA, rail-to-rail CMOS operational amplifier
designed with weak inversion techniques is presented.
Depletion-mode NMOS transistors buffer a bulk-driven
PMOS differential pair to realize wide input dynamic
range, while the output stage architecture provides
symmetric rail-to-rail output drive through the use of a
low voltage translinear control circuit.
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Session 22 - A Modeling Standard for IP
Chairman: Mike Beunder
Co-Chairman: Rakesh Patel
The challenge of integrating an IP block is simplified
by using a formal language, ALF. An invited paper will
explain the ALF standard. A subsequent panel discussion
will cover application examples of ALF as well as
current and future challenges.
8:30am - Introduction
22.1 - 8:35am
Coherent Functional, Electrical and Physical Modeling of IP
Blocks Using ALF (Invited)
W. Roethig, NEC Electronics, Santa Clara, CA
Abstract :
This paper describes the principles of the Advanced
Library Format (ALF) and its benefits for the usage in a
SOC design flow with IP blocks. The ALF description
capabilities for canonical function specification,
electrical characterization for timing, power, signal
integrity and physical description for hierarchical
design are shown.
22.2 - 9:25am
Special Panel on ALF/OLA
Moderator: Mike Beunder, Philips Semiconductor
Panelists: Representatives of: Philips Semiconductors, NEC, SI2,
Silicon Metrics, LSI Logic, IBM Microelectronics,
Cadence
Abstract :
The EDA Industry has been notoriously failing in
standardization efforts. Some of the most common formats
used in the EDA world (e.g. GDS II, Spice netlist)
originate from the earlier days of IC development, some
20 years or more ago. Newer developments often lead to
fractured support, multiple standards and/or dialects to
appear. OLA (and ALF as a precursor), a new standard
which has been under development for some time, is
starting to see some signs of more widespread
application. This panel will address the merits of the
OLA standard and the chances of this standard becoming
another car wreck on the side of the EDA road(map).
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