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Session 14 - Wired Gigabit Interfaces
Chairman: Jerry Molnar
Co-Chairman: Kris Iniewski
Two invited papers feature integrated solutions for the
electro-optical physical interface for gigabit
transmission. The remaining papers focus on advanced PLL
and clock-generation techniques.
2:00pm - Introduction
14.1 - 2:05pm
Design of High-Speed Circuits for Optical Communication
Systems (Invited)
B. Razavi, University of California, Los Angeles, CA
Abstract :
(not available)
14.2 - 2:55pm
A 9.8 - 11.5 GHz Quadrature Ring Oscillator for Optical
Receivers
J. van der Tang, D. Kasperkovitz* , A. van Roermund,
University of Technology, Eindhoven, Netherlands and *Philips Research
Labs, Eindhoven, The Netherlands
Abstract :
A 9.8 - 11.5 GHz quadrature ring oscillator for use in
the data clock recovery circuit of optical receivers has
been realized in a BiCMOS technology with 30 GHz cut-off
frequency. Carrier to noise ratios better than 94
dBc/Hz at 2 MHz offset are measured with 75 mW
dissipation and 2.7 V supply voltage. A state-of-the-art
oscillation frequency over transistor cut-off frequency
ratio of 0.38 is achieved.
14.3 - 3:35pm
A 1.0V GHz Range 0.13um CMOS Frequency Synthesizer
L. Sun
and D. Nelson, Lucent Technologies, Bell Laboratories, Allentown, PA
Abstract :
A 0.13um CMOS user programmable PLL frequency
synthesizer is designed to operate at low voltage
(1.0-1.8V) and cover a wide range of operating
frequencies for multiple applications. This design
incorporates low voltage circuits and a digital
auto-trimming scheme which calibrates the center
frequency of VCO and limits the VCO gain variation for
stability and reduced jitter over all process and
temperature conditions. The maximum frequency is 1.25
GHz and 2.85 GHz at 1.0V and 1.8V supply voltages,
respectively. Period jitter at 1GHz output is 4.9ps(rms)
and 45.8ps(p-p) with a power consumption of 3.9mW for
1.0V supply.
14.4 - 4:00pm
Circuits and Technologies for Highly Integrated Optical
Networking ICs at 10 GB/s to 40 GB/s (Invited)
S. Voinigescu, P.
Popescu, P. Banens, M. Copeland, G. Fortier, K. Howlett, M. Herod, D.
Marchesan, J. Showell, S. Szilagyi, H. Tran and J. Weng, Quake
Technologies, Ottawa, Ont., Canada
Abstract :
This paper presents a comparative overview of the
performance of Si CMOS, SiGe BiCMOS and III-V
technologies for 10-40Gb/s fiber-optic applications.
Active and passive device performance and building block
requirements, as well as on-chip isolation issues are
first addressed. Finally, a sub 2.5W, highly integrated
10Gb/s SiGe BiCMOS implementation of a 10Gb/s to 622Mb/s
transceiver is described in detail. The transceiver
achieves the highest level of integration, providing EOI
(electro-optical-interface) and SerDes
(Serializer-Deserializer) functions.
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Session 15 - Modeling for Analog Design
Chairman: Steffen Rochel
Co-Chairman: Colin McAndrew
This session addresses topics critical for analog and
mixed-signal design, including technology-scaling
limitations; behavioral modeling and simulation; and
mismatch.
2:00pm - Introduction
15.1 - 2:05pm
Speed-Power-Accuracy Trade-Off in High-Speed ADC's: What
about Nano-Electronics?
K. Uyttenhove and M. Steyaert, Katholieke
Universiteit Leuven, Heverlee, Belgium
Abstract :
In this article the fundamental trade-off between speed,
power and accuracy for high-speed converters is reviewed
with respect to technology scaling. The never-ending
story of technology trends towards smaller transistor
dimensions has resulted to date in deep sub-micron
transistors with lower supply voltages. It will be shown
that in future technologies the power consumption of
high-speed ADC's will increase to achieve the same
accuracy and speed.
15.2 - 2:30pm
Autocorrelation Analysis of Distortion Generated from
Bandpass Nonlinear Circuits
K. Gard, L.E. Larson* and M. B. Steer**,
Qualcomm CDMA Technologies Inc., San Diego, CA and *University of
California, San Diego, CA and **North Carolina State University,
Raleigh, NC
Abstract :
(not available)
15.3 - 2:55pm
Dedicated System-Level Simulation of Delta-Sigma Modulators
K. Francken, M. Vogels and G. Gielen, Katholieke
Universiteit Leuven, Heverlee, Belgium
Abstract :
A new approach is presented for significantly speeding
up system-level simulation of Delta-Sigma modulators.
The method is based on high-level simulation that can be
combined with an acceleration algorithm and has been
implemented in C. Also, the decimator has been included
yielding a complete and fast simulation of the whole
converter. This reduces the bottleneck seen in
system-level simulation of complete systems, e.g.
receiver front-ends. Different topologies are included
as well as the effects of most important nonidealities.
Experimental results show the effectiveness of the
approach.
15.4 - 3:35pm
Behavioral Modeling for Timing, Noise, and Signal Integrity
Analysis
J.D. Hayes and L. Wissel, IBM Microelectronics, Essex
Junction, VT
Abstract :
(not available)
15.5 - 4:00pm
Test-Circuit-Based Extraction of Inter- and Intra-Chip
MOSFET-Performance Variations for Analog-Design
Reliability
S. Matsumoto, H.J. Mattausch, S. Ooshiro, Y. Tatsumi,
M. Miura-Mattausch, S. Kumashiro*, T. Yamaguchi*, K.
Yamashita* and N. Nakayama*, Hiroshima University,
Hiroshima, Japan and *Semiconductor Technology Academic
Research Center, Tokyo, Japan
Abstract :
We propose an efficient, test-circuit-based method to
determine not only CMOS-device-parameter variations but
to simultaneously separate intra-chip from inter-chip
variations. The method is demonstrated by using a
differential-amplifier stage with feed-back coupling as
the test-circuit and the drift-diffusion MOSFET model
HiSIM for the circuit simulation.
15.6 - 4:25pm
A Fast Method for Identifying Matching-Relevant Transistor
Pairs
F. Schenkel, M. Pronath, H. Graeb and K. Antreich, Technical
University of Munich, Munich, Germany
Abstract :
This paper presents a new method to identify
mismatch-relevant transistor pairs on the circuit level.
It consists in a two-stage selection process that is
derived from a sensitivity-based formulation of mismatch
relevancy and is thus very fast. The presented results
show the efficiency and effectiveness of the method.
15.7 - 4:50pm
Capacity Limits and Matching Properties of Lateral Flux
Integrated Capacitors
R. Aparicio and A. Hajimiri, California Institute
of Technology, Pasadena, CA
Abstract :
Theoretical limits for the capacitance density of any
capacitive structure are presented. These theoretical
upper bounds lead to two new capacitor structures with
high lateral-field efficiency. Simulation and
experimental results demonstrate higher capacitance
density and superior matching properties compared to the
standard Horizontal Parallel Plate and previously
reported lateral-flux capacitors.
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Session 16 - Afternoon Panel Session - "Will the Real Network
Processor Please Stand up?"
2:00pm
Moderator: Elliot Gould, C-Port Corporation
Panelists:
Robert Blake, Vice President Product Planning, Altera
Dave Husak, CTO, C-Port Corporation
Jeff Lawrence, CTO Network Communications Group, Intel Corp.
Rex Naden, Exec VP and COO, Silicon Access Networks
David Sonnier, CTO, Network Processors & Switch Division, Agere Systems
Rick Merritt, Editor-in-Chief, EETimes
Network processors are revolutionizing the networking
industry. Today's networking products are based on
hardware designed for a relatively fixed task. Network
Processors claim to change this whole model by enabling
the vendors to modify the personality of a product
simply by downloading new software and perhaps adding a
different physical interface. The advantage to vendors
is clear: faster time-to-market and lower cost of
development. The advantage to their customers is also
compelling - products will last much longer in the
market place because new features and standards can be
added via software as the needs change.
Over the last two years, many companies have announced
chip offerings that claim to be Network Processors,
ranging from highly configurable chips to architectures
with full-blown programmability. But which one is best
for the market? Will one emerge as the standard and
become the x86 of the network world? Will network
processors eliminate other approaches, such as ASICs,
DSPs, and PLDs, or will they co-exist with them and
capture only a niche market? This panel discussion will
explore the various network processor offerings
available today, and contrast and compare them to
highlight their various strengths and weaknesses in
order to educate the audience on the network processor
market.
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