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Session 10 - Frequency Synthesizers and VCOs
Chairman: Peter Kinget
Co-Chairman: Francesco Svelto
VCO realizations for Bluetooth, 900/1800 MHz, low-noise
bias, and amplitude control are described. Also covered
are frequency synthesizer implementations: a low-gain,
low-jitter PLL, and a waveform converter technique for
wideband applications.
8:30am - Introduction
10.1 - 8:35am
A 2.2 GHz CMOS VCO with Inductive Degeneration Noise
Suppression
P. Andreani and H. Sjöland, Lund University, Lund, Sweden
Abstract :
A 1.4 V, 9 mA monolithic LC-tank voltage-controlled
oscillator (VCO) fabricated in a standard 0.35um CMOS
process is presented. The VCO is tunable between 2.0 GHz
and 2.37 GHz, and displays a phase noise between -140
dBc/Hz and -138 dBc/Hz at a 3 MHz offset frequency
across the whole tuning range. This low phase noise is
achieved through the use of an on-chip LC filter and an
off-chip low frequency inductor, which totally remove
the noise of the tail current source. The phase noise
improvement due to the off-chip inductor is between 2 dB
and 6 dB, increasing with higher oscillation
frequencies.
10.2 - 9:00am
A -94dBc/Hz@100kHz, Fully-Integrated, 5-GHz, CMOS VCO with
18% Tuning Range for Bluetooth Applications
C. Samori, S. Levantino and
V. Boccuzzi, Agere Systems, Lucent Technologies, Murray Hill, NJ
Abstract :
(not available)
10.3 - 9:25am
Demonstration of a Switched Resonator Concept in Dual-Band
Monolithic CMOS LC-Tuned VCO
S-M. Yim and K.K. O, University of
Florida, Gainesville, FL
Abstract :
A switched resonator concept which allows better
trade-off between phase noise and power consumption is
demonstrated using a dual-band VCO. The dual-band VCO
operates near 900 MHz and 1.8 GHz with phase noise of
-125 and -123 dBc/Hz at a 600-KHz offset and 16-mW power
consumption. Compared to a single band 1.8GHz VCO, the
dual-band VCO has almost the same phase noise and power
consumption.
10.4 - 10:05am
Automatic Amplitude Control Loop for a 2-V, 2.5-GHz
LC-Tank VCO
A. Zanchi, A. Bonfanti*, S. Levantino*, C. Samori* and A.L.
Lacaita*, Texas Instruments, Dallas, TX and *Politecnico di Milano,
Milano, Italy
Abstract :
Design techniques for the automatic amplitude control
loop (AAC) for wireless oscillators are discussed,
presenting a 2-V, 2.5-GHz bipolar VCO. The
fully-integrated LC-tank oscillator manufactured has
Q-factor about 8, and dissipates 14mW with
SSCR=-104dBc/Hz@100kHz, showing the highest normalized
performance published to date for Si/SiGe, standalone or
AAC-equipped, bipolar VCOs.
10.5 - 10:30am
A 0.10um CMOS, 1.2V, 2GHz Phase-Locked Loop with Gain
Compensation VCO
K. Minami, M. Fukaishi, M. Mizuno, H. Onishi, K. Noda,
K. Imai, T. Horiuchi, H. Yamaguchi, T. Sato, K. Nakamura
and M.Yamashina, NEC Corporation, Kanagawa, Japan
Abstract :
A 1.2-V, 2-GHz low-jitter phase-locked loop (PLL) using
a gain compensation has been developed. The VCO
achieves a low gain and a linear V-f characteristic by
using three V-I converters. The PLL is fabricated in
0.10-um CMOS technology. At 1.2V, 2-GHz operation,
measured rms and peak-to-peak jitter of the PLL are 2.8
and 21 ps, respectively.
10.6 - 10:55am
A CMOS VLSI Delay Oriented Waveform Converter Dedicated to
the Synthesizer of an UMTS Transceiver
A. Spataro, Y. Deval, J.-B..
Bégueret, P. Fouillat and D. Belot*, Université Bordeaux, Talence,
France and *STMicroelectronics, Crolles, France
Abstract :
In this paper we presents a waveform converter
implemented on a 0.25um CMOS technology using a
dedicated design methodology (Delay Oriented Design).
The circuit converts a square wave signal in both
in-phase and quadrature-phase sinusoidal differential
outputs. It also multiplies the frequency by seven. The
output frequency range of this converter extends from
1.05GHz up to 2.17GHz. This converter is dedicated for
the design of a third generation mobile phone
synthesizer using a double loop architecture. For an
output frequency of 2GHz, the measured phase noise at
10kHz offset from the carrier is -97dBc/Hz. The circuit
consumes 50mW from a 2.5V supply.
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Session 11 - Modeling for High-Speed Digital Design
Chairman: Paul Wiley
Co-Chairman: Hidetoshi Onodera
Papers cover two topics that high-speed digital
designers must consider: the effects of process
variations on signal delays and methods to account for
inductance.
8:30am - Introduction
11.1 - 8:35am
Modeling and Analysis of Manufacturing Variations
(Invited)
S.R. Nassif, IBM Austin Research Laboratory, Austin, TX
Abstract :
Process-induced variations are an important
consideration in the design of integrated circuits.
Until recently, it was sufficient to model die-to-die
shifts in device performance, leading to the well known
worst-case modeling and design methodology. However,
current and near-future integrated circuits are large
enough that device and interconnect parameter variations
within the die are as important as variations from die
to die. This presents a new set of challenges for
process modeling and characterization and for the
associated design tools and methodologies.
This paper examines the sources and trends of process
variability, the new challenges associated with the
increase in within-die variability analysis, and
proposes a modeling and simulation methodology to deal
with this variability.
11.2 - 9:25am
Impact of Within-Die Parameter Fluctuations on Future
Maximum Clock Frequency Distributions
K.A. Bowman and J.D. Meindl,
Georgia Institute of Technology, Atlanta, GA
Abstract :
(not available)
11.3 - 10:05am
Effects of Non-Uniform Substrate Temperature on the Clock
Signal Integrity in High Performance Designs
A.H. Ajami, M. Pedram and
K. Banerjee*, University of Southern California, Los Angeles, CA and
*Stanford University, Stanford, CA
Abstract :
This paper presents the analysis and modeling of the non-uniform
substrate temperature in high performance ICs and its effect on the
integrity of the clock signal. Using a novel non-uniform
temperature-dependent distributed RC interconnect delay model, the
behavior of clock skew in presence of the substrate thermal gradients is
analyzed and some design guidelines are provided to ensure the integrity
of the clock signal.
11.4 - 10:30am
R(f)-L(f)-C Coupled Noise Evaluation of An S/390
Microprocessor Chip
H. Smith, A. Deutsch*, S. Mehrotra**, D. Widiger**,
M. Bowen, A. Dansky, G. Kopcsay*, B. Krauter**, IBM, Poughkeepsie, NY
and *Yorktown Heights, NY and **Austin, TX
Abstract :
A coupling noise evaluation of a high performance S/390
microprocessor using a full chip RLC extraction and
simulation process is presented. Review of on-chip
wiring guidelines with respect to the inaccuracies of an
RC coupling evaluation for known net topologies is
discussed in terms of tool requirements for full-chip
noise evaluation which include inductive coupling
effects. The extraction and simulation approach is
described in terms of algorithms and procedures used to
account for the frequency dependent RLC effects in a
manner that allow a full chip noise evaluation. Results
are presented which compare noise amplitude differences
between RC and R(f)L(f)C evaluations for the wiring data
of a S/390 microprocessor as well as pertinent
statistics such as run times and memory usage.
11.5 - 10:55am
A Fast Analytical Technique for Estimating the Bound of
On-Chip Clock Wire Inductance
Y-C. Lu, K. Banerjee, M. Celik* and R.W.
Dutton, Stanford University, Stanford, CA and *Monterey Design Systems,
Sunnyvale, CA.
Abstract :
Accurate integrity assessment of on-chip clock lines is
difficult without any a priori knowledge about their
inductance at an early stage in the clock design
process. This paper introduces an efficient approach to
estimate the bounds of on-chip clock wire inductance at
the very beginning of the design stages. With this
information, more accurate waveforms along the clock
distribution networks can be obtained thus greatly
reducing the overall length of design cycles.
11.6 - 11:20am
Circuit-Aware On-Chip Inductance Extraction
H.Hu and S.
Sapatnekar, University of Minnesota, Minneapolis, MN
Abstract :
(not available)
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Session 12 - Design Approaches for Testability and Reliability
Chairman: Mark Young
Co-Chairman: Norman Abt
Addressing test and reliability issues early in the
design process is the focus of papers covering process
definition, RTL coding style, built-in test circuits,
and enhanced design techniques.
8:30am - Introduction
12.1 - 8:35am
Circuits for On-Chip Sub-Nanosecond Signal Capture and
Characterization
N. Abaskharoun and G.W. Roberts, McGill University,
Montreal, Canada
Abstract :
(not available)
12.2 - 9:00am
Effect of RTL Coding Style on Testability
Y. Huang, C-C.
Tsai*, N. Mukherjee*, W-T. Cheng* and S.M. Reddy, University of Iowa,
Iowa City, IA and *Mentor Graphics Corporation, Wilsonville, OR
Abstract :
This paper illustrates the effect of functional Register
- Transfer - Level (RTL) coding styles on the
testability of synthesized gate-level circuits. Thus,
the advantage of having a RTL code analyzer to reduce
the number of untestable faults, thereby improving the
overall testability of a design is presented. In
addition, it has been also observed that writing
efficient RTL code to improve testability reduces the
total silicon area of the gate-level circuit as well.
12.3 - 9:25am
A Deterministic Scan-BIST Architecture with Application to
Field Testing of High-Availability Systems
S. Swaminathan and K.
Chakrabarty*, IBM Microelectronics, Research Triangle Park, NC and *Duke
University, NC
Abstract :
We propose an autonomous, deterministic scan-BIST
architecture that allows compact, pre-computed test sets
with complete fault coverage to be used for field
testing. The use of such short test sequences is
desirable in safety-critical systems since it reduces
the error latency. It also reduces testing time and
therefore allows periodic field testing to be carried
out with low system downtime. We synthesize the BIST
logic for several ISCAS 89 benchmarks and industrial
circuit modules and show that the BIST overhead is low
in all cases. The proposed can also be efficiently used
with a mixed-mode BIST strategy.
12.4 - 10:05am
Low-Cost, Software-Based Self-Test Methologies for
Performance Faults in Processor Control Subsystems
S. Almukhaizim, P. Petrov and A. Orailoglu, University
of California, San Diego, La Jolla, CA
Abstract :
A software-based testing methodology for processor
control subsystems, targeting hard-to-test performance
faults in high-end embedded and general-purpose
processors, is presented. An algorithm for directly
controlling, using the instruction-set architecture
only, the branch-prediction logic, a representative
example of the class of processor control subsystems
particularly prone to such performance faults, is
outlined. Experimental results confirm the viability of
the proposed methodology as a low-cost and effective
answer to the problem of hard-to-test performance faults
in processor architectures.
12.5 - 10:30am
An Efficient Method of Applying Hot-Carrier Reliability
Simulation to Logic Design
H. Sato, M. Ohtsuka, K. Yanagisawa, P.M.
Lee, Hitachi, Ltd., Tokyo, Japan
Abstract :
(not available)
12.6 - 10:55am
Design for Manufacturability Characterization and
Optimization of Mixed-Signal IP
P. McNamara, S. Saxena, C. Guardiani,
H. Taguchi*, E. Yoshida*, N. Takahashi*, K. Miyamoto*, K. Sugawara* and
T. Matsunaga*, PDF Solutions, San Jose, CA and *Toshiba Corporation,
Yokohama, Japan
Abstract :
This paper presents results of applying a statistically
based parametric yield modeling approach to quantify
current manufacturing yield and potential yield
improvement of mixed-signal blocks. This design for
manufacturability methodology is used to statistically
characterize and quantify parametric yield optimization
of a 2-channel 9-bit DAC manufactured in a 0.4um CMOS
process. Parametric yield loss characterization and
optimization are validated in silicon to be 15% and 4%,
respectively.
12.7 - 11:20am
Design Methodology of High Performance Microprocessor
using Ultra-Low Threshold Voltage CMOS
T. Miyake, T. Yamashita, N.
Asari, H. Sekisaka, T. Sakai, K. Matsuura, A. Wakahara, H. Takahashi, T.
Hiyama*, K. Miyamoto* and K. Mori, Hitachi Ltd., Tokyo, Japan and
*Kanagawa, Japan
Abstract :
A new design methodology of high performance CMOS MPU
that applies ultra-low VTH is discussed. The multi-VTH,
the back-bias control, IDDQ measurement at low
temperature and IDDQ are applied to speedup without
increasing IDDQ leakage. Operation frequency of our
64bit MPU was improved 340MHz to 560MHz without lowering
IDDQ quality.
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Session 13 - DSPs for Wired and Wireless Communications
Chairman: Elliot Gould
Co-Chairman: Dawn Fitzgerald
Targeting the need to push higher data rates through
bandwidth-limited channels, this session covers DSPs,
which describe new techniques in error correction,
modulation, and low-power filtering.
8:30am - Introduction
13.1 - 8:35am
DSP Techniques for Optical Transceivers (Invited)
K. Azadet, E. Haratsch, H. Kim, F. Saibi, J. Saunders*,
M. Shaffer*, L. Song and M-L. Yu, Agere Systems,
Holmdel, NJ and *Andover, MA
Abstract :
This tutorial paper presents the application of
well-known DSP techniques used in lower speed wireline
and wireless applications, to high-speed optical
communications. After an introduction on today's optical
network architecture and optical channel impairments, we
review fiber equalization, Maximum likelihood detection
and forward error correction, with emphasis on VLSI
implementation.
13.2 - 9:00am
Single-Chip 10.7 Gb/s FEC CODEC LSI Using Time-Multiplexed
RS Decoder
K. Seki, K. Mikami, M. Baba, N. Shinohara, S. Suzuki, H.
Tezuka, S. Uchino, N. Okada, Y. Kakinuma and A. Katayama, NEC
Corporation, Kanagawa, Japan
Abstract :
This paper describes a 10.7 Gb/s throughput FEC (Forward
Error Correction) codec LSI for optical transmission
systems. In order to reduce the power consumption and
logic size, the FEC codec uses a time-multiplexed
Reed-Solomon (RS) decoder, which is shared among 4 RS
codewords and processes 5 parallel digits. The
time-multiplexed RS decoder requires only 58% of the
gates and 75% of the power consumption of the
conventional decoder. As a result, the codec achieves a
low power consumption of only 3.31 W and a low gate
count of only 1.1 Mgates using 0.18um CMOS technology.
13.3 - 9:25am
A 220m W 1Gb/s 1024-Bit Rate-1/2 Low Density Parity Check
Code Decoder
C. Howland and A. Blanksby, Agere Systems, Holmdel, NJ
Abstract :
A 1024 bit rate-1/2 Low Density Parity Check (LDPC) code
decoder has been implemented that matches the coding
gain of equivalent turbo codes. The parallel decoder
architecture supports throughputs up to 1 Gb/s and
convergence in the decoding algorithm translates into
extremely low switching activity with power dissipation
under 220 mW.
13.4 - 10:05am
Implementation of a Hermitian Decoder IC in 0.35um CMOS
J.B. Ashbrook, N.R. Shanbhag*, R. Koetter* and R.E. Blahut*, IBM
Microelectronics, Essex Junction, VT and *University of Illinois at
Urbana-Champaign, Urbana, IL
Abstract :
This paper presents the first integrated circuit
implementation of a Hermitian decoder thereby proving
its practical viability. Hermitian codes provide much
larger block lengths (n=4080) compared to that of the
popular Reed-Solomon (RS) codes (n=256) over the same
field (GF(256)). This translates to a coding gain of
0.6dB for the same rate. However, Hermitian codes were
deemed to be too complex to implement until the
emergence of a recent algorithmic breakthrough with made
the complexity of Hermitian decoders comparable to that
of RS codes. Based on Koetter's decoding algorithm, the
chip architecture consists of an array of sixteen
interdependent Berlekamp-Massey algorithm (BMA) blocks.
Thus, the same IC can be used for decoding RS codes as
well. The decoder IC is designed in a 3.3V, 0.35um,
four-metal CMOS process and can correct up to t=60
errors per block of n=4080 words at a rate of 400Mb/s.
The IC prototype consumes 3.0W with a 50MHz clock.
13.5 - 10:30am
A Multicarrier QAM-Modulator for WCDMA Basestation with
On-Chip D/A Converter
M. Kosunen, J. Vankka, M. Waltari and K. Halonen,
Helsinky University of Technology, Espoo, Finland
Abstract :
A multicarrier QAM modulator for a wideband code
division multiple access (WCDMA) basestation has been
designed. The multicarrier modulator performs pulse
shaping filtering for four baseband I and Q data
streams. Input data is interpolated in four stages each
interpolating by a factor two. Four independent carriers
aregenerated and modulated with the CORDIC based
numerically controlled oscillators (NCOs) and summed up
to form a multicarrier WCDMA signal. SINC-attenuation
effect of a D/A converter is canceled by an inverse-SINC
predistortion filter. The multicarrier signal is
converted to the analog domain with a 14-bit current
steering D/A converter which is integrated on the same
silicon chip. Process used in realization of the chip is
a 0.35 um BiCMOS process. However, only CMOS transistors
are used.
13.6 - 10:55am
A Platform-Based Highly Parallel Digital Signal
Processor
T. Richter, W. Drescher*, F. Engel, S. Kobayashi**, V. Nikolajevic, M.
Weiss*, G. Fettweis, TU Dresden, Dresden, Germany and *Systemonic AG,
Dresden, Germany and **Asahi Chemical, Kanagawa, Japan
Abstract :
Realizations of demanding applications particularly in
the field of mobile communications often require
processing performance which is far beyond what is
delivered by DSPs today. To avoid designing inflexible
ASIC solutions a powerful, highly parallel DSP core for
System-on-Chip domains is presented in this paper.
Targeted for a wireless OFDM based modem application the
fixed-point DSP core consists of 16 x 16-bit datapath
units in parallel providing 640 M MAC operations per
second. In a Galois field split mode 32 8-bit datapaths
deliver 1.28 G MAC/s. The DSP is based on a scalable
architecture which supports customization depending on
the application needs. The 289mm2 chip was manufactured
in a 0.35um CMOS technology, operates at 40MHz and
dissipates <1W from a 3.3V supply. This low power
approach outperforms commercial DSPs running at 200MHz.
13.7 - 11:20am
A Low-Power Digital Filter IC via Soft DSP
R. Hegde and
N.R. Shanbhag, University of Illinois, Urbana, IL
Abstract :
In this paper we present an integrated circuit
implementation of a soft DSP based low-power digital
filter in 0.35um, 3.3V CMOS process. Soft DSP is a
low-power technique that employs voltage overscaling
(VOS) and algorithmic noise-tolerance (ANT) to push the
limits of energy-efficiency beyond that achievable by
voltage scaling alone. VOS refers to scaling the supply
voltage beyond the limit imposed by the throughput
constraints. ANT is an algorithmic level error-control
technique that is employed to restore thealgorithmic
performance degradation in terms of output
signal-to-noise ratio (SNR) caused by VOS. Measured
results indicate 40%-67% reduction in energy dissipation
over optimally voltage-scaled systems with less than 1db
loss in SNR for a wide range of filter bandwidths
(0.05fs - 0.25fs, where fs is the sampling frequency).
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