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Session 6 - Sensor Applications and Low Power Techniques
Chairman: Kenneth Szajda
Co-Chairman: John Wright
Following papers on new methods for power conservation
and reduction are circuit applications for sensors and
sensor interfaces.
2:00pm - Introduction
6.1 - 2:05pm
Mixed-Swing Methodology for Domino Logic Circuits
A. Rave and L.R. Carley, Carnegie Mellon University,
Pittsburgh, PA
Abstract :
In this paper we present a multiplier-accumulator (MAC)
implemented in mixed-swing dual rail domino logic. The
performance in the presence of noise and on-chip
coupling is studied. A completely on-chip voltage
regulation technique which adjusts the degree of voltage
regulation in the MAC in the face of process induced
delay variations so as to minimize energy dissipation
while always guaranteeing the target operating frequency
is described. Measurements for a commercial 0.5u CMOS
process demonstrate that the mixed-swing methodology
with series regulation is a viable low power high speed
solution for multiplier circuits.
6.2 - 2:30pm
Utilizing Surplus Timing for Power Reduction
M. Hamada, Y. Ootaguro and T. Kuroda*, Toshiba Corp.,
Japan and *Keio University, Japan
Abstract :
Multiple Vdd's, multiple Vth's, and multiple transistor
width for utilizing surplus timing in non-critical paths
for power reduction is investigated. Theoretical models
are developed from which rules of thumb for optimum
Vdd's, Vth's, and W's are derived, as well as knowledge
for future design.
6.3 - 2:55pm
VTH-Hopping Scheme for 82% Power Saving in Low-Voltage
Processors
K. Nose, M. Hirabayashi, H. Kawaguchi, S. Lee* and T.
Sakurai, University of Tokyo, Tokyo, Japan and *Ewha
University, Seoul, Korea
Abstract :
A threshold voltage hopping (VTH-hopping) scheme is
proposed where VTH is dynamically controlled through
software depending on a workload. VTH-hopping is shown
to reduce the power to 18% of the fixed low-VTH circuits
in 0.5V supply voltage regime for multimedia
applications. A positive back-gate bias scheme within
VTH-hopping is presented for the high-performance and
low-voltage processors. The measurement result shows
about 90% leakage power reduction is possible by using
VTH-hopping.
6.4 - 3:35pm
Design of an Analogue ASIC Using Subthreshold CMOS
Transistors to Model Biological Neurons
L. Alvado, J. Tomas, S. Renaud-Le Masson and V.
Douence, ENSERB-Université Bordeaux, Talence Cédex,
France
Abstract :
We have designed an analogue IC using CMOS transistors
in weak inversion region. This IC emulates the
electrical activity of biological neurons according to
the Hodgkin-Huxley modeling formalism. Measurements
demonstrate the capabilities of the circuit for its use
as an artificial neuron.
6.5 - 4:00pm
A 40 uA/Channel Compensated 18-Channel Strain Gauge
Measurement System for Stress Monitoring in Dental
Implants
W. Claes, W. Sansen and R. Puers, Katholieke
Universiteit Leuven, Heverlee, Belgium
Abstract :
This paper presents an ASIC of an autonomous monitoring
system that is capable of measuring 18 strain gauges
simultaneously. The sensor interface chip is implemented
in a 0.7 um CMOS technology and includes a PTAT-current
reference, an 8-bit DAC, together with a digital
interface for multi-gauge nulling, a SC instrumentation
amplifier, a SC S/H and a 9-bit successive approximation
ADC. The accuracy is better than 20 (strain, while
consuming only 40 uA/channel.
6.6 - 4:25pm
High Sensitivity Silicon Magnetic Field Detector
J. Doyle, University College, Cork, Ireland
Abstract :
A CMOS Magnetic Field Sensitive Oscillator (MAGOSC) is
presented. This device, in response to a 2.1 Gauss
magnetic field, registered a 16.6Hz change in frequency
while running on 27uA supply. An improved noise
reduction technique ensured this was over three sigma
above the noise floor, yielding a high sensitivity
device for this power level. Thus demonstrating the
potential for very high sensitivity silicon magnetic
field detectors.
6.7 - 4:50pm
Interface Circuit for Metal-Oxide Gas Sensor
P.-F. Rüedi, P. Heim, A. Mortara, E. Franzi, H. Oguey
and X. Arreguit, Centre Suisse d'Elecronique et de
Microtechnique S.A., Neuchatel, Switzerland
Abstract :
This paper describes a sensor interface for metal-oxide
chemical gas sensor for pollution detection. The
function of the ASIC is to control the sensor working
temperature by applying a programmable voltage with 10
bits resolution, to measure the resistance of the
sensitive elements ranging from 5kilohm to 100megohm,
measure the ambient temperature with an external NTC
thermistor and offer a fully digital user interface. It
gives the possibility to make low power and low cost
high performance gas sensing micrsosystems for consumer
application.
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Session 7 - Broadband Wireline Transceivers
Chairman: Vincent von Kaenel
Co-Chairman: Sang-Soo Lee
Focusing on wireline transceiver ICs, included papers
describe low-power chips for ADSL, VDSL, and SONET/SDH,
along with Gigabit Ethernet standards.
2:00pm - Introduction
7.1 - 2:05pm
A 800mW, Full-Rate ADSL-RT Analog Frontend IC with
Integrated Line Driver
H. Weinberger, A. Wiesbauer, C. Fleischhacker and J.
Hauptmann, Infineon Technologies, Villach, Austria
Abstract :
An analog front-end IC with integrated line driver for
an ADSL system is presented. The IC contains all analog
functions including gain-controlled transmit- and
receive-amplifiers, highly linear continuous-time low
pass filters including on-chip automatic tuning, 14 bit
ADC and DAC as well as a digitally controlled crystal
oscillator. The IC has been fabricated in a
mixed-signal 0.6um DPTM BiCMOS technology with a chip
area of 29mm2 and a power consumption of only 800mW,
using 3.3V supply for all blocks except 12V supply for
the line driver.
7.2 - 2:30pm
A 12-bit Integrated Analog Front-End for Broadband
Wireline Networks
I. Mehr, P. Maulik and D. Paterson, Analog Devices,
Inc., Wilmington, MA
Abstract :
An integrated transceiver for broadband wireline
networks is presented. The transceiver includes a
receive data path, a transmit data path, and auxiliary
functions including serial port interface, clock and
reference generation blocks, and voltage regulator
control circuitry. The receive data path provides
constant input impedance and is composed of two variable
gain amplifier (VGA) blocks, an analog 4-pole filter, a
12-bit analog-to-digital converter (ADC) sampling at
32MHz, and a digital high-pass filter. The transmit data
path contains digital interpolation filters and a 12-bit
digital-to-analog converter (DAC) sampling at 128MHz.
The chip was implemented in double-poly triple-metal
0.35um CMOS technology. Measured performance for both
receive and transmit data paths meets target
specifications with no noticeable crosstalk.
7.3 - 2:55pm
A Low-Power 8-PAM Serial-Transceiver in 0.5um Digital
CMOS
D. J. Foley and M. P. Flynn, Parthus Technologies and
National University of Ireland, Cork, Ireland
Abstract :
A CMOS multi-level (8-PAM) transceiver is described.
Pre-emphasis is implemented without an increase in DAC
resolution or digital computation. The receiver
oversamples with three fully differential 3-bit ADCs.
The device transmits at up to 1.3Gb/s and has a measured
BER of <10-13 for an 810Mb/s PRBS transmission.
7.4 - 3:35pm
A Low-Power CMOS 155Mb/s Transceiver for SONET/SDH Over
Co-ax & Fibre
M. Altmann, J.M Caia, R. Morle, M. Dunsmore, Y. Xie and
N. Kocaman*, Level One Communications, Sacramento, CA
and *NewPort Communications, Irvine, CA
Abstract :
A single-chip 155Mb/s mixed-signal transceiver includes
line driver, analog TX PLL, digitally-adaptive analog
AGC & equalizer with 18dB range, third order
pulse-shaping filter with tracking PLL, timing recovery
PLL & CMI encoder/decoder. Recovered clock jitter is
<20psRMS. It occupies 10mm2 in a 0.35um digital CMOS
process and consumes 150mA at 3.3V.
7.5 - 4:00pm
A 125-MHz CMOS Mixed-Signal Equalizer for Gigabit
Ethernet on Copper Wire
T-C. Lee and B. Razavi, University of California, Los
Angeles, CA
Abstract :
(not available)
7.6 - 4:25pm
A DSP Based 10BaseT/100BaseTX Ethernet Transceiver in a
1.8V, 0.18um CMOS Technology
S. Huss, M. Mullen, C.T. Gray, R. Smith, M. Summers, J.
Shafer, P. Heron, T. Sawinska and J. Medero, Tality
Corp., Cary, NC
Abstract :
This paper describes a DSP based 10BaseT/100BaseTX
ethernet physical layer interface in a 1.8V 0.18um
single-poly 5-level metal CMOS technology. The DSP
architecture allows for robust performance for cable
lengths >150m. The integrated transceiver is IEEE 802.3
compliant and uses existing 1:1 transformers. The active
area is 6.6mm2 and consumes 350 mW of power.
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Session 8 - Nyquist-Rate Data Converters
Chairman: Venu Gopinathan
Co-Chairman: David Allee
Four ADCs that advance the state-of-the-art in sampling
speed and power consumption are described. Two DACs and
a direct digital synthesizer using a non-linear DAC are
also presented.
2:00pm - Introduction
8.1 - 2:05pm
Design Techniques for Very Low Power ADCs
R.C. Taft, M.R. Tursi, A. Glenny*, National
Semiconducter East Coast Labs, Fürstenfeldbruck, Germany
and *National Semiconductor, Santa Clara, CA
Abstract :
The three low-power ADC techniques of interleaving-by-4
with an amplifier reset and master sampling clock, using
self-regulating CMOS push-pull amplifiers, and a hybrid
comparator are described. They are demonstrated in an
8-bit 100 MSPS ADC which achieves +/- 0.25 LSB DNL and
7.5 effective bits with very low power, 54 mW at 2.7 V
supply.
8.2 - 2:30pm
A 'Digital' 6-bit ADC in 0.25um CMOS
C. Donovan and M.P. Flynn, National University of
Ireland and Parthus Technologies, Cork, Ireland
Abstract :
We describe a digital technique, which removes the
accuracy constraints from the comparators in a flash
analog-to-digital converter. With no analog matching
requirement, the comparators can be small, fast and
power efficient. A 6-bit prototype converter built in a
standard 0.25um digital CMOS process occupies 1.2mm2 and
dissipates 110mW from a 2.2V supply at 300Ms/s. The
technique scales readily, and with improving
performance, to finer processes.
8.3 - 2:55pm
A 900MS/s 6b Interleaved CMOS Flash ADC
B. Yu and W.C. Black, Iowa State University, Ames, IA
Abstract :
A 900MS/s, 6 bit, 4-way, time-interleaved flash ADC is
demonstrated. The 4 on-chip ADCs share a common
reference string and preamplifiers to minimize the
mismatch between channels. The measured SNDR is over
31dB at 900MHz with input at 1.1MHz. The chip has been
fabricated in a standard 0.25um CMOS process.
8.4 - 3:35pm
A 165 MS/s 8-bit CMOS A/D Converter with Background
Offset Cancellation
G. Feygin, K. Nagaraj, R. Chattopadhyay, R. Herrera, I.
Papantonopoulos*, D. Martin, P. Wu, S. Pavan, Texas
Instruments, Warren, NJ and *Dallas, TX
Abstract :
A 8-bit A/D converter using an efficient architecture is
described. An important feature of this is a background
offset cancellation scheme. This A/D converter has been
implemented in a 0.18um digital CMOS technology. It
operates at up to 165 MS/s with an SNDR of 43.5 dB, a
DNL of 0.7 LSB and an INL of 1 LSB. It occupies an
active area of 0.9 mm2 and has a power dissipation of
140 mW.
8.5 - 4:00pm
A Low Power, 10-bit CMOS D/A Converter for High Speed
Applications
M. Borremans, A. Van den Bosch. M. Steyaert and W.
Sansen, Katholieke Universiteit Leuven, Haverlee,
Belgium
Abstract :
In this paper, the realization of a fully binary 10-bit
current steering CMOS DAC is presented. Both the
measured INL and DNL are smaller than 0.2LSB. Better
than 60dB SFDR is achieved for all output signals up to
a 30MS/s Nyquist frequency. For a 1MHz signal, the chip
achieves better than 60dB SFDR for all update rates up
to 800MS/s. The presented DAC core occupies 0.23mm2. The
digital power consumption is only 1mW for a 30MS/s
Nyquist operation. Based on a fundamental theoretical
INL- and DNL-yield analysis, the presented design
explores the limits towards the binary and the low-power
edges of the design space.
8.6 - 4:25pm
A Differential Bipolar Quasi-Passive Cyclic
Digital-to-Analog Converter with 4.416 MSps Conversion
Rate and -77 dB THD
M. Moussavi, R. Mason* and C. Plett*, Catena Networks, Kanata,
Ont., Canada and *Carleton University, Ottawa, Ont., Canada
Abstract :
Cyclic DACs can provide low power alternatives to
current steering DACs for medium conversion rates. A
differential bipolar cyclic DAC achieves close to 12
bits of linearity at 4.416 MSps conversion rate. The
cyclic D/A converter, implemented in a 0.35-u
double-poly CMOS technology, dissipates only 10 mW.
8.7 - 4:50pm
A ROM-less Direct Digital Frequency Synthesizer Using
Segmented Nonlinear Digital-to-Analog Converter
J. Jiang and E.K.F.
Lee*, Iowa State University, Ames, IA and *Silicon Laboratories, Inc.,
Austin, TX
Abstract :
A direct digital frequency synthesizer (DDFS) based on
segmented nonlinear digital-to-analog converter is
proposed. The DDFS has 12 bits of phase resolution and
11 bits of magnitude resolution. It was fabricated in a
0.25um CMOS process with an active area of 1.4 mm2. The
SFDR is 57 dB for output frequency equal to 3/8 of the
300 MHz clock frequency.
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Session 9 - Embedded Memory
Chairman: Albert Stritter
Co-Chairman: Kenji Noda
Future trends in SOC design involving non-volatile
memory with simplified technologies, shared
architectures with compressed repair, and CAM-based
BIST/BISR are presented.
2:00pm - Introduction
9.1 - 2:05pm
FeRAM Device and Circuit Technologies Fully Compatible with
Advanced CMOS (Invited)
H. Toyoshima, S. Kobayashi, J. Yamada, T. Miwa,
H. Koike, H. Takeuchi, H. Mori, N. Kasai, Y. Maejima, A. Seike, N.
Tanabe, T. Tatsumi and H. Hada, NEC Corporation, Kanagawa, Japan
Abstract :
A ferroelectric memory cell has been fabricated after
the completion of standard CMOS. A 0.35-um 2T/2C FeRAM
macro features high write/read endurance, low
consumption current, and a flexible size. This cell
technology also enables a 0.25-um ASIC SRAM macro to be
nonvolatile with a Vdd/2 plate line architecture making
read/write fatigue virtually negligible.
9.2 - 2:55pm
CMOS Process Compatible ie-Flash (Inverse Gate Electrode
Flash) Technology for System-on-a-Chip
S. Shukuri, K. Yanagisawa and K.
Ishibashi, Hitachi Ltd., Tokyo, Japan
Abstract :
A single-poly flash technology named ie(inverse gate
electrode)-Flash, which can be embedded in common CMOS
process without any process modifications, was proposed.
A bit consists of two elementary cells for OR-logical
reading, resulting in significant reliability
improvement. 5V-programming with 1ms duration and
1.2V-read operation of 35bit memory modules is
demonstrated.
9.3 - 3:35pm
An ASIC-Embedded Content Addressable Memory with
Power-Saving and Design For Test Features
T. Chadwick, T. Gordon, R.
Nadkarni and J. Rowland, IBM Microelectronics Division, Essex Junction,
VT
Abstract :
(not available)
9.4 - 4:00pm
A Shared Built-In Self-Repair Analysis for Multiple Embedded
Memories
J. Ohtani, T. Ooishi, T. Kawagoe, M. Niiro, M. Maruta and H.
Hidaka, Mitsubishi Electric Corp., Hyogo, Japan
Abstract :
A shared Built-In Self-Repair Analysis scheme
(Shared-BISA) for multiple embedded memory cores in the
SOC is proposed to realize minimum area penalty
independent of the number of embedded memory cores. A
compact re-configurable CAM array in the BISA circuitry
realizes a flexible redundancy analysis structure to
cope with various memory core and redundancy structures,
and a high-speed operation up to 500MHz.
9.5 - 4:25pm
Shared Fuse Macro for Multiple Embedded Memory Devices with
Redundancy
M. R. Ouellette, D.L. Anand and P. Jakobsen, IBM, Essex
Junction, VT
Abstract :
Customers designing increasingly complex integrated
circuits are turning to ASIC vendors to help bring their
products to market faster than their competitors. ASIC
designs with large amounts of embedded memory must use
fuse-enabled redundancy techniques to maintain price
competitive yield. IBM has developed a data compression
and shared fuse technique to accommodate large numbers
of redundant elements in an ASIC. This technique
minimizes or eliminates problems associated with a large
number of fuses distributed within many embedded
memories on an ASIC.
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