(Back to Sessions List)
Session 1 - Plenary Session
1.1 - 8:00am
Welcome/Opening Remarks
Awards Presentations
Keynote Speaker Introduction
Mike Beunder, General Chairman
1.2 - 8:20am
Keynote Address
"Global Wireless Internet Momentum"
Lloyd Carney, President, Wireless Internet Network
Solutions, Nortel Networks, Inc.
Abstract :
Ubiquitous access to the internet anytime, anywhere, from any device,
will bring entirely new forms of communication and commerce. The
emergence of what we call the "Wireless Internet" signals the joining of
two of the fastest-growing technologies in history: wireless
telecommunications and the internet. The pace of change in the wireless
world has been nothing short of amazing over the past 15 years, with no
consistency other than the continual ability of industry analysts to
underestimate the magnitude of the opportunity. Analog networks have
been replaced almost entirely by new digital technologies. Now, these
second-generation (2G) digital technologies are about to be replaced by
higher capacity, higher-speed third-generation (3G) networks. Wireless
subscribers are projected to reach one billion by 2002, approximately 20
years after the first cellular networks were deployed. Untethered
Internet users will become accustomed to receiving e-mail, stock quotes,
driving directions and other timely information from the Web. Business
users will enjoy the ability to access corporate intranets and virtual
private networks (VPNs) from a personal digital assistant (PDA) or
laptop connected to the mobile network.
It is important for operators to provide cost-effective Wireless
Internet services, and carriers will try to keep from becoming a "dumb
pipe" by controlling the look and feel of the wireless access device.
Nortel believes the next Internet wave will be accomplished by combining
industry-leading optical technology with a strong IP core competency and
advanced wireless access technology.
(Back to Sessions List)
Session 2 - Analog Filtering Techniques
Chairman: Rick Carley
Co-Chairman: Tatsuji Matsuura
The session starts with two continuous-time on-chip filters for use in
radio receivers. Following are two papers on switched-capacitor filters
incorporating anti-aliasing and low-voltage operation.
10:00am - Introduction
2.1 - 10:05am
An Anti-Blocker Structure MOSFET-C Filter For a Direct
Conversion Receiver
A. Yoshizawa and Y. Tsividis*, Sony Corporation Tokyo, Japan and
*Columbia University New York, NY
Abstract :
A MOSFET-C channel selection filter for a direct conversion WCDMA
receiver is presented. This 5th-order elliptic filter achieves -1.8 dBV
in-band IIP3, +27.8 dBV out-of-band IIP3, +93.8 dBV out-of-band IIP2,
46.7 uVrms input-referred noise, and dissipates 6.2 mW from a 2.7 V
supply; the on-chip continuous automatic tuning system dissipates 4.1
mW.
2.2 - 10:30am
A 2.7V CMOS GSM/WCDMA Continuous - Time Filter with
Automatic Tuning
S. Lindfors, T. Hollman*, T. Salo* and K. Halonen*, Royal Institute of
Technology, Kista, Sweden and *Helsinki University Technology, Helsinky,
Finland
Abstract :
A 5th-order continuous-time baseband filter with 7-step
gain control for a dual-mode cellular phone was
implemented. A cascade of a real pole and a ladder
filter implementing the complex pole pairs was used for
low noise. The GBW of the opamps was made programmable
to reduce the power consumption in the GSM-mode. The
corner frequency tuning was facilitated by integrating a
1-bit DAC with the filter and a digital tuning circuit
separately with an ADC.
The integrated input referred noise is 6.9uV and 13.6uV
and the circuit consumes 13mW and 21.8mW in the GSM- and
WCDMA-modes, respectively. The IIP3 is +25dBV in the
WCDMA-mode.
2.3 - 10:55am
Embedded Anti-Aliasing in
Switched-Capacitor Ladder Filters
D. Senderowicz, S. Azuma*, S. Kawama*,
K. Iizuka* and M. Miyamoto*,
SynchroDesign Inc., Berkeley, CA and
*Sharp Corporation, Nara, Japan
Abstract :
A combination of continuous-time and switched-capacitor integrators in a
simulated LC loss-less ladder yields a response with suppressed aliasing
without using continuous-time pre-filtering. Fabricated in a 0.35-um
CMOS process, a fifth-order Cauer low-pass filter has a cut-off
frequency of 1.92 MHz and aliasing suppression of better than 40 dB.
Without using any tuning mechanism, +/-10% accuracy of the cut-off
frequency is achieved. It consumes 3.7 mA at 1.8-V power supply.
2.4 - 11:20am
1.5V 5.0MHz Switched Capacitor Circuits in 1.2um CMOS
Without Voltage Bootstrapper
L. Wang, S.H.K. Embabi and E. Sanchez-Sinencio, Texas
A&M University, College Station, TX
Abstract :
A fully differential SC bandpass biquad and a 4th order
bandpass delta-sigma modulator were designed with 1.2um
CMOS process at 1.5V without using voltage
bootstrappers. The clock frequency is 5.0MHz. The biquad
had Q=8.0 and IM3=-52dB. The modulator had SNR=61dB and
IM3<-78dB in its narrowband of 25KHz centered at
1.25MHz.
(Back to Sessions List)
Session 3 - Oversampled Data Converters
Chairman: Tim Rueger
Co-Chairman: Doug Garrity
This session comprises papers describing low-power and
multi-bit techniques for the development of oversampled
analog-to-digital converters for audio and wireless
networks.
10:00am - Introduction
3.1 - 10:05am
A 12 mW ADC Delta-Sigma Modulator with 80dB of Dynamic
Range Integrated in A Single-Chip Bluetooth Transceiver
J. Grilo, I. Galton*, K. Wang and R. Montemayor,
Silicon Wave, San Diego, CA and *University of
California at San Diego, La Jolla, CA
Abstract :
A 12 mW switched-capacitor (SC) multi-bit ADC
delta-sigma modulator for baseband demodulation
integrated in a single-chip Bluetooth radio-modem
transceiver achieves 77 dB of SINAD and 80 dB of dynamic
range over a 500 kHz bandwidth with a 32 MHz
sample-rate. The 1 mm2 circuit is implemented in a
0.35um BiCMOS SOI process and operates from a 2.7 V
supply.
3.2 - 10:30am
A 105dB SNR Multibit Sigma-Delta ADC for Digital Audio
Applications
K. Nguyen, B. Adams and K. Sweetland,
Analog Devices Inc, Wilmington, MA
Abstract :
A four-channel multibit Sigma-Delta analog-to-digital
converter (ADC) for consumer audio applications is
presented. The converter uses a 2nd-order
switched-capacitor modulator with a 4-bit quantizer and
a 1st-order noise-shaped scrambler. The converter
measured an SNR and D- range of 105dB A-weighted, THD+N
of -98dB at 48kHz sample rate. The circuit is
implemented in 0.5um DPTM CMOS, dissipates 90mW and
occupies 1.6mm squared per channel.
3.3 - 10:55am
A 1.8V Delta-Sigma Modulator Interface for Electret Microphone
with On-Chip Reference
O. Bajdechi and J.H. Huijsing, Delft University of
Technology, Delft, The Netherlands
Abstract :
A delta-sigma ADC for voltage readout of an electret
microphone is presented. The circuit works at a supply
voltage of 1.8V and uses an improved-linearity,
single-ended high-impedance input, differential output
integrator to read the 125mVp audio signal. The fourth
order delta-sigma converter attains 80dB dynamic range
over 11kHz.
3.4 - 11:20am
Ultra Low Voltage Switched Opamp Sigma-Delta Modulator
For Portable Applications
J. Sauerbrey and R. Thewes, Infineon Technologies AG,
Munich, Germany
Abstract :
A Sigma-Delta modulator for portable applications is
presented operating within a large window of supply
voltages. The third order modulator is realized in
Switched-Opamp technique with CM-level shift, clock
boosting is avoided. The prototype is realized in a
0.18um n-well CMOS technology. Measured results are
shown for a voltage range from 1.5 V down to 0.61 V. For
VDD = 0.75 V a SNDR of 64dB is achieved at a signal
bandwidth of 16 kHz.
(Back to Sessions List)
Session 4 - Power Amplification and ESD Issues in Wireless Design
Chairman: Edoardo Charbon
Co-Chairman: Ranjit Gharpurey
After discussions on protection structures for ESD and
related modeling techniques are papers covering the
implementation and analysis of high-efficiency and
high-power amplifiers.
10:00am - Introduction
4.1 - 10:05am
ESD Protection Device Issues For IC Designs (Invited)
C. Duvvury, Texas Instruments, Inc., Dallas, TX
Abstract :
(not available)
4.2 - 10:55am
An IF CMOS Signal Component Separator Chip for LINC
Transmitters
B. Shi and L. Sundström*, Lund University, Lund, Sweden
and *Ericsson Mobile Communications AB, Lund, Sweden
Abstract :
The LINC transmitter provides linear amplification using
highly nonlinear but power efficient amplifiers. The
signal component separator (SCS) is a crucial function
of LINC. This paper presents an IF SCS chip implemented
in a 0.35um CMOS process using a design based on
voltage-translinear circuits. The experimental LINC
transmitter, built with the chip and nonlinear
amplifiers, had output spurious levels some -55dBc and
-48dBc for a NADC signal and an IS-95 signal,
respectively. This implies a high degree of linearity.
4.3 - 11:20am
Accurate Prediction of Spectral Regrowth and In-Channel
Distortion Based on CDMA Signal Time-Domain Model
V. Aparin, Qualcomm, Inc., San Diego, CA
Abstract :
Spectral regrowth of a CDMA signal and in-channel
distortion causing the gain compression or expansion are
analyzed using the power series and statistical theory.
The proposed time-domain model of the CDMA signal is
shown to give more accurate distortion estimates than
the widely used narrow-band Gaussian noise assumption.
The model was also used to show the difference between
statistical properties of the CDMA signal and the
Gaussian noise.
4.4 - 11:45am
A 2.4-GHz, 2.2-W, 2-V Fully-Integrated CMOS
Circular-Geometry Active-Transformer Power Amplifier
I. Aoki, S.D. Kee, D. Rutledge and A. Hajimiri,
California Institute of Technology, Pasadena, CA
Abstract :
A 2.4-GHz, 1.5-W, 2-V fully integrated circular geometry
power amplifier with 50ohm input and output matching is
fabricated using 2.5V, 0.35um CMOS transistors. Harmonic
suppression is 64dB or better. An on-chip
circular-geometry active-transformer is used to combine
several push-pull low-voltage amplifiers efficiently to
produce a larger output power while maintaining a 50ohm
match. This new on-chip power combining and impedance
matching method uses virtual ac grounds and magnetic
couplings extensively to eliminate the need for any
off-chip component such as wirebonds.
(Back to Sessions List)
Session 5 - Not Your Father's FPGA: Programmable Systems-on-a-Chip
Chairman: Vaughn Betz
Co-Chairman: Albert Wang
The complexity of SOC design stymies many. Programmable
logic is being integrated with fixed IP to create
complete programmable systems. Is this the answer?
10:00am - Introduction
5.1 - 10:05am
Programmable Logic IP Cores in SoC Design: Opportunities
and Challenges
S.J.E. Wilton and R. Saleh, University of British
Columbia, Vancouver, Canada
Abstract :
(not available)
5.2 - 10:30am
PLC Advanced Technology Demonstrator TestChip
T. Vaida, LSI Logic Corp., Boulder, CO
Abstract :
(not available)
5.3 - 10:55am
A Hardware/Software Solution for Embeddable FPGA
F. Lien, J. Feng, E. Huang, C. Sun, T. Liu, N. Liao and
D. Hightower, Actel Corporation, Sunnyvale, CA
Abstract :
This paper describes a novel FPGA architecture and
related design software for embedding FPGA logic into
ASIC designs. The requirements for embedding FPGAs
include: fixed pinouts, predictable utilization,
predictable and reasonable signal delays, scalability,
die size control, and ease of layout. This paper
describes Actel's embedded FPGA solution.
5.4 - 11:20am
A Novel FPGA Architecture Supporting Wide Shallow
Memories
S.W. Oldridge and S.J.E. Wilton, University of British
Columbia, Vancouver, Canada
Abstract :
A novel architecture for on-chip user storage in an FPGA
is presented. Shallow wide memories are created by
allowing the user to access switch block configuration
memory. A 100x100 logic block FPGA with 128
tracks/channel yields 9.46 Megabits of memory using this
architecture (at an area cost of 3.58 transistors/bit,
and with typical critical path degradation of 5%).
5.5 - 11:45am
Platform Design Approach for Re-Configurable Network
Appliances
R. Cmar, R. Paško, J-Y. Mignolet, G. Vanmeerbeeck, P.
Schaumont and S. Vernalde, IMEC, Leuven, Belgium
Abstract :
The presented platform-based object-oriented modeling
concept for system design allowed us to create a
networked hardware re-configurable camera in a 25
man-month schedule with concurrent development of
application and target FPGA platform. The developed
TCP/IP layer achieves throughput of 2Mb/s/MHz and the
complete application logic consumes 700 mW at 20MHz.
Back to Sessions List