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CICC 2001 Ed Sessions: Session 3 |
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Session 3 |
Circuit Design for Optical Fiber Communications Golden
Moderator: Francesco Svelto, Università di Pavia E3-1 - 8:00-9:50
System Analysis of High Speed Optical Interfaces: A Design Case Study Optical interfaces are the core of both transport and access networks, currently based on SONET digital transmission hierarchy. The ever-growing need of bandwidth is paving the way for the long distance Optical Transport Network (OTN), which will carry multiple lightpaths on a single fiber, giving a further push to optical component technology. After a brief overview on standards and the SONET and OTN network architectures, the lecture will focus on a case study where the design of a bidirectional interface will be presented. The interface maps a SONET 2.5 Gbit/s client stream on a specific optical wavelength to be carried on the OTN. The design process will be discussed, starting from system specifications and showing how they influence the designer choices and component definition (such as laser, pinfet, amplifiers and timing circuits).The evaluation criteria and trade-off for selecting the components and building the whole system are also covered. E3-2 - 10:10-12:00
Receiver and Transmitter IC design We will examine some practical aspects of receiver and transmitter IC design for multi-gigabit-per-second fiber optic systems. In particular we will discuss the design of transimpedance amplifiers, limiting amplifiers, and laser and modulator drivers. Although in most publications the emphasis tends to lie on obtaining record speeds, in reality the needs of systems designers are much more subtle than that. Some performance criteria in addition to bandwidth that are used for the receiver parts are sensitivity, dynamic range, group delay and pulse distortion. We'll also touch on somewhat more subtle topics such as AC vs. DC coupling, linear vs. limiting receivers, and their applications. On the transmit side we distinguish drivers for lasers, both cooled and uncooled, electro-absorption as well as Mach-Zehnder modulators drivers. Here the main criteria are output current or voltage capability, power dissipation and jitter, overshoot, undershoot, and pulse shape. We'll look at packaged vs. co-packaged drivers; impedance matched vs. open drain/collector output stages; clocked vs. unclocked designs; and RZ (return-to-zero) vs. NRZ (non return-to-zero) coding. E3-3 - 1:00-2:50
Practical CMOS Circuits for Clock and Data Recovery Intuitive explanation of CDR functions. Survey of commonly used clock recovery circuits. Properties of random NRZ data in the frequency domain and analytical methods for CDR design. Discussion of jitter in oscillators. Impact of SONET jitter transfer and jitter generation specs on the system design and loop parameters. Tradeoff between jitter tolerance and maximum run-length without transitions. Session includes a practical design example using a Ring VCO and an LC VCO and concludes with measurement techniques and examples. E3-4 - 3:10-5:00
Basic SiGe Bipolar ICs for 40 Gb/s Optical-Fiber Links - Design and
Realization Optical fiber links based on 40 Gb/s electrical time-divison multiplexing are just under development. It has been shown that the electronic circuits required can be fabricated in available SiGe bipolar technologies, provided they are designed very carefully. Therefore, design considerations are the first topic of this lecture. The lecture covers adequate analog and digital circuit concepts, demands on transistor modeling, optimization of transistor geometry, and layout aspects with special regard to on-chip interconnections. Then it is shown how the chips can simply be mounted and how they were measured up to 60 Gb/s. Finally, the circuits developed for a 40 Gb/s link are described and their measuring results are presented. Examples are a 60 Gb/s 2:1 MUX, a 40 Gb/s EAM driver circuit, and a 40 Gb/s high-gain transimpedance amplifier.
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