CICC 2001 Ed Sessions: Session 1

Advanced Data Converter Design and Test Techniques

Moderator: Douglas Garrity, Motorola

Assistant: David Allee, Arizona State University

E1-1 - 8:00-9:50

Multi-bit Mismatch-Shaping DACs for High-Performance Delta-Sigma Data Conversion
Ian Galton, University of California

Mismatch-shaping DACs have become widely used in high-performance delta-sigma data converters. By suppressing the signal-band portion of the error introduced by inevitable component mismatches, mismatch-shaping DACs have made the use of multibit quantization in delta-sigma modulators practical. Relative to single-bit quantization, which was the norm prior to the availability of mismatch-shaping DACs, multi-bit quantization significantly relaxes the performance required of the analog circuitry, thereby increasing the data conversion performance that can be achieved for a given power consumption and circuit area. This tutorial will present a detailed explanation of mismatch-shaping DACs and their application to high-performance delta-sigma data converters at both the signal-processing and circuit levels. After a brief review of delta-sigma modulation, the tutorial will provide a practical explanation of the signal processing principle underlying the ability of mismatch-shaping DACs to shape mismatch error without knowledge of the mismatches, a survey of alternative mismatch-shaping DAC topologies, a detailed circuit-level description of highly efficient first-order and second-order mismatch-shaping DACs, and the system and analog circuit level delta-sigma modulator design implications of mismatch-shaping DACs. Examples of state-of-the-art delta-sigma data converters will be presented as case studies.

Post-Conference Update

Due to an unfortunate production error, certain pages were omitted from the printed course materials for this talk. You can find them here (45k pdf).

E1-2 - 10:10-12:00

Design of Pipelined Analog-to-Digital Converter
Pat Rakers, Motorola

This tutorial presents the design of pipelined ADCs. The tutorial will start with a basic review of ADC specifications. Then the basics of pipeline ADC system design, including performance requirements of system blocks and residue plots, will be presented. Further detail will be given for a fully pipelined 1.5 bit/stage design. A design example for a CMOS pipelined ADC will be given and this will be followed up with case studies that highlight some important design considerations.

E1-3 - 1:00-2:50

Background Calibration of Analog-to-Digital Converters
Steve Lewis, UC Davis

This session will review recently published articles from UC Davis on the background calibration of analog-to-digital (A/D) Converters. Background calibration will be defined as calibration that is transparent to A/D converter users.

Until recently, background calibration has mostly been used to achieve very high levels of A/D converter performance. However, its importance is increasing because it may be useful in even low-performance converters as a result of process-technology scaling. This scaling has two main effects. First, it increases the difficulty of the design of analog circuits because reduced channel lengths require reduced power-supply voltages. As a result, the maximum gain of single-stage operational amplifiers (op amps) is decreasing, which increases the corresponding closed-loop errors. Second, scaling reduces the cost of digital circuits.

Although the gain problem can be overcome by increasing the number of op-amp stages and using nested Miller-effect compensation for stability, multistage op amps are not as fast as single-stage op amps. Therefore, this session will assume the continued use of single-stage op amps to maximize speed. To compensate for the effects of reduced finite op-amp gain, digital background-calibration techniques will be described. This is a competitive solution because scaled technologies offer large numbers of inexpensive digital transistors that can be used for calibration.

E1-4 - 3:10-5:00

State of the Art Lab Characterization Methods for High Speed ADCs and DACs
Steve Reine, Analog Devices

High Speed ADCs and DACs are making the distance, often spoken of as bits to the antenna, shorter in each new generation of converters. Cutting-edge digital communications systems require novel and unique characterization methods for ADCs and DACs. Converter characteristics are now defined in terms of radio and broadband communications technology. Spectral characteristics become key, while time domain effects take on new meaning. Generation of high-speed analog and digital test signals requires that generators be capable of synthesizing high dynamic range multi-carrier and wideband signals.