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Session 22 - CAD Methods for Deep Sub-Micron Designs
Chairman: N.S. Nagaraj
Co-Chairman Peter Feldmann
This session discusses parasitic extraction, model reduction, crosstalk
analysis and avoidance methods for deep sub-micron designs. Included
are coupling-aware bus coding for low-power design and mismatch-aware
analog synthesis techniques.
1:30pm - Introduction
22.1 - 1:35pm
On-Chip Inductance Modeling and RLC Extraction of VLSI Interconnects for
Circuit
X. Qi, G. Wang, Z. Yu, R. Dutton, T. Young* and N. Chang**,
Stanford University, Stanford, CA, *Synopsys Inc., Mountain View, CA and
**Hewlett-Packard Laboratories, Palo Alto, CA
Abstract :
On-Chip inductance modeling of VLSI interconnects is presented which
captures 3D geometry from layout design and process technology
information. Analytical formulae are derived for quick and accurate
inductance estimation which can be used in circuit simulations and whole
chip extraction screening process. Circuit simulations show critical
global wire inductive effects as well as power and ground inductive
noise.
22.2 - 2:00pm
Parasitic Extraction for Multimillion-Transistor Intregrated Circuits:
Methodology and Design Experiences
E. You, S. Choe, C. Kim, L.
Varadadesikan, K. Aingaran and J. MacDonald*, Sun Microsystems Inc.,
Palo Alto, CA and *Mentor Graphics Corp., Wilsonville, OR
Abstract :
This paper discusses accuracy issues in parasitic extraction for
multimillion-transistor integrated circuits. The methodology reported
aims at reducing the gap between early parasitic estimation and
post-layout extraction. The objective is to obtain consistent
interconnect models in hierarchical design flows. Experimental results
on the 800 MHz UltraSPARC-III microprocessor demonstrate the profound
impact of extraction methodology on interconnect modeling as well as
subsequent timing and noise analyses.
22.3 - 2:25pm
Multi-Aggressor Relative Window Method for Timing Analysis Including
Crosstalk Delay Degradation
Y. Sasaki and K. Yano, Hitachi Ltd., Tokyo,
Japan
Abstract :
We have developed a method to deal with the crosstalk effects in timing
analysis. The method calculates quantitative delay degradation caused
by crosstalk even when there are multiple aggressors for one victim and
the signal arrival times dynamically change depending on the input
patterns. The method can decrease design delay margins and is especially
useful for designing high-performance LSIs.
22.4 - 2:50pm
Multi-Dimensional Model Reduction of VLSI Interconnects
P. Gunupudi
and M. Nakhla, Carleton University, Ottawa, Canada
Abstract :
Recently there have been numerous publications for developing
reduced-order macromodels for linear circuits. However, all these
techniques perform model reduction with respect to a single parameter
such as frequency. This paper presents a new technique to reduce the
order of the linear system simultaneously with respect to multiple
parameters. The reduction is based on multi-dimensional congruence
transformation. The proposed algorithm provides efficient means to
estimate the response of large circuits simultaneously as a function of
frequency and other design parameters.
22.5 - 3:15pm
A Novel High-Performance Predictable Circuit Architecture for the Deep
Sub-micron Era
Y. Im and K. Roy, Purdue University, West Lafayette, IN
Abstract :
We suggest a novel predictable circuit architecture, named optimized
overlaying array based architecture (O2ABA), especially suited for the
deep sub-micron regime. O2ABA achieves reduction of cross talk by
considering the current directions and by reducing the size of interwire
capacitance. The introduction of unit cell leads to ultimate regularity,
making performance predictable even before layout.
22.6 - 3:40pm
Low Power Bus Coding Techniques Considering Inter-wire Capacitances
P.
Sotiriadis and A. Chandrakasan, Massachusetts Institute of Technology,
Cambridge, MA
Abstract :
In this paper we analyze the energy consumption on data busses
considering wire to substrate and wire to wire parasitic capacitances.
It is shown that transition reduction is not necessarily the best
approach for reducing power consumption. A family of coding techniques
that can reduce the average power of the bus by 40% according to the
derived energy estimation model is presented.
22.7 - 4:05pm
WiCkeD: Analog Circuit Synthesis Incorporating Mismatch
K. Antreich,
J. Eckmueller*, H. Graeb, M. Pronath, F. Schenkel, R. Schwencker* and
S. Zizala*, Technical University of Munich, Munich, Germany and
*Infineon Technologies, Munich, Germany
Abstract :
This paper presents a method to consider local process variations, which
crucially influence the mismatch-sensitive analog components, within a
new simulation-based analog synthesis tool called WiCkeD. WiCkeD
includes tolerance analysis, performance optimization and design
centering and is a university tool used in industry for the design of
analog CMOS circuits.
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Session 23 - IP Development and Protection
Chairman: Alex Kurosawa
Co-Chairman Terry Sideris
This session begins with an extensive overview of IP protection,
implementation styles, and conversion techniques. It concludes with
examples of IP development for network applications.
1:30pm - Introduction
23.1 - 1:35pm
On Intellectual Property Protection (Invited)
E. Charbon and I.
Torunoglu, Cadence Design Systems, San Jose, CA
Abstract :
New design paradigms based on the concept of system-on-chip are
gradually replacing printed circuit board centric approaches. This trend
is mainly due to two factors: far higher running speeds and greater
miniaturization. The new paradigms will accelerate design cycles, which
in turn will force designers to reuse existing and acquire new circuits
ready to be integrated. Such acceleration will be possible only if
highly specialized core authors, integrators, and foundries will be able
to efficiently and safely exchange and handle their intellectual
property.The field known as intellectual property protection is aimed at limiting
all violations to intellectual property rights through appropriate
design methodologies, tools, and infringement detection techniques. The
paper surveys all published aspects of the intellectual property
protection problem, in the context of concerted VSIA efforts to define
new standards and protocols.
23.2 - 2:25pm
An Analysis of the Design Processes Required for the Technology
Conversion of SoC Intellectual Property
J. Nash and P. Smith, Motorola,
Inc., Austin, TX
Abstract :
The conversion of existing embedded intellectual property (IP) from one
automotive, mix mode technology to another is analyzed with respect to
the methods and resources required. Conclusions are drawn about advances
required in tools and design processes to better aid this task.
23.3 - 2:50pm
Firm IP Development: Methodology and Deliverables
A. Ranjit, P.
Ramkumar and V. Noel, Cadence Design Systems Inc., San Jose, CA
Abstract :
This paper addresses the need to develop firm intellectual properties
(IP's), with a standard set of deliverables, so they can be integrated
with very little effort. We have presented the design flow used for
developing a firm IP. A DMA controller is used as an example. The paper
also highlights the deliverables from a IP vendor/user perspective to
proliferate the acceptance and usage of the IP.
23.4 - 3:15pm
A New Paradigm for Very Flexible SONET/SDH IP- Modules
T. Rower, M. Stadler, M. Thalmann*, H. Kaeslin, N. Felber and W.
Fichtner, Swiss Federal Institute of Technology, Zurich, Switzerland and
*Siemens Switzerland AG, Zurich, Switzerland
Abstract :
We have implemented a SONET/SDH compatible 155Mbit/s input block using a
new paradigm called programmable intellectual property. The module can
be reconfigured by downloading new software versions into the IP
embedded processor. This concept offers maximum flexibility for both
hard- and soft-IP modules.
23.5 - 3:40pm
Merging Hardware and Software: Intellectual Property Cores for Internet
Applications
G. Bollano, S. Claretto, E. Filippi, A. Torielli and M.
Turolla, CSELT, Torino, Italy
Abstract :
The paper presents soft and hard IP cores for design reuse purposes that
can be efficiently used to solve both exact and longest match operations
in forwarding Internet packets.The soft macro is an innovative IP implementing a ternary CAM, it merges
an HW module for fast search and a SW module for search table
configuration. The hard macro is a configurable and physical Ternary
CAM.
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Session 24 - Audio and Visual Signal Processing
Chairman: Dawn Fitzgerald
Co-Chairman Alan Willson
This session presents techniques for implementing audio and video signal
processing algorithms for such applications as HDTV, set-top boxes and
video telephony. Such computationally intensive applications demand the
highest performance possible from the current technology.
1:30pm - Introduction
24.1 - 1:35pm
VLSI Implementatation of a Realtime Wavelet Video Coder
R. Omaki, Y.
Dong, M. Miki, M. Furuie, S. Yamada, D. Taki, M. Tarui, G. Fujita, T.
Onoye* and I. Shirakawa, Osaka University, Osaka, Japan and *Kyoto
University, Kyoto, Japan
Abstract :
The architecture of a realtime wavelet video coder is described, with
main emphasis put on memory bandwidth reduction and efficient VLSI
implementation. The video encoder is integrated in a 0.35 um 3 layer
metal chip by using 341 K transistors on a 4.93x4.93 mm2 die, which can
process 720x480 30fps pictures in realtime.
24.2 - 2:00pm
A Partitioned Wavelet-based Approach for Image Compression using FPGA's
J. Ritter and Paul Molitor, University of Halle-Wittenberg, Halle,
Germany
Abstract :
Discrete wavelet transformations (DWT) followed by embedded zerotree
encoding is a very efficient technique (EZT) for image compression.
However, the algorithms proposed in literature assume random access to
the whole image. This makes the algorithms unsuitable for hardware
solutions because of extensive access to external memory. Here, we
introduce efficient FPGA hardware approaches for DWT for lossless and
lossy image compression targeting the minimization of external memory
accesses. In particular, the approaches allow both parallel wavelet
transformation and parallel embedded zero tree encoding.
24.3 - 2:25pm
FLOVA: A Four-issue VLIW Geometry Processor with SIMD Instructions and
Lighting Acceleration Unit
S.-J. Nam, B.-W. Kim, Y.-H. Im, Y.-S. Kwon,
J.-H. Lee, Y.-W. Cheon, S.-J. Byun, D.-H. Lee and C.-M. Kyung, Korea
Advanced Institute of Science and Technology, Taejon, Korea
Abstract :
This paper describes a VLIW (Very Long Instruction Word) geometry
processor called FLOVA (FLOating-Point VLIW Architecture) which was
developed to accelerate the geometry stage of 3D graphics. FLOVA
executes four instructions in one cycle and supports 136 instructions
including 35 SIMD (Single Instruction Multiple Data) instructions to
accelerate the geometry stage. Special features to accelerate
transformation and lighting operations in 3D graphics geometry stage are
described. FLOVA can calculate the power value of two floating-point
numbers in only four clock cycles with a negligible loss of accuracy,
compared to over 150 clock cycles in other processors.
24.4 - 2:50pm
Novel VLIW Code Compaction Method for a 3D Geometry Processor
H.
Suzuki, H. Makino and Y. Matsuda, Mitsubishi Electric Corporation,
Hyogo, Japan
Abstract :
A novel code-compaction method has been proposed to solve the code bloat
problem of VLIW architectures. An instruction swap circuit controlled
by the decompaction rules expands the compacted VLIW code. The 2-issue
VLIW and the proposed method enable a 3D geometry processor to achieve
the 1.3x speed and the 94% code density.
24.5 - 3:15pm
Multi-Thread VLIW Processor Architecture For HDTV Decoding
H. Kim,
W.-S. Yang, M.-C. Shin, S.-J. Min*, S.-O. Bae* and I.-C. Park, Korea
Advanced Institute of Science and Technology, Taejon, Korea and *LG
Corporate Institute of Technology, Taejon, Korea
Abstract :
This paper describes a single-chip high definition television (HDTV)
decoder which performs system parsing, video decoding, audio decoding
and resolution conversion. To process a huge amount of data and deal
with various standards in the decoder, a multi-thread processor
architecture is proposed to minimize the overhead cycles of
task-switching. The features of parallelism and conditional branches in
MPEG2 video decoding algorithm are considered to enhance the performance
of the embedded processor and to reduce the size of code memory.
Experimental results show that the proposed processor architecture is
5.3 times faster than a scalar processor at the cost of negligible
increase of code memory.
24.6 - 3:40pm
A Full Accuracy MPEG1 Audio Layer 3 (MP3) Decoder with Internal Data
Converters
S. Hong, B. Park, Y. Song, H. Seo, J. Kim, H. Lee, D. Kim
and M. Sing*, TLI Inc., Kyunggi-do, Korea and *Dongguk University,
Seoul, Korea
Abstract :
A full accuracy MPEG1 Audio Layer 3(MP3) decoder with internal A/D
Converter and D/A Converter is proposed. The chip is composed of a
digital block to implement MP3 decoding and voice
compression/decompression algorithm, a 12-bit recycling type A/D
Converter, and an oversampling delta-sigma 1-bit D/A Converter. In order
to satisfy the full accuracy specification of MP3 decoder, a novel
32-bit floating DSP core is proposed. Further, an efficient power
management technique is implemented to reduce power consumption for
portable applications. The proposed decoder has been fabricated with a 4
metal 0.35um CMOS technology and the chip area is about 6.4x6.7 mm2 with
165mW power dissipation at 2.7V power supply.
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Session 25 - Oscillators, PLLs and Applications
Chairman: Peter Kinget
Co-Chairman Vincent VonKaenel
This session reports insights in phase-noise mechanisms and describes
novel topologies in oscillator design. State-of-the-art performance for
integrated oscillators and phase locked loops is presented.
1:30pm - Introduction
25.1 - 1:35pm
Physical Processes of Phase Noise in Diffrential LC Oscillators
J. Rael
and A. Abidi, University of California, Los Angeles, CA
Abstract :
Using a simple nonlinear model, the mechanisms which convert voltage and
current noise into phase noise are explored. An exact expression is
derived for all the sources of thermally induced phase noise, and
Leeson's noise factor obtained. Flicker noise upconversion is found to
be the result of fundamental FM processes. The analysis is validated
against measured phase noise.
25.2 - 2:00pm
A New Approach to Fully Intregrated CMOS LC-Oscillators with a Very
Large Tuning Range
F. Herzel, H. Erzgraber and N. Ilkow, Institute of Semiconductor
Physics, Frankfurt, Germany
Abstract :
We describe a new approach to fully integrated CMOS LC-oscillators with
very large tuning range. An experimental oscillator is tunable from 1.34
GHz to 2.14 GHz. The standard deviation of the oscillation period due to
thermal device noise is below 250 ppm.
25.3 - 2:25pm
A 1 mA, -120.5 dbc/Hz at 600 kHz from 1.9 GHz fully tuneable LC CMOS
VCO
F. Svelto, S. Deantoni* and R. Castello**, University di
Bergamo-Via Marconi, Dalmine, Italy, *ST Microelectronics-Via Ferrata,
Pavia, Italy and **University di Pavia-Via Ferrata, Pavia, Italy
Abstract :
A 2V, 1 mA, 1.8 GHz to 2.45 GHz tuneable LC-tank CMOS VCO is presented.
The tank is made of a Metal-Oxide-Silicon varactor and a bondwire
inductor, realized connecting two pads to a package frame lead, to be
compatible with the production environment. This solution enables to
tune all components variations, while achieving the lowest phase noise
times current consumption product, reported to date.
25.4 - 2:50pm
A 10 GHz Distributed Voltage Controlled Oscillator
H. Wu and A.
Hajimiri, California Institute of Technology, Pasadena, CA
Abstract :
A 10 GHz CMOS distributed voltage controlled oscillator (DVCO) is
designed in a 0.35um BiCMOS process technology using only CMOS
transistors. The oscillator achieves a tuning range of 12% (9.3 GHz to
10.5 GHz) and a phase noise of -114 dBc/Hz at 1 MHz offset from a
carrier frequency of 10.2 GHz. The VCO uses two different simultaneous
tuning techniques, which allow for a coarse and fine tuning of frequency
in a frequency synthesizer. The oscillator provides an output power of
-7 dBm without any buffering, drawing 14mA of dc current from a 2.5V
power supply.
25.5 - 3:15pm
A 1.8 GHz Highly-Tunable Low-Phase-Noise CMOS VCO
B. De Muer, N. Itoh*,
M. Borremans and M. Steyaert, Katholieke University Leuven, Heverlee,
Belgium and * Toshiba Corporation, Kawasaki, Japan
Abstract :
A 1.8 GHz fully integrated CMOS Voltage Controlled Oscillator is
presented. Through inductor optimization, the phase noise is as low as
-127.5 dBc/Hz at 600 kHz and -142.5 dBc/Hz at 3MHz. A 28 % wide tuning
range is achieved with a 1.8 V power supply. The VCO is implemented in a
2-metal layer, 0.25um standard CMOS technology.
25.6 - 3:40pm
A Fully-Intregrated Low Phase-Noise Nested-Loop PLL for Frequency
Synthesis
A. Hafez and M. Elmasry, University of Waterloo, Waterloo,
Canada
Abstract :
It is greatly beneficial to integrate the VCO. An efficient way to
accomplish that is through the help of wide-bandwidth PLLs. This paper
presents a simple 'nested-loop' PLL architecture that achieves very wide
BW while maintaining the required frequency resolution and spur
rejection. The wide-BW loop, including the loop filter, is integrated
on a single chip in a 25GHz bipolar process. The PLL achieves a
phase-noise of -100dBc/Hz at 10kHz offset from 1GHz and consumes 9.9mA
from a 3.3V supply.
25.7 - 4:05pm
A Low Power High Spectral Purity Frequency Translational Loop for
Wireless Applications
M. Margarit and M. Deen*, Silicon Wave, San
Diego, CA and *McMaster University, Hamilton, Ontario, Canada
Abstract :
PLL's with a mixer in the loop can perform the up-conversion function in
communication systems which use constant envelope modulation techniques.
These loops, usually named Frequency Translational loops (FTL), perform
the up-conversion of the modulated signal from an intermediate frequency
to the transmitter frequency.Frequency Translational Loops used in portable wireless communications
applications, such as cellular telephony, are required to achieve low
phase noise and low spurious levels. This paper presents the design of a
monolithic FTL which operates in the IF frequency range from 100MHz to
450MHz and the RF frequency range from 900MHz to 1.9GHz. The output
phase noise level is -120dBc/Hz at 400kHz offset and -165dBc/Hz at 20MHz
offset from a 900MHz carrier and the spurious levels are lower than 60dB
below the carrier. These characteristics make the FTL suitable for use
in cellular telephony applications such as GSM/DCS.
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