(Back to Sessions List)
Session 18 - Analog Techniques
Chairman: Jose Cruz
Co-Chairman Venugopal Gopinathan
This session presents high-speed synthesizers and clock-recovery
circuits with state-of-the-art performance. Also described are a set of
continuous-time filters and a pico ampere readout circuit for
pyroelectric array detectors.
8:30am - Introduction
18.1 - 8:35am
CMOS DLL Based 2V, 3.2ps Jitter, 1GHz Clock Synthesizer and Temperature
Compensated Tunable Oscillator
D. Foley and M. Flynn*, NMRC, University
College, Cork, Ireland and *Silicon Systems Limited, Cork, Ireland
Abstract :
This paper describes a low voltage, low jitter clock synthesizer and a
temperature compensated tunable oscillator. Both of these circuits
employ a self-correcting Delay Locked Loop (DLL). The DLL provides
multiple clock phases that are combined to produce the desired output
frequency for the synthesizer and provides temperature compensated
biasing for the tunable oscillator. With a 2V supply the measured RMS
jitter for the 1GHz synthesizer output was 3.2ps. With a 3.3V supply RMS
jitter of 3.1ps was measured for a 1.6GHz output. The tunable oscillator
has a 1.8% frequency variation over an ambient temperature range from 0
to 85C. The circuits were fabricated on a generic 0.5um digital CMOS
process.
18.2 - 9:00am
A 900MHz, 2.5mA CMOS Frequency Synthesizer with an Automatic SC Tuning
Loop
T.-H. Lin and W. Kaiser, University of California, Los Angeles, CA
Abstract :
A 900MHz PLL frequency synthesizer implemented in 0.6um CMOS technology
is developed for WINS applications. It incorporates an SC
discrete-tuning loop to extend the frequency tuning range to 20% while
the VCO gain from the CMOS varactor continuous-tuning is kept low at
only 20MHz/V, to minimize the reference spurs. This synthesizer achieves
a phase noise of -102 dBc/Hz at 100kHz offset and reference spurs below
-55 dBc. Including an on-chip VCO, it dissipates only 2.5mA from a 3V
supply.
18.3 - 9:25am
A 2.5-Gb/s Clock Recovery Circuit for NRZ Data in 0.4-um CMOS
Technology
S. Anand and B. Razavi, University of California, Los
Angeles, CA
Abstract :
This paper describes a 2.5-Gb/s phase-locked clock recovery circuit
utilizing a two-stage ring oscillator and a sample-and-hold phase
detector. Fabricated in a 0.4-um digital CMOS technology, the recovered
clock exhibits an rms jitter of 10.8 ps for a PRBS sequence of length
27-1 while dissipating 50 mW of power from a 3.3-V supply.
18.4 - 9:50am
A 65 mW, 0.4-2.3 GHz Bandpass Filter for Satellite Receivers
J. van
der Tang, D. Kasperkovitz and A. Bretveld*, Philips Research
Laboratories, Eindhoven, The Netherlands and *Philips Consumer
Electronics, Eindhoven, The Netherlands
Abstract :
A monolithic tunable bandpass filter for satellite receiver front-ends
is demonstrated for the first time. The center frequency of the filter
can be tuned from 0.4 GHz to 2.3 GHz. The filter is constructed using
four gm-C filter sections and has a 50 dB variable gain range. An
on-chip I/Q oscillator enables automatic tuning. The filter dissipates
65 mW and occupies 0.16 mm2 chip area.
18.5 - 10:15am
A 3V Linear Input Range Tunable CMOS Transconductor and Its Application
to a 3.3V 1.1MHz Chebyshev Low-Pass Gm-C Filter for ADSL
J.-Y. Lee,
C.-C. Tu and W.-H. Chen, Industrial Technology Research Insititute,
Hsinchu, Taiwan, R.O.C.
Abstract :
A fully differential adaptively biased CMOS transconductor with 3V
linear input range is proposed. The Gm value of the transconductor is
tunable through current division scheme. A 0.35um 3.3V 1.1MHz chebyshev
low-pass filter using this highly linear transconductor achieves IM3
distortion @ 300KHz to be -62dBc for 2Vppd input signal.
18.6 - 10:40am
A CMOS gm-C IF Filter for Bluetooth
P. Andreani and S. Mattisson*,
Lund University, Lund, Sweden and *Ericsson Mobile Communications AB,
Lund, Sweden
Abstract :
An 18th (4th + 14th) order gm-C IF filter for the Bluetooth short-range
radio, implemented in a 0.6um CMOS process, is presented. The filter
bandwidth is 1MHz, the center frequency fc is 3MHz, the in-band group
delay variation is 0.75us, and the stop-band attenuation at fc +/- 1MHz
is at least 47dB. The noise floor is 250uVrms and the spurious free
dynamic range is at least 58dB for out-of-band signals, thus exceeding
the Bluetooth requirements. Current consumption is 2.4mA from a 2.5V
power supply.
18.7 - 11:05am
A CMOS Readout Circuit for Pico-Ampere Thin Film Pyroelectric Array
Detectors
T. Reimann, F. Krummenacher, B. Willing, P. Muralt and M.
Declercq, Swiss Federal Institute of Technology, Lausanne, Switzerland
Abstract :
A 16-channel readout circuit able to process low frequency modulated
(1-10 hertz) current signals in the pico-ampere range has been
integrated in a 0.7 um CMOS technology. Each channel consists in a low
input-referred noise (1.5 fA/(Hz @ 10 Hz) high gain (14 Gohm)
transimpedance preamplifier, a multiplier for the signal demodulation
followed by an integrator and a 12-bit A/D converter.
(Back to Sessions List)
Session 19 - Low Power and Dynamic Design Techniques
Chairman: Ken Au
Co-Chairman Michio Yotsuyanagi
Logic-design style, performance, power dissipation, and noise immunity
are all important design parameters. Optimizing these parameters
becomes increasingly difficult as technology continues to scale down.
8:30am - Introduction
19.1 - 8:35am
Effect of Technology Scaling on Digital CMOS Logic Styles (Invited)
M. Allam, M. Anis and M. Elmasry, University of Waterloo, Waterloo,
Canada
Abstract :
In this paper, the main challenges of technology scaling are reviewed in
depth. Five popular logic families, namely, Conventional CMOS, CPL,
Domino, DCVS and MCML are represented highlighting their advantages and
drawbacks. The behavior of each logic style in deep submicron
technologies is analyzed and predicted for future generations.
19.2 - 9:25am
Boosted Gate MOS (BGMOS): Device/Circuit Cooperation Scheme to Achieve
Leakage-Free Giga-Scale Integration
T. Inukai, M. Takamiya, K. Nose,
H. Kawaguchi, T. Hiramoto and T. Sakurai, University of Tokyo, Tokyo,
Japan
Abstract :
This paper proposes a new device and circuit scheme that drastically
suppresses the stand-by leakage current for the deep sub-0.1um era.
Applying boosted gate voltage on the low leakage switches with higher
Vth and thicker Tox, extremely low stand-by power for battery type
application is achieved, while degradation of circuit performance and an
increase of area overhead are sufficiently suppressed.
19.3 - 9:50am
Power Minimization by Simultaneous Dual-Vth Assignment and Gate-sizing
L. Wei, K. Roy and C.-K. Koh, Purdue University, West Lafayette, IN
Abstract :
Gate-sizing is an effective technique to optimize CMOS circuits for
dynamic power dissipation and performance while dual-Vth (threshold
voltage) CMOS is ideal for leakage power reduction in low voltage
circuits. This paper focuses on simultaneous dual-Vth assignment and
gate-sizing to minimize the total power dissipation while maintaining
high performance. An accurate power dissipation model that includes
short-circuit, switching, and leakage power is derived and used in our
optimization. Results show that more than 20% and 40% power reductions
are achievable for circuits at high and low switching activities,
respectively, compared to single low-Vth CMOS circuits while maintaining
performance.
19.4 - 10:15am
5.5V Tolerant I/O in a 2.5V 0.25um CMOS Technology
A.-J. Annema, G.
Geelen* and P. de Jong**, Philips Research Laboratories, Eindhoven, The
Netherlands, *Philips Semiconductors, Eindhoven, The Netherlands and **
Philips Semiconductors, Nijmegen, The Netherlands
Abstract :
Robust high-voltage tolerant I/O that do not need process options is
presented, demonstrated on 5.5V tolerant open-drain I/O in a 2.5V 0.25um
CMOS technology. Circuit techniques limit oxide stress and hot-carrier
degradation, resulting in hundreds of years extrapolated lifetime for
5.5V pad voltage swing, 2.2V supply voltage, 10MHz switching frequency.
The shown concepts are also implemented in other types of I/O and can
easily be scaled towards newer processes.
19.5 - 10:40am
Dynamic Current Mode Logic (DyCML) - A New Low-Power High-Performance
Logic Family
M. Allam and M. Elmasry, University of Waterloo, Waterloo,
Canada
Abstract :
This paper presents a new logic style for low-power high-performance
VLSI applications. The new logic family combines the speed, low supply
voltage and noise immunity of CML circuits with the low standby current
and design simplicity of dynamic circuits. Experimental results shows
that DyCML is superior over other logic styles.
19.6 - 11:05am
A Noise-Tolerant Dynamic Circuit Design Technique
G. Balamurugan and
N. Shanbhag, University of Illinois at Urbana-Champaign, Urbana, IL
Abstract :
A new circuit technique, referred to as the twin-transistor technique,
for increasing the noise immunity of dynamic logic circuits is
presented. This technique makes dynamic logic gates more tolerant to
noise appearing at the gate inputs. A multiply-accumulate circuit has
been designed and fabricated using a 0.35um process to verify this
technique. Experimental results indicate that the twin-transistor
technique provides a significant improvement in the noise immunity of
dynamic circuits (>2.4X), with only a modest increase in power
dissipation (15%) and no loss in throughput.
(Back to Sessions List)
Session 20 - Noise Analysis and Circuit Modeling For RF Applications
Chairman: Georges Gielen
Co-Chairman Edoardo Charbon
This session first describes new techniques for the analysis of phase
noise and jitter in RF circuits. New methods for RF circuit modeling and
model extraction are presented.
8:30am - Introduction
20.1 - 8:35am
Noise in Mixers, Oscillators, Samplers, and Logic An Introduction to
Cyclostationary Noise (Invited)
J. Phillips and K. Kundert, Cadence
Design Systems, San Jose, CA
Abstract :
The origins and characteristics of cyclostationary noise are described
in a way that allows designers to understand the impact of
cyclostationarity on their circuits. In particular, cyclostationary
noise in time-varying systems (mixers), sampling systems (switched
filters and sample/holds), thresholding systems (logic circuitry), and
autonomous systems (oscillators) is discussed.
20.2 - 9:25am
Complete Noise Analysis for CMOS Switching Mixers Via Stochastic
Differential Equations
D. Ham and A. Hajimiri, California Institute of
Technology, Pasadena, CA
Abstract :
A complete analysis of noise in CMOS switching mixers using stochastic
differential equations is presented. This analysis takes both
cyclostationary noise sources and capacitive high frequency effects into
account. This analysis provides important design insights for mixer
design and fast simulation technique for noise calculation.
20.3 - 9:50am
Analysis of Jitter due to Power-Supply Noise in Phase-Locked Loops
P.
Heydari and M. Pedram, University of Southern California, Los Angeles,
CA
Abstract :
Phase-locked loops (PLL) in RF and mixed signals VLSI circuits
experience supply noise which translates to a timing jitter. In this
paper an analysis of the timing jitter due to the noise on the power
supply rails is presented. Stochastic models of the power supply noise
in VLSI circuits for different values of on-chip decoupling capacitances
are presented first. This is followed by calculation of the phase noise
of the voltage-controlled oscillator (VCO) in terms of the statistical
properties of supply noise. Finally the timing jitter of PLL is
predicted in response to the VCO phase noise. A PLL circuit has been
designed in 0.35um CMOS process, and our mathematical model was applied
to determine the timing jitter. Experimental results prove the accuracy
of the predicted model.
20.4 - 10:15am
Nonlinear Behavioral Modeling and Simulation of Phrase-Locked and
Delay-Locked Systems
L. Wu, H. Jin and W. Black, Iowa State University,
Ames, IA
Abstract :
A new method is proposed for modeling VCO and Voltage Controlled Delay
Line (VCDL) circuits that allows inclusion of device noise and supply
coupling effects with simplified numerical computation. PLL and DLL
behavioral simulations allow accurate prediction of system performance
during both locked and unlocked conditions with a great reduction in CPU
time over transistor level simulators. Simulation results are presented
and compared with theoretical predictions and measurement results, that
demonstrate the effectiveness of this scheme.
20.5 - 10:40am
Automated Extraction of Nonlinear Circuit Macromodels
J. Phillips,
Cadence Design Systems, San Jose, CA
Abstract :
Model reduction is a popular approach for incorporating detailed
physical effects into high level simulations. In this paper we present a
simple method for automatically extracting macromodels of nonlinear
circuits with time-varying operating points. The models are truly
"reduced", meaning that the complexity of macromodel generation is not
strongly dependent on the size or complexity of the original detailed
circuit description.
20.6 - 11:05am
Finite-Length Signal Quantization using Discrete Optimization
M.Chapman*, A. Demir and P. Feldmann, Bell Laboratories, Lucent
Technologies, Ascot, United Kingdom and *Murray Hill, NJ
Abstract :
This paper introduces a novel, discrete optimization based method for
the computation of coarsely quantized, oversampled finite-length digital
signals. The method, while only suitable for off-line computation, is
more general than the established sigma-delta encoding technique, due to
its capacity to take into account complex specifications and design
trade-offs. Signal generation is formulated as a linearly constrained,
convex, integer quadratic programming problem which is solved through an
application specific branch-and-bound algorithm. The optimization method
is illustrated with a fractional-N frequency synthesizer based modulator
design example.
(Back to Sessions List)
Session 21 - Digital and Hybrid Signal Processing
Chairman: Alan Willson
Co-Chairman Jackie Snyder
This session addresses signal processing techniques for high-speed
applications. Performance improvements are achieved by employing novel
digital and analog architectures, mixed signal processing, and combined
programmable/dedicated digital implementations.
8:30am - Introduction
21.1 - 8:35am
A 4-Tap 125-MHz Mixed-Signal Echo Canceller for Gigabit Ethernet on
Copper Wire
T.-C. Lee and B. Razavi, University of California, Los
Angeles, CA
Abstract :
A discrete-time analog echo canceller is described that reduces the echo
in the front end of Gigabit Ethernet twisted-pair interfaces. Echo
cancellation in the analog domain by means of four taps reduces the
complexity of the digital echo canceller and crosstalk cancellers by 50
taps. Designed in a 0.4 um-CMOS technology, the circuit employs an LMS
algorithm to adapt to the cable length and impedance discontinuities,
providing an echo suppression of 10 dB. The design operates at 125 MHz
while consuming 43 mW from a 3-V supply.
21.2 - 9:00am
A Low Complexity Joint Equalizer and Decoder for 1000Base-T Gigabit
Ethernet
E. Haratsch and K. Azadet, Bell Laboratories, Lucent
Technologies, Holmdel, NJ
Abstract :
A VLSI architecture is presented which removes post-cursor intersymbol
interference and decodes the trellis coded signals in 1000Base-T Gigabit
Ethernet. Compared to a conventional implementation, the hardware
complexity and critical path are substantially reduced. The design has
been implemented in 3.3V 0.25um standard cell CMOS process for operation
at 125MHz.
21.3 - 9:25am
A PN-Acquisition ASIC for Wireless CDMA Systems
C. Deng and C. Chien*,
University of California, Los Angeles, CA and *Rockwell Science Center,
Thousand Oaks, CA
Abstract :
CDMA spread-spectrum systems require PN-acquisition to synchronize the
transmitted signal at the receiver. Fast acquisition minimizes the
amount of synchronization overhead required in the communication link
for maximum system throughput. Yet, the fast acquisition should be done
with low energy for portable applications. Conventional techniques,
using matched filters or serial correlators alone, offer either fast
pseudo-noise (PN) acquisition for CDMA or low power dissipation but not
both. This paper presents an ASIC which implements an hybrid PN
acquisition architecture that achieves both fast acquisition and up to
50% reduction in energy dissipation compared to conventional techniques.
This ASIC has been fabricated using 0.5-um technology with an area of 23
mm2. It operates at 20 MHz with a 3.3V supply and dissipates 50 mW per
acquisition, or less than 1.5 mW per 50 byte packet.
21.4 - 9:50am
Media Processor Core Architecture for Realtime, Bi-Directional
MPEG4/H.26X Codec with 30 fr/s for CIF-Video
T. Kamemaru, H. Ohira, H.
Suzuki, K. Asano, M. Yoshimoto and T. Murakami, Mitsubishi Electric Co.,
Ltd., Kanagawa, Japan
Abstract :
We have developed a media processor core for MPEG4/H.26X codec LSI,
which realizes a real-time bi-directional encoding/decoding for
CIF-resolution video at the frame rate of 30 fr/s. It features a
MPEG-oriented hybrid architecture which incorporates a SIMD processor
optimized for matrix-operation, a programmable VLC engine and a
2-dimentional multifunction DMA.
21.5 - 10:15am
Efficient and Reusable Time-Sharing Architectures for Equalizer
Structures
S. Meier and M. Schobinger, Infineon Technologies AG,
Munich, Germany
Abstract :
Efficient and reusable time-sharing architectures are derived, that
allow the implementation of a time-domain equalizer and similar
functions. The fact that the clock rates in modern sub-um CMOS processes
are much higher than the usually required sample rates can be exploited
for a significant reduction of chip area. Special care is taken to
preserve the known advantages of very efficient architectures like
bitplane-based filter structures.
21.6 - 10:40am
A Locally-Clocked Dynamic Logic Serial/Parallel Multiplier
G. Hoyer
and C. Sechen, University of Washington, Seattle, WA
Abstract :
Locally-Clocked (LC) Dynamic Logic is an asynchronous circuit technique
that uses an event-driven controller to moderate a fine-grained pipeline
consisting of latching dynamic logic gates. This paper extends the
methodology to include feedback between successive pipeline stages. LC
Dynamic Logic's ability to handle feedback is illustrated with the
design of a 660 MHz serial/parallel multiplier implemented in a 1um, 5V
CMOS process.
Back to Sessions List