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Session 14 - High-Speed Data Communication/Storage Circuits
Chairman: Sang-Soo Lee
Co-Chairman Fang Lu
This session features signal-processing techniques on advanced
communication and storage ICs. Papers in this session includes chips
for ADSL, cable modem, SDH/PDH, HDD read/write channel, power-line FSK
transceiver, and on-chip isolated AFE for V.90 modem applications.
2:00pm - Introduction
14.1 - 2:05pm
A CMOS ADSL Codec for Central Office Applications
P. Siniscalchi, J.
Pitz, R. Hester, S. DeSoto, M. Wang, S. Sridharan, R. Halbach, D.
Richardson, W. Bright, M. Sarraj, J. Hellums, C. Betty and G. Westphal,
Texas Instruments, Inc., Dallas, TX
Abstract :
A CMOS central office codec that supports Full Rate and G.Lite ADSL
applications is described. The transmit channel consists of
application-dependent digital filters, a 14 bit, 8.832 MSample/s DAC, a
1.104 MHz analog filter and programmable attenuation. The receive
channel contains programmable gains, analog and digital low-pass filters
and a 14 bit, 2.208 MSample/s pipeline ADC. The IC dissipates 450 mW
from 3.3 V.
14.2 - 2:30pm
A 4 Channel Analog Front End for Central Office ADSL Modems
J. Kenney,
F. Sabouri, V. Leung, J. Guido, E. Zimany, A. Agrillo, J. Trackim, J.
Khoury* and R. Shariatdoust, Analog Devices, Inc., Somerset, NJ and
*Lucent Technologies, Allentown, PA
Abstract :
This chip integrates a 4 channel analog front-end for central office
ADSL modems. The receive path has a programmable gain amplifier (PGA)
with 30 dB of range followed by a fourth-order 2-bit sigma-delta
modulator clocking at 35MHz. The transmit path uses a 14-bit current
steering D/A converter followed by a fourth-order low-pass filter. The
device is implemented in 0.35um CMOS and consumes less than 160 mW per
channel. It is packaged in a 100 pin MQFP package.
14.3 - 2:55pm
A Single-Chip Universal Burst Receiver for Cable Modem/Digital Cable-TV
Applications
F. Lu, J. Min, S. Liu, K. Cameron, C. Jones, O. Lee, J.
Li, A. Buchwald, S. Jantzi, C. Ward, K. Choi, J. Searle and H. Samueli,
Broadcom Corp., Irvine, CA
Abstract :
This paper presents a single-chip cable upstream receiver which
demodulates QPSK/16-QAM burst data in a frequency-agile, time-division
multiple access (TDMA) scheme. An analog front end (AFE), an all-digital
receiver and an FEC decoder are integrated on chip. The AFE performs
coarse gain setting and signal quantization on either an IF input or
baseband I/Q inputs. The digital QAM receiver contains a quadrature
down-mixer, multi-stage decimators, Nyquist filters, carrier/timing
acquisition loops, and an adaptive equalizer. The FEC decoder consists
of a programmable descrambler and a versatile Reed-Solomon decoder. The
chip occupies 4.7 x 7.8 mm2 die area in a 0.35-um CMOS process, and
consumes 1.0 W at 3.3 V in a 100-pin PQFP.
14.4 - 3:20pm
A Single Chip 155Mbps/140Mbps SDH/PDH Transceiver
J. Guinea, L.
Tomasini, S.Maggio* and M. Rutar*, ST Microelectronics, Agrate, Italy
and *Alcatel Italia, Vimercate, Italy
Abstract :
The 155Mbps (STM-1electrical) transceiver complies with relevant ITU-T
recommendations. The transmiter features CMI transmission
(transformerless) with specified Jitter-generation. On the receiver,
Jitter-tolerance and Bit-error-rate performance is attained. The cable
equalizer supports 13.7dB loss (Nyquist-frequency) with an eye-closure
less than 600psec. Device uses one master-clock (155MHz) and a DLL for
TX and RX synchronization. Targetted crosstalk isolation is reached with
0.35um BiCMOS technology. The TQFP48 IC powered from 3.3V consumes
390mW.
14.5 - 3:45pm
A 450Mbit/s Parallel Read/Write Channel with Parity Check and 16-State
Time Variant Viterbi
G. Bollati, A. Dati, G. Betti, I. Bietti, F.
Brianti, M. Bruccoleri, M. Coltella, P. Demartini, M. Demicheli,
P.Gadducci, S. Marchese, D. Ottini, V. Pisati, F. Rezzi, A. Rossi, P.
Savo, C. Tonci and R. Castello*, STMicroelectronics, Milan, Italy and
*Universita'di Pavia, Pavia, Italy
Abstract :
A PRML Read/Write IC operating up to 450Mbit/s is presented. The chip
implements a 16-state EPR4 Parity Check Time Variant Viterbi detector
and a digital servo. A 24/26 code with parity check improves the
robustness to white noise, media noise and to off-track operations. The
device is integrated in a mature 0.35um technology with a die size of
13mm2 and dissipates 1.9W in Read Mode at 450Mbit/s.
14.6 - 4:10pm
A Versatile Low-Power Power Line FSK Transceiver
R. Cappelletti and A. Baschirotto*, STMicroelectronics, Cornaredo,
Italy and *University of Leece, Leece, Italy
Abstract :
The operations of a Power-Line-Modem are controlled by an internal 24bit
register in order to satisfy the requirement of several protocols for
power-line communications and home automation. The PLM, realized in a
0.6um BCD-technology, from a 9V supply, in Tx mode, delivers 1W on
16ohms, while in Rx mode it consumes 3.5mA.
14.7 - 4:35pm
An Analog Front-End LSI with On-Chip Isolator for V.90 56kbps Modems
N.
Kanekawa, Y. Kojima, S. Yokutake, N. Minehiro, T. Iwasaki, K. Takami,
Y. Takeuchi*, A. Yano* and Y. Shima*, Hitachi Res. Lab, Ibaraki, Japan
and *Device Development Center, Tokyo, Japan
Abstract :
This paper presents an Isolated Analog Front-End (I-AFE) LSI with
built-in isolation function for V.90, 56kbps modems. The LSI has
1.5kVrms. AC isolation and analog front-end functions. The on-chip
isolation approach eliminates external isolation devices such as
transformers or photo-couplers.
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Session 15 - Radio Integration: Architecture, Components and Technology
Chairman: Trudy Stetzler
Co-Chairman Georges Gielen
This session focuses on integration trends in wireless systems and the
impact of CMOS technology trends on RF circuits. Examples include a
novel CMOS T/R switch, new approaches to integrated transformers and
techniques to reduce substrate noise.
2:00pm - Introduction
15.1 - 2:05pm
Silicon Radio Integration: Architectures and Technology: From Cartesian
Zero IF Receive & Transmit to Polar Zero I and Q, From Silicon Bipolar
to Bulk and SOI CMOS (Invited)
J. Sevenhans, Antwerp, Belgium
Abstract :
15.2 - 2:55ppm
A 900-MHz T/R Switch with a 0.8-dB Insertion Loss Implemented in a
0.5-um CMOS Process
F. Huang and K. O., University of Florida,
Gainesville, FL
Abstract :
A single-pole, double-throw transmit/receive switch for 3.0-V
applications has been fabricated in a 0.5-um CMOS process. The switch
exhibits a 0.8-dB insertion loss and a 17-dBm P1dB. The low insertion
loss is achieved by optimizing the transistor widths and bias voltages,
and by minimizing the substrate resistances, while the high 1dB
compression point is achieved by dc biasing the input and output nodes.
15.3 - 3:20ppm
Stacked Inductors and 1-to-2 Transformers in CMOS Technology
A.
Zolfaghari, A. Chan and B. Razavi, University of California, Los
Angeles, CA
Abstract :
A modification of stacked spiral inductors increases the self-resonance
frequency by 100% with no additional processing steps, yielding values
of 5 nH to 266 nH and self-resonance frequencies of 11.2 GHz to 0.5 GHz.
Closed-form expressions predicting the self-resonance frequency with
less than 5% error have also been developed. A 1-to-2 transformer
consisting of 3 stacked spirals achieves a voltage gain of 1.8 at 2.5
GHz. The structures have been fabricated in standard CMOS technologies
with four and five metal layers.
15.4 - 3:45pm
An Integrated Capacitively Coupled Transformer and Its Application for
RF IC's
L.-P. Wong, C. Snyder, T. Manku and S. Kovacic*, University of
Waterloo, Waterloo, Canada and *SiGe Microsystems, Inc., Ottawa, Canada
Abstract :
This paper describes a low voltage topology that uses a capacitively
coupled transformer element. The structure is used to design a 1V LNA
at 1.9GHz. The LNA consumes 4mA of current has an IP3in of -4.5dBm, a
NF50 of 2.3dB, a NFmin of 1.9dB, and a gain of 10.1dB.
15.5 - 4:10pm
Measuring and Modeling the Effects of Substrate Noise on the LNA for a
CMOS GPS Receiver
M. Xu, D. Su, D. Shaeffer, T. Lee and B. Wooley,
Stanford University, Stanford, CA
Abstract :
The influence of substrate noise generated in digital circuit on the
low-noise amplifier (LNA) of a CMOS GPS receiver has been experimentally
characterized and theoretically analyzed. A frequency domain approach is
used to model noise injection into the substrate from the digital
circuitry and the mechanisms by which that noise can affect analog
circuit behavior. The results reveal that substrate noise can modulate
the LNA input signals as well as directly couple to the LNA output.
15.6 - 4:35pm
Active Substrate Noise Suppression In Mixed-Signal Circuits Using
On-Chip Driven Guard Rings
W. Winkler and F. Herzel, Institute for
Semiconductor Physics, Frankfurt, Germany
Abstract :
The paper presents an active substrate noise suppression circuit using a
pair of concentric guard rings. A SiGe on-chip amplifier injects
inverted substrate noise such that efficient noise cancellation is
achieved. A ring oscillator is used to sense the residual substrate
noise. The measured noise suppression bandwidth is as high as 400 MHz.
15.7 - 5:00pm
Impact of Technology Scaling on CMOS RF Devices and Circuits
E.
Abou-Allam, T. Manku, M. Ting and M. Obrecht, University of Waterloo,
Waterloo, Canada
Abstract :
Devices from 0.18um, 0.25um, 0.35um, 0.5um, and 0.8um CMOS technologies
are characterized and compared in terms of their RF performance. The
ratio of transconductance to bias current (gm/Ids) becomes higher as the
device length gets smaller. A 1V receiver front-end is designed, the LNA
has 1.7 dB noise figure and 14 dB gain and the mixer has an IIP3 of 11
dBm. The power dissipation is 33mW and 6mW for the 0.5um and 0.18um
receivers, respectively.
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