(Back to Sessions List)
Session 9 - MOS Device Modeling
Chairman: Hidetoshi Onodera
Co-Chairman Steffen Rochel
Accurate and scalable MOSFET modeling is a fundamental requirement for
successful circuit design and validation, especially for emerging
technologies such as RF and SOI.
8:30am - Introduction
9.1 - 8:35am
MOS Transitor Modeling for RF Integrated Circuit Design (Invited)
C.
Enz, CSEM, Neuchatel, Switzerland
Abstract :
The design of radio-frequency (RF) integrated circuits in deep-submicron
CMOS processes requires accurate and scalable compact models of the MOS
transistor that are valid in the GHz frequency range and even beyond.
Unfortunately, the currently available compact models give inaccurate
results if they are not modified adequately. This paper presents the
basis of the modeling of the MOS transistor for circuit simulation at
RF. A physical and scalable equivalent circuit that can easily be
implemented as a Spice subcircuit is described. The small-signal, noise
and large-signal operations are discussed and measurements made on a
0.25 um CMOS process are presented that validate the RF MOS model up to
10 GHz.
9.2 - 9:25am
BSIMPD: A Partial-Depletion SOI MOSFET Model for Deep-Submicron CMOS
Designs
P. Su, S. Fung*, S. Tang, F. Assaderaghi* and C. Hu, University
of California at Berkeley, Berkeley, CA and *IBM Semiconductor Research
and Development Center, Hopewell Junction, NY
Abstract :
BSIMPD- a physics-based SPICE model is developed for bridging
deep-submicron CMOS designs using partially-depleted SOI technologies.
Formulated on top of the industry-standard bulk-MOSFET model BSIM3v3 for
a sound base of scalability and robustness, BSIMPD captures SOI-specific
dynamic behaviors with its built-in floating-body, self-heating and
body-contact models. A parameter-extraction strategy is demonstrated,
and the simulation efficiency is studied. The model has been tested
extensively within IBM on state-of-the-art high speed SOI technologies.
It has been implemented in many circuit simulators.
9.3 - 9:50am
New Paradigm of Predictive MOSFET and Interconnect Modeling for Early
Circuit Simulation
Y.Cao, T. Sato*, M. Orshansky, D. Sylvester** and C.
Hu, University of California at Berkeley, Berkeley, CA, *Hitachi Ltd.,
Tokyo, Japan and **Synopsys Inc., Mountain View, CA
Abstract :
A new paradigm of predictive MOSFET and interconnect modeling is
introduced. This approach is developed to specifically address SPICE
compatible parameters for future technology generations. For a given
technology node, designers can use default values or directly input
Leff, Tox, Vt, Rdsw and interconnect dimensions to instantly obtain a
BSIM3v3 customized model for early stages of circuit design and
research. Models for 0.18um and 0.13um technology nodes with Leff down
to 70nm are currently available on the web. Comparisons with published
data and 2D simulations are used to verify this predictive technology
model.
9.4 - 10:15am
RFCMOS Extension Model Accurate up to 40 GHz with Distributed Junction
Diode
T. Kuo, VLSI Technology, San Jose, CA
Abstract :
A 0.2-um RFCMOS extension model valid up to 40GHz using BSIM3v3 as core
transistor is presented. To account for model accuracy beyond 20GHz, a
distributed junction diode and substrate network model is introduced. In
addition, a new approach for extracting parasitic gate resistance has
been developed. To account for induced gate noise, a small signal
equivalent circuit is used to simulate the noise performance. Excellent
agreement is achieved with this noise model.
9.5 - 10:40am
Advanced Compact Model for Short-Channel MOS Transistors
O. da Costa Gouveia-Filho*, A. Cunha**, M. Schneider and C.
Galup-Montoro, LCI, Florianopolis, Brazil, *CIEL, Curitiba, Brazil and
**Escola Politecnica, Salvador, Brazil
Abstract :
This paper introduces the advanced compact MOSFET (ACM) model, a
physically based model of the MOS transistor, derived from the
long-channel transistor model presented in (1). The ACM model is
composed of very simple expressions, is valid for any inversion level,
conserves charge and preserves the source-drain symmetry of the
transistor. Short-channel effects are included using a compact and
physical approach. The performance of the ACM model in benchmark tests
demonstrates its suitability for circuit simulation.
9.6 - 11:05am
S-TFT: An Analytical Model of Polysilicon Thin-Film Transistors for
Circuit Simulation
G.-Y. Yang, Y.-G. Kim, T.-S. Kim and J.-T. Kong,
Samsung Electronics Co., Kyunggi-Do, Korea
Abstract :
This paper describes the S-TFT model developed for poly-Si TFT which
improves the accuracy dramatically. The proposed model emphasizes on
deriving the large parasitic resistance characteristics at low Vds by
adding the junction current to the on-current. The physical-based
subthreshold and off-state current model are also considered. The model
guarantees the continuities of the current and the derivatives.
Compared to the RPI model, known to be the best model, the proposed
model improved overall simulation speed by 40~50% due to the better
convergence characteristics.
(Back to Sessions List)
Session 10 - System-on-a-Chip: From Concept to Consumer
Chairman: Michele Taliercio
Co-Chairman Ann Rincon
This session demonstrates that SOC is now a reality. The proof is shown
by six real-life designs covering voice and video recording,
communication, internet devices, and secure contactless smart-cards.
8:30am - Introduction
10.1 - 8:35am
A 64-min Single-Chip Voice Recorder/Player using Embedded 4bit/cell
Flash Memory
M. Borgatti, A. Rocchi, M. Bisio, M. Besana, L. Navoni
and P. Rolandi, STMicroelectronics Central R&D, Agrate, Italy
Abstract :
A system-on-chip prototype implements a full integration of a 64-minutes
digital voice recorder/player embedding a 4bit/cell multilevel digital
Flash memory. A speech coder/decoder (8 to 40kbps), a MCU and an
8Mcell/32Mb multilevel Flash memory with fully digital on-chip BIST
solution are integrated in a 0.5um embedded Flash technology. The
system features a modular architecture allowing full reuse and
mix-and-match of its IP building blocks. The chip counts 13M transistors
at 225mm2 area.
10.2 - 9:00am
A Low-Power System-on-Chip for the Documentation of Road Accidents
L.
Bolcioni and R. Guerrieri, University of Bologna, Bologna, Itlay
Abstract :
This paper presents the design flow of a video encoder system that
reaches 15 QCIF frames/s applying a digital signature on the encoded
bitstream. The system has been implemented in 6x6 mm2 on a 0.25um,
6-metal standard cell CMOS working at 40MHz, 2.5V power supply.
10.3 - 9:25am
Designing High-Speed Serial Ports Using Standard ASIC Library Elements
Tools and Design Methodologies
P.Freud, IBM Microelectronics, Waltham, MA
Abstract :
This paper describes a high-speed serial port design approach which uses
standard ASIC libraries, tools and design methodologies. Leveraging
existing ASIC tools and technology enabled us to build and verify serial
links running up to 622 Mb/s. Our approach has been validated with a
detailed comparison of Spice to static timing analysis.
10.4 - 9:50am
A 9-M Tr. Access Network System-On-a-Chip for Mega-bit Internet Access
at Home
S. Kozu, T. Aramaki, C. Ikeda, Y. Kuroda, S. Kawanago, M. Okada,
H. Kariya, M. Manabe, H. Utani, E. Sudou, Y. Oda and H. Suzuki, NEC
Corporation, Kanagawa, Japan
Abstract :
In this paper, an Access Network Controller for ADSL (Asymmetric Digital
Subscriber Line) is described. It consists of a VR4120 MPU core, a
system controller, an Ethernet controller, an ATM (Asynchronous Transfer
Mode) cell processor, a USB (Universal Serial Bus Interface) controller,
and other blocks. This controller, along with ADSL PHY devices, can
provide a total solution for ADSL modem and ADSL router.
10.5 - 10:15am
A 300K-gate 0.5um CMOS Implementation of An 8-VSB Receiver IC
I. Lee,
D. Kim, S. Lee, K. Kwon, J. Kim, I. Kim, Y. Kim, S. Park, C. Kim, H.
Jung and G. Chang, Daewoo Electronics Corp., Seoul, Korea
Abstract :
This paper presents an integrated 8-VSB receiver IC which demodulates
and decodes the ATSC-compliant terrestrial RF transmission signal. The
design has been accomplished in an ASIC-vendor independent way using
only HDL description and synthesis tools. It can receive any IF signal
of 5.38MHz or 44MHz. The chip has been implemented with equivalent 300k
gates comprising 200k logic parts and 100k gate-equivalent memory parts
in an area of 8.0x7.7 mm2. The chip is operative at 50MHz and consumes
approximately 3.2W under 5 volts in a commercial operating condition.
10.6 - 10:40am
Secure Contactless Smartcard ASIC with DPA Protection
P. Rakers, L.
Connell, T. Collins* and D. Russell*, Motorola Labs, Schaumburg, IL and
*Motorola Worldwide Smartcard Solutions Division, Schaumburg, IL
Abstract :
A 10% ASK Smartcard ASIC achieves 3e-10 BER in the presence of digital
noise. A 2000 times reduction in digital signature amplitude greatly
improves security against DPA attack. Voltage compliance is maintained
for more than two decades of received power. The 2.8-mm X 2.9-mm ASIC is
fabricated in a 0.6 micron CMOS process with EEPROM.
(Back to Sessions List)
Session 11 - High Speed Data Conversion
Chairman: L. Richard Carley
Co-Chairman Yusuf Haque
This session describes high-speed data conversion techniques ranging
from a 1 GHz sample-and-hold circuit to high speed pipelined & flash
ADCs to high speed DACs.
8:30am - Introduction
11.1 - 8:35am
A Broadband 10 GHz Track-And-Hold In Si/Sige HBT Technology
J. Jensen
and L. Larson, University of California at San Diego, San Diego, CA
Abstract :
This paper presents a track-and-hold amplifier with an input bandwidth
in excess of 10GHz, implemented in a 45GHz BiCMOS Si/SiGe process.
Based on a diode bridge design this IC consumes approximately 550mW and
can accommodate an input voltages up to 600mV with an IIP3 of greater
than 25dBm.
11.2 - 9:00am
A 6-bit 1 GHz Acquisition Speed CMOS Flash ADC with Digital Error
Correction
K. Uyttenhove, A. Marques* and M. Steyaert, Katholieke
Universiteit Leuven, Heverlee, Belgium and *University of Coimbra,
Chipidea, Portugal
Abstract :
A 6-bit ADC with a maximum acquisition speed of 1 GHz is presented.
Special attention was paid on metastability-problems which degrade SFDR
at high sampling frequencies. SFDR is more than 38 dB at Fclk = 500 Mhz.
The chip has been processed in a standard 0.35um CMOS technology.
11.3 - 9:25am
A 100-MSPS 8-b CMOS Subranging ADC with Parametric Operation From 3.8 V
Down to 2.2 V
R. Taft and M. Tursi, National Semiconductor East Coast
Labs, Fuerstenfeldbruck, Germany
Abstract :
A 100-MSPS 8-bit ADC obtains very low supply voltage operation with four
circuit techniques: Differential T-gate boosting, a unified coarse/fine
analog channel with dual gain, a supply independent delay generator, and
a delay-lock loop digital output driver. A maximum DNL below 0.5 LSB
and 7.0 (7.3) effective bits for a 50 MHz (10 MHz) input are maintained
down to 2.2 V, 84 mW.
11.4 - 9:50am
A 10-bit, 3V, 100MS/s Pipelined ADC
D. Nairn, Analog Devices,
Greensboro, NC
Abstract :
The design of a low-power 10-bit, 100MS/s ADC is presented. The ADC is
based on a pipelined architecture in which the number of bits converted
per stage and the stage sizes were optimized to simultaneously achieve
the desired linearity while minimizing the total power. When operated
at 100MS/s with a 3V supply the ADC core dissipates 105mW. The ADC was
fabricated in a 0.35um double poly CMOS process.
11.5 - 10:15am
A Highly Linear Low-Power 10 bit DAC for GSM
P. Ferguson, X. Haurie
and G. Temes*, Analog Devices, Inc., Wilmington, MA and *Oregon State
University, Corvallis, OR
Abstract :
A 10-bit 6.5 MS/s DAC designed for a GSM baseband transmit channel is
described. It features a low power quasi-passive architecture with
segmentation and element mismatch-shaping used in the conversion of the
four MSBs. The DAC achieves less than 1/4 bit DNL and 0.6 bit INL at
the 10-bit level with no calibration or trimming.
11.6 - 10:40am
A 10 bit 1-G Sample/s Nyquist Current-Steering CMOS D/A Converter
A.
Van den Bosch, M. Borremans, M. Steyaert and W. Sansen, Katholiecke
University Leuven, Heverlee, Belgium
Abstract :
In this paper, a 10 bit 1 GS/s current-steering CMOS D/A converter is
presented. The measured INL is better than +/-0.2 LSB. The 1 GSample/s
conversion rate has been obtained by a fully custom designed thermometer
decoder. The dynamic limitations have been solved, resulting in more
than 61 dB measured SFDR in the interval from DC to Nyquist at all
conversion rates up to 1 GS/s. At this conversion rate, the power
consumption equals 110 mW. The chip has been processed in a standard
0.35um CMOS technology and has an active area of only 0.35 mm2.
(Back to Sessions List)
Session 12 - Embedded Memory
Chairman: Cormac O'Connell
Co-Chairman Joe Ting
This session encompasses the entire spectrum of design disciplines
including virtual- socket methodology, low-power architectures, 9ns Trac
EDRAM, advanced dielectrics in processing, flash-based redundancy, and
at-speed 1 GHz BIST.
8:30am - Introduction
12.1 - 8:35am
Design Methodology of the Embedded DRAM with the Virtual Socket
Architecture
M. Kinoshita, T. Yamauchi, T. Amano, K. Dosaka and K.
Arimoto, Mitsubishi Electric Corporation, Hyogo, Japan
Abstract :
We proposes the virtual socket architecture which provide the embedded
DRAM control circuitry as the software macro to take advantage of the
automated tools based on the synchronous circuit design. We applied this
architecture with array generator to the 0.18um embedded DRAM test
device and confirmed over 166Mhz operation .
12.2 - 9:00am
Low-Power Technique for On-Chip Memory Using Biased Partitioning and
Access Concentration
N. Kawabe and K. Usami, Toshiba Corporation,
Kawasaki, Japan
Abstract :
We propose a low-power technique for on-chip memory using biased
partitioning and access concentration technique. Memory array is
partitioned into different size of two sub-arrays. In addition, code
motion is performed to concentrate memory access on the smaller
sub-array. Power of instruction memory of MPEG4 Codec was reduced by
40%.
12.3 - 9:25am
A 1.8-V Embedded 18-Mb DRAM Macro with a 9-ns RAS Access Time and Memory
Cell Efficiency of 33%
Y. Yokoyama, N. Itoh, M. Katayama*, K.
Takashima, H. Akasaki*, M.Kaneda*, T.Ueda*, Y. Tanaka, E. Yamasaki*, M.
Todokoro*, K. Toriyama, H. Miki**, M. Yagyu**, T. Kobayashi, S. Miyaoka
and N. Tamba, Hitachi, Ltd., Tokyo, Japan, *Hitachi ULSI Systems Co.,
Ltd., Tokyo, Japan and **Hitachi Ltd., Central Research Lab., Tokyo,
Japan.
Abstract :
A 1.8-V embedded 18-Mb DRAM with memory-cell efficiency of 33% that is
achieved by a single-side interface architecture has been developed. A
9-ns RAS access time and a 4.6-ns CAS access time that enables a
data-translation rate of 40 Gb/s was achieved. To achieve fast access
time, it uses a multi-word redundancy scheme and a YS merged sense
scheme. Noise restraint capacitors are introduced to reduce the induced
noise to as low as 100mV for simultaneous wide bandwidth operation with
VDD of 1.8 V.
12.4 - 9:50am
An Ultra-High-Density High-Speed Loadless Four-Transistor SRAM Macro
with a Dual-Layered Twisted Bit-Line and a Triple-Well Shield
K. Noda,
K. Matsui, S. Ito, S. Masuoka, H. Kawamoto, N. Ikezawa, K. Takeda*, Y.
Aimoto*, N. Nakamura*, H. Toyoshima*, T. Iwasaki** and T. Horiuchi, NEC
Corporation, *Silicon Systems Research Laboratories and **NEC Informatec
Systems, LTD., Kanagawa, Japan
Abstract :
We have developed two schemes for improving access speed and reliability
of a loadless four-transistor (4T) SRAM cell: a dual-layered twisted bit
line, and triple-well shielding. We incorporated these technologies in
a 0.18-um CMOS process and fabricated a 16-Mb SRAM macro with a 1.9-um2
memory cell. This macro fully functions at 400 MHz and has an access
time of 2.35 ns.
12.5 - 10:15am
SRAM Embedded Memory with Low Cost FLASH EEPROM-Switch-Controlled
Redundancy,
R. McPartland, D. Loeper, F. Higgins*, R. Singh**, G.
MacDonald, G. Komoriya, S. Aymeloglu, M. DePaolis and C. Leung**, Bell
Laboratories, Lucent Technologies, Allentown, PA, *Princeton, NJ and
**Orlando, FL
Abstract :
This paper describes the use of low cost, Flash EEPROM switches to
control redundancy in SRAM embedded memories. Flash cell design,
operation and process technology are described. A 768K-bit embedded SRAM
memory with Flash controlled column redundancy and built in self-repair
is presented.
12.6 - 10:40am
Embedded DRAM: An Element and Circuit Evaluation
P. Diodato, J.
O'Neill*, Y.-H. Wong, G. Alers, H. Vaidya**, S. Chaudhry***, W.
Lindenberger, A. Dumbri+, C.-T. Liu and W. Lai, Lucent Technologies,
Murray Hill, NJ, *Holmdel, NJ, **Singapore, ***Orlando, FL and
+Allentown, PA
Abstract :
Embedded DRAM memory cells employing advanced capacitor dielectrics
(Ta2O5) have been designed, fabricated, and measured. Memory cell data
retention time is used to compare capacitor characteristics between four
Ta2O5 equipment vendors. Static behavior in one type of DRAM cell is
attributed to the bimodal current-voltage characteristic of the Ta2O5,
and circuit topography.
12.7 - 11:05am
Design Validation of .18 um 1 GHz Cache and Register Arrays
D. Malone,
P. Bunce, J. DellaPietro, J. Davis, J. Dawson, T. Knips, D. Plass, P.
Pritzlaff and K. Reyer, IBM Corp., Poughkeepsie, NY
Abstract :
This paper describes the design and results of SRAM experiments from a
prototype test chip in IBM's .18 um 7 level metal copper technology.
Results and approaches for assuring product applications at 1 Ghz across
wide process ranges will be discussed. Aggressive product cycle time
SRAM applications for IBM's S/390 L2 cache chips require multifaceted
approaches to address the following:
* SRAM operability in product-like clocking and ABIST environments
* Demonstration of yield using 2 dimensional redundancy
* Characterization of SRAM signals used in the macro timing rules
* Obtain high volume pre-product manufacturing test experience
* Verify SRAM functionality at technology stress test conditions
Back to Sessions List