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Session 5 - Test and Reliability
Chairman: Mark Young
Co-Chairman Jim Gilbert
Various aspects of test technology are covered first, with applications
to static-timing analysis, test generation and application, diagnosis,
and mixed-signal self-test. Reliability issues are then discussed,
including ESD for high-speed devices and noise in both cells and
substrate.
2:00pm - Introduction
5.1 - 2:05pm
A Quick And Inexpensive Method To Identify False Critical Paths Using
ATPG Techniques: An Experiment With A PowerPC(TM) Microprocessor
J.
Bhadra, M. Abadir* and J. Abraham, University of Texas at Austin,
Austin, TX and *Motorola Inc., Austin, TX
Abstract :
Static timing analysis tools are used by designers of high speed/high
performance circuits to determine whether timing requirements are met.
Timing analysis tools can report critical paths which are characterized
by a transition on each node along the path, however, they cannot
generate a "witness" vector which would sensitize that path. This gives
rise to the possibility of having paths which are reported by the static
timing analysis tool as potential critical paths, whereas there exists
no vector sequence which can sensitize them. Our goal is to identify
these "false critical paths" safely and without much overhead, so that
the efforts needed to redesign and/or optimize critical paths can be
reduced. We have devised a simple technique using an ATPG tool to meet
this goal. We applied the technique on the state of the art fourth
generation MPC7400 PowerPC(tm) microprocessor designed at Motorola's
PowerPC Design Center in Austin, TX. Our initial experimental results
show the effectiveness of the technique. The salient features of the
technique are that it is both quick and inexpensive.
5.2 - 2:30pm
Modular Test Generation and Concurrent Transparency-Based Test
Translation Using Gate-Level ATPG
Y. Makris, A. Orailglu and P. Vishakantaiah*, University of California,
La Jolla, CA and *Intel Corporation, Hillsboro, OR
Abstract :
We introduce a hierarchical test generation methodology, employing
exclusively gate-level ATPG. While full circuit ATPG is applied, faults
in each module are targeted individually, while the surrounding modules
are replaced by their transparency-equivalent logic. The proposed
methodology results in significant test generation speed-up, while
preserving comparable fault coverage and vector count to full-circuit
ATPG.
5.3 - 2:55pm
Diagnosing Resistive Bridges Using Adaptive Techinques
J.
Ghosh-Dastidar and N. Touba, University of Texas at Austin, Austin, TX
Abstract :
A systematic procedure for locating resistive bridges is presented.
Critical path tracing is used to identify a set of "suspect" bridges
whose presence could explain all of the observed faulty behavior of the
circuit for the original test set. The set of suspects is then reduced
by adaptively applying additional tests derived from the failing vector
pairs in the original test set.
5.4 - 3:20pm
A Stand-Alone Integrated Excitation/Extraction System for Analog BIST
Applications
M. Hafed and G. Roberts, McGill University, Montreal,
Canada
Abstract :
An integrated test core for mixed-signal circuits is described. It
consists of a completely digital implementation, except for a
reconstruction filter and a comparator, and it is capable of generating
arbitrary band-limited waveforms and coherently digitizing arbitrary
periodic analog waveforms. An implementation in a 0.35 um CMOS process
was shown to perform various curve tracing, oscilloscope, and spectrum
analysis tasks.
5.5 - 3:45pm
A New Design for Complete On-Chip ESD Protection
A. Wang, Illinois
Institute of Technology, Chicago, IL
Abstract :
Design of a novel compact Electrostatic Discharge (ESD) protection
structure is reported. It provides complete ESD protection in all
directions, i.e., I/O-to-VDD, I/O-to-ground, and VDD-to-ground. This
ultra-fast structure, good for RF IC's, operates symmetrically and
passed 14KV (HBM). Measurements showed low holding voltage (~2V), low
discharging impedance (~ohm), and adjustable triggering voltages.
5.6 - 4:10pm
Cell Characterization for Noise Stability
K. Shepard and K. Chou*,
Columbia University, New York, NY and *CadMOS Design Technology, San
Jose, CA
Abstract :
Verifying whether a digital standard-cell design is functional in the
presence of interconnect coupling noise is an important concern to ASIC
designers. Determining whether the coupling noise occurring on a node
is excessive requires comparing this noise against the dynamic noise
margins of the receiving gates. The noise stability requirement,
introduced in the context of transistor-level static noise analysis, is
a technique for quantifying these ac noise margins. In this paper, we
describe a technique for modeling noise stability in the form of a
four-parameter rule which can be used to characterize the cells of a
digital standard-cell library.
5.7 - 4:35pm
Quantitative Characterization of Substrate Noise for Physical Design
Guides in Digital Circuits
M. Nagata, J. Nagai, T. Morie and A. Iwata,
Hiroshima University, Higashi-Hiroshima, Japan
Abstract :
Substrate noise is quantitatively evaluated by a gain calibrated
substrate voltage measurements in a 100ps-100uV resolution. Activity is
a key amount to which the noise intensity is proportional. Use of
Kelvin grounding and guardbanding together reaches 75% noise reduction
at maximum, however, the effect is limited to low frequency components
such as a ringing.
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Session 6 - Key Methods for Successful SOCs
Chairman: Scott Baker
Co-Chairman Jim Lipman
System-on-chip success depends on good design techniques. These
problem-solving methods address SOC planning, embedded software
development, design automation, multicore integration, and design
analysis.
2:00pm - Introduction
6.1 - 2:05pm
Improving Embedded Software Design and Integration in SOCs (Invited)
G.
Martin and C. Lennard, Cadence Design Systems, Inc., San Jose, CA
Abstract :
The rapid advances in System-On-Chip (SOC) design enabled by improved
process technology will be hindered unless major improvements are made
in the specification, design and implementation of embedded software.
Embedded software usually makes up at least half of the design content
of an SOC device. In the future, it will constitute an even larger
percentage of the design effort. In this paper we introduce a number of
the major issues involved with design and integration of embedded
software. We discuss some of the most recent standards, trends and
capabilities that will provide effective solutions.
6.2 - 2:55pm
CORAL Automating the Design of Systems-On-Chip Using Cores
R.
Bergamaschi, W. Lee*, D. Richardson* S. Bhattacharya, M. Muhlada*, R.
Wagner**, A.Weiner** and F. White*, IBM TJ Watson Research Center,
Yorktown Heights, NY, *IBM Microelectronics, Research Triangle Park, NC
and ** IBM, Fishkill, NY
Abstract :
The reuse of pre-designed and pre-verified IP blocks or cores has been
touted as the enabler of large systems-on-chip designs. However, the
lack of appropriate tools and the increasing complexity of such cores
makes them inherently difficult and error-prone to use. This paper
presents a new tool, "Coral", for the design of systems using cores.
Coral is based on a new synthesizable virtual design representation
which is automatically synthesized to a real design. Novel algorithms
are presented to interconnect cores automatically as well as configure
system parameters, such as interrupt maps, DMA channel assignments, etc.
Coral significantly reduces the time, complexity and potential for
errors associated with SoC integration.
6.3 - 3:20pm
Wire Planning for Performance and Yield Enhancement
C. Ouyang, K. Ryu*,
H. Heineken, J. Khare, S. Shaikh and M. d'Abreu, Level One
Communications, Inc., Sacramento, CA and *Intel Corporation, Folsom, CA
Abstract :
In this paper, a wire planning strategy at the layout stage is proposed.
The strategy addresses deep sub-micron (DSM) issues facing both
designers and manufacturing engineers. For designers, the proposed
method reduces the magnitude and variance of cross-coupling capacitance,
making interconnect delay smaller and more predictable. For
manufacturing engineers, the method reduces design sensitivity to random
defects and process variations, thereby increasing yield. These
objectives are achieved by directing commercial placement and routing
tools to utilize routing resources more evenly over the entire die.
Example implementations of the wire planning strategy are demonstrated.
6.4 - 3:45pm
Probabilistic Aspects of Crosstalk Problems in CMOS ICs
C. Ababei, R.
Marculescu and V. Sundarajan, University of Minnesota, Minneapolis, MN
Abstract :
In this paper we present a probabilistic approach for analyzing the
dependence of crosstalk effects on input pattern correlations. In
particular, we show that the effects of coupling between
interconnections, in current VLSI ICs, are strongly dependent on the
spatio-temporal correlations at the primary inputs. Consequently, a
smaller fraction of the total number of nets poses true crosstalk
problems and only that fraction should be considered at lower levels of
abstraction. The analysis is carried out at the logic-level of
abstraction, which provides efficient CPU run time and memory usage.
6.5 - 4:10pm
Applying Placement-Based Synthesis for On-Time System-on-a-Chip Design
D. Lackey, IBM Microelectronics, Essex Junction, VT
Abstract :
This paper examines the fundamental issues in timing closure, using
present-day methodologies, for designs enabled by System-on-a-Chip (SOC)
silicon technologies. Placement-based synthesis is proposed as a method
to address these issues, and it's benefits are contrasted against the
problems of current methods. Finally, this paper discusses application
of placement-based synthesis for optimum benefit in enabling on-schedule
SOC design.
6.6 - 4:35pm
Methodology for I/O Cell Placement and Checking in ASIC Designs Using
Area-Array Power Grid
P. Buffet, J. Natonio, Robert A. Proctor, Y. Sun
and G. Yasar, IBM Microelectronics Division, Essex Junction, VT
Abstract :
Electrical rule checking is fundamental to achieve a good I/O cell
placement. This paper presents the analysis techniques used to design a
robust power-grid structure, the method used to make I/O cell placement
guidelines, details of the I/O cell placement process and electrical
checking algorithms.
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Session 7 - Innovations in Programmable Devices
Chairman: Steve Wilton
Co-Chairman Elliot Gould
This session expands the role of programmable logic beyond prototyping
and system emulation. The papers describe the challenge and tradeoffs
when embedding system functions in next-generation architectures.
2:00pm - Introduction
7.1 - 2:05pm
Architecture of Cluster-Based FPGAs with Memory
J. Clifford and S.
Wilton, University of British Columbia, Vancouver, Canada
Abstract :
Embedded memory has become an essential part of FPGAs. In this paper,
we investigate how a particular FPGA architecture can be enhanced by
including a single memory array in each logic cluster. It is shown that
the best overall speed and density results when a cluster contains
between 16 and 20 logic elements and one memory array with 512 or 1024
bits. It is also shown that 40% of the logic and memory element inputs
should be available outside the cluster.
7.2 - 2:30pm
Cypress Delta39K - A Memory-Rich, High Performance, Scalable CPLD
Architecture
A. Kennings, H. Mohammed, J. P. Skudlarek and B. Tian*,
Cypress Semiconductor, Beaverton, OR and *Cypress Semiconductor, San
Jose, CA
Abstract :
The architecture of the Cypress Delta39K CPLD family is described,
including the hierarchical organization, the novel single-source
dedicated-track MUX-based routing architecture, and the large quantity
of on-chip specialty memory. Other essential elements including
Macrocells, I/O Cells and PLL functions are described. Finally, we
mention the speed of the fitting software.
7.3 - 2:55pm
Dynamic Clock Management for Low Power Applications in FPGAs
I.
Brynjolfson and Z. Zilic, McGill University, Montreal, Canada
Abstract :
Low power techniques employing dynamically controlled clock rates offer
potentially powerful energy saving capabilities. In this paper, we
consider the application of this low power technique to FPGAs, where we
reduce energy waste in clock distributions. We show that current FPGA
clock managers are inadequate for use in dynamically controlled systems.
We provide an architectural block, the dynamic clock divider, that can
be added either internally to clock managers or as user logic, to allow
dynamic clock management.
7.4 - 3:20pm
A Million Gate PLD with 622MHz I/O Interface, Multiple PLLs and High
Performance Embedded CAM
S. Cheung, K. Chua, B. Ang, T. Chong, W.
Goay, W. Koay, S. Kuan, C. Lim, J. Oon, T. See, C. Sung, K. Tan, Y. Tan
and C. Wong, Altera Corporation, San Jose, CA
Abstract :
A million gate Programmable Logic Device (PLD) designed for high
performance system integration is discussed. The APEX 20K1000E is
fabricated on a 0.18um CMOS Process. The chip supports multiple I/O
standards with data bandwidth up to 622Mbps when using the integrated
Low Voltage Differential Signaling (LVDS) interfaces. Multiple on-chip
Phase-Locked Loops (PLL) increase performance and provide
clock-frequency synthesis. The embedded Content Addressable Memory
(CAM) enhances performance for fast search applications.
7.5 - 3:45pm
Parallel and Scalable Architecture for Solving SATisfiability on
Reconfigurable FPGA
T. Pagarani, F. Kocan, D.G. Saab and J.A. Abraham*,
Case Western Reserve University, Cleveland, OH and *University of Texas
at Austin, Austin, TX
Abstract :
In this paper, we present different architectures and implementation for
solving the general SATisfiability (SAT) problem on reconfigurable
devices. In particular, we address the solution of this basic and
important problem using multiple small FPGAs. Our approach utilizes
partitioning and decomposition to map any large SAT problem on more than
one small FPGA. First, a SAT problem is decomposed into several
independent sub-problems. This way, all sub-problems may be solved on
different FPGAs simultaneously. If any of the sub-problems can not fit
on a single FPGA, then a second technique is used to divide the
sub-problem into dependent parts. We compute the solution time and
hardware resources for both approaches and also compare our results with
the previously published results.
7.6 - 4:10pm
Spatial - Temporal Mapping of Real Applications on a Dynamically
Reconfigurable Logic Engine (DRLE) LSI
K. Furuta, T. Fujii, M.
Motomura, K. Wakabayashi and M. Yamashina, NEC Corporation, Kanagawa,
Japan
Abstract :
We have used DES and Reed-Solomon applications to evaluate a dynamically
reconfigurable logic engine (DRLE) LSI and have spatially mapped and
temporally partitioned these applications into multiple contexts of a
DRLE LSI. The evaluation shows that the DRLE improved by more than an
order of magnitude over the conventional low-power uP in both
performance and energy consumption.
7.7 - 4:35pm
Field Configurable System-on-Chip - Device Architecture
S. Knapp and
D. Tavana, Triscend Corporation, Mountain View, CA
Abstract :
Integration of microprocessors, memory, peripherals, and programmable
logic is made possible with a new bus architecture called the
Configurable System Interconnect Bus (CSI) developed at Triscend
Corporation. The Configurable System Interconnect Bus was specifically
designed to facilitate re-use, guarantee timing, increase system
throughput, and reduce system debug time in applications that require
intense time-to-market and field upgrade.
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Session 8 - Low-Power Low-Voltage Wireless Systems
Chairman: Vincent Von Kaenel
Co-Chairman Peter Kinget
This exciting session presents low-power and low-voltage fully
integrated RF systems. It includes an overview of CMOS RF design along
with CMOS low-power wireless receivers and transmitters.
2:00pm - Introduction
8.1 - 2:05pm
CMOS RF Design - The Low Power Dimension (Invited)
Q.Huang, Swiss
Federal Institute of Technology
Abstract :
In many wireless applications power consumption of an RF-IC is more
important than integration level due to battery life time
considerations. Growing attention is now being paid to low power design
of CMOS RF ICs. This paper addresses issues such as technology
requirement, transceiver architecture, circuit topologies as well as the
extent of integration, in the context of power consumption.
8.2 - 2:55pm
A Low Power CMOS Super-Regenerative Receiver at 1 GHz
A. Vouilloz, C. Dehollain and M. Declercq, Swiss Federal Institute of
Technology, Lausanne, Switzerland
Abstract :
A low-power and low-voltage super-regenerative receiver operating at 1
GHz and implemented in a 0.35 um CMOS process is described. The receiver
includes a LNA, a super-regenerative oscillator, an envelope detector,
an AGC circuitry with sample/hold capability and a baseband amplifier.
The power consumption is less than 1.2 mW at VDD = 1.5 V.
8.3 - 3:20pm
A 1v, 1mW, 434 MHz FSK Receiver Fully Integrated in a Standard Digital
CMOS Process
A. Porret, T. Melly, D. Python, C. Enz* and E. Vittoz*,
Swiss Federal Institute of Technology, Lausanne, Switzerland and *CSEM,
Neuchatel, Switzerland
Abstract :
A broad range of new applications require the availability of ultra
low-power wireless microsystems. For such applications, a direct
conversion receiver was realized in a 0.5um CMOS process. It uses FSK
modulation in the 434MHz ISM band and consumes 1mW with a 1V supply,
allowing single battery cell operation. It achieves a -95dBm sensitivity
for a data rate of 24kbps.
8.4 - 3:45pm
A Dual-Band RF Front-End for WCDMA and GSM Applications
J. Ryynanen, K. Kivekas, J. Jussila, A. Parssinen and K. Halonen,
Helsinki University of Technology, Helsinki, Finland
Abstract :
Paper presents a dual-band, dual-mode RF front-end for direct conversion
WCDMA and GSM receivers. It consumes 22.5 mW from a 1.8 V supply. The
noise figure, gain, and IIP3 are 2.3 dB, 39.5 dB, and -19 dBm for GSM
and 4.3 dB, 33 dB, and -14.5 dBm for WCDMA, respectively.
8.5 - 4:10pm
A 1.2 V, 433 MHz, 10dBm, 38% Global Efficiency FSK Transmitter
Integrated in a Standard Digital CMOS Process
T. Melly, A. Porret, C.
Enz* and E. Vittoz*, Swiss Federal Institute of Technology, Lausanne,
Switzerland and *CSEM, Neuchatel, Switzerland
Abstract :
This paper describes the design of an FSK transmitter for the 433MHz ISM
(Industrial, Scientific, Medical) band, which is realized in a standard
digital 0.5um CMOS technology. It includes the power amplifier itself,
an upconverter, and the circuit generating the base-band quadrature
signals with a continuous modulation phase. The overall measured
efficiency of the circuit is higher than 38% for 1.2V supply and an
output power reaching 10dBm at 433MHz.
8.6 - 4:35pm
Frequency-Scalable SiGe Bipolar RFIC Front-end Design
O. Shana'a, I.
Linscott and L. Tyler, Stanford University, Stanford, CA
Abstract :
An analytical method to design a bipolar low noise amplifier (LNA) at
the optimum noise figure point is derived. The design scales linearly
with frequency. The method is extended to the design of an improved
Gilbert cell active mixer. The technique was demonstrated on a 1.8 GHz
SiGe bipolar RF front-end whose LNA achieves a 1.3dB NF at a bias
current of 4.5 mA while the mixer achieves a single-sideband noise
figure (SSB NF) of 6.5dB at only 4.8mA.
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