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Session 1 - Plenary Session
1.1 - 8:00am
Welcome and Opening Remarks,
Awards Presentations,
Keynote Speaker Introduction
Brian Fitzgerald, General Chairman
1.2 - 8:20am
Keynote Address:
"SOC: The Convergence Point for Solutions of the 21st Century"
Joe Pumo, Director, SoC Design Technology Group, Motorola
Abstract :
The future challenge from the customer is to deliver a complete solution
that meets system requirements - function, performance and price - in a
competitive time-to-market. The answer: A System-on-a-Chip (SoC). The
term "SoC" defines a product that is targeted for a specific application
and contains an entire system, complete with embedded software. SoC also
defines a process which starts with system requirements, which are
modeled, analyzed and partitioned into hardware and software for design
and implementation.
This process depends on four capabilities which build upon one another
to make SoC a reality. The first capability, Manufacturing Technology,
is the basic enabler for SoC. Silicon processing, packaging and test
technology are advancing rapidly to accommodate the higher complexity of
integrated systems. Price and performance goals can be met through the
smaller geometries, more efficient connectivity, and integration of base
technologies like digital and analog. The complexities afforded by the
technology require a second capability, that of Silicon Implementation.
Silicon Implementation, the conversion of data from design
representation level to manufacturing formats, must be enhanced to deal
with the high device counts and mixed device types.
The tools commonly used in Silicon Implementation must improve their
efficiency and accuracy in order to maintain product schedules and
performance. Due to the discrepancy between the complexity provided by
the Manufacturing Technology and delivered through Silicon
Implementation, a third capability, Reusable IP Portfolio, is required.
The Reusable IP Portfolio provides a central location for strategic
blocks of IP which have been designed for reuse. They must be readily
available and easily reusable blocks to be able to plug- and-play into
SoC designs, greatly reducing the overall cycle time. In order to
identify and define strategic blocks to be placed in the Portfolio, a
fourth capability, System Design Skills, is needed. System Design Skills
provide the ability to work above the level of hardware/software
partitioning to define a complete system at a high level representation
where tradeoffs can be made most efficiently. Well thought out systems
will be the platforms from which IP can be reused in many SoC
implementations and are the keys to success.
These SoC platforms will become more and more prevalent as the various
consumer markets with heavy utilization of electronics converge.
Consumers of entertainment devices desire the flexibility and
performance provided by computing and networking. The computer and
communications industries are merging as wireless networking capability
expands and more consumers demand hand-held computing capability.
Communications and transportation markets converge as advanced features
such as GPS are appearing in automobiles. These markets will continue
to be the driving force behind the need for single chip silicon based
system platforms.
1.3 - 10:00am
Special Technical Session - ASIC Packaging
Sanjay Dandia, Philips Semiconductors
Abstract :
Today's ICs are bringing a new revolution in the semiconductor
packaging. It is no longer a backend activity needed to ship a product
out to a customer. The increasing number of I/Os per semiconductor chip
combined with product-driven requirements of size, performance and cost
are driving semiconductor packaging and assembly in new areas.
This presentation will begin by examining the traditional QFP packages,
what they offer and their limitations. Next, area array packaging (BGA,
DCA etc.) will be discussed. This is the technology that is growing and
is here to stay. Several styles of this package are offered today.
Package construction will be compared to study the performance and cost
tradeoffs. Market segments that are served by these packages will also
be looked.
Assembly processes will be briefly discussed with an emphasis on the
interconnect technology. The traditional approach is wire bonding but
future applications are demanding flip chip technology. Interactions
between silicon and various packages will be evaluated to understand the
impact on package design, cost, performance, product reliability, etc.
"System on a Chip" is here. How has it affected the world of packaging?
What is being done to address this? New materials for packaging, new
tools to design and new ways to optimize for cost and performance will
be reviewed. The presentation will conclude with a discussion on the
challenges for the semiconductor packaging to address the needs of next
generation ICs.
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Session 2 - Oversampled Analog-to-Digital Converters
Chairman: Timothy Rueger, Crystal Semiconductor
Co-Chairman Douglas Garrity, Motorola
This session features developments in oversampled analog-to-digital
converters with applications covering a wide range of bandwidths. Both
single-bit and multi-bit techniques are presented.
10:00am - Introduction
2.1 - 10:05am
142dB Delta-Sigma ADC with a 100nV LSB in a 3V CMOS Process
R. Naiknaware and T. Fiez*, Washington State University, Pullman, WA
and *Oregon State University, Corvallis, OR
Abstract :
A delta-sigma ADC designed in a 0.6um CMOS process uses a reference
voltage of only 1.0V to provide a dynamic range of 142dB and 132dB with
a bandwidth of 100 and 1000Hz, respectively. The power optimized ADC
implemented using a noise cancellation strategy has a noise floor of
-168dB and consumes 22.8mW from a single 3.0V supply.
2.2 - 10:30am
A 20 Bit 25kHz Delta Sigma A/D Converter Utilizing Frequency-Shaped
Chopper Stabilization Scheme
C. Wang, Burr Brown Corporation, Tucson, AZ
Abstract :
A 20 bit 25KHz Delta Sigma A/D converter is implemented for high-speed
DC measurement. Offset and finite gain compensation technique is used in
the front-end Programmable Gain Amplifier to effectively reduce the
linearity error of the amplifier and to improve the drift performance.
In the Delta Sigma converter, low frequency error reduction is achieved
through chopper stabilization technique. A novel frequency-shaped
chopper stabilization scheme is used to alleviate the inter-modulation
tone problem commonly exists due to the use of fix frequency chopping in
Delta Sigma modulators.
2.3 - 10:55am
A 1V 1mW Digital-Audio Delta-Sigma Modulator with 88dB Dynamic Range
using Local Switch Bootstrapping
M. Dessouky and A. Kaiser*, University of Paris, Paris, France and
*CNRS, Lille, France
Abstract :
A 1V, 1mW, 14 bit delta-sigma modulator in a standard CMOS 0.35-um
technology is presented. A modified symmetrical bootstrapped switch is
used in order to allow rail-to-rail signal switching. A single-loop
third-order topology with an oversampling ratio of 100 achieves a
dynamic range of 88 dB, a peak SNR of 87 dB and a peak SNDR of 85 dB in
a signal bandwidth of 25 kHz.
2.4 - 11:20am
An Audio ADC Delta-Sigma Modulator with 100dB SINAD and 102dB DR Using a
Second-Order Mismatch-Shaping DAC
E. Fogleman, J. Welz and I. Galton,
University of California, San Diego, CA
Abstract :
A second-order audio ADC delta-sigma modulator using a low-complexity
33-level second-order mismatch-shaping DAC is presented. The DAC
encoder is designed to reduce signal-dependent DAC noise modulation.
The prototype was implemented in a 3.3V 0.5um single-poly CMOS process,
and it achieves 100dB SINAD and 102dB DR.
2.5 - 11:45am
A 12-bit 12.5 MS/s Multi-Bit Delta-Sigma CMOS ADC
Y. Geerts, M. Steyaert and W. Sansen, Katholiecke University Leuven,
Heverlee, Belgium
Abstract :
A third-order multi-bit delta-sigma converter in a 0.65 um CMOS process
is presented. The improved performance of multi-bit topologies is
exploited to reduce the oversampling ratio to 8, while still achieving a
12-bit resolution. A clock-speed of 100 MHz results in a 12.5 MS/s
output rate.
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Session 3 - Advanced Communications Subsystems
Chairman: Jerry Molnar
Co-Chairman Kris Iniewski
Today's SOC devices are comprised of complex subsystems that combine
circuit and architectural design knowledge. This session presents
developments that span novel modulation techniques, low-jitter clock
generation, and state-of-the-art error-correction methods.
10:00am - Introduction
3.1 - 10:05am
A 8.75-MBaud Single - Chip Digital QAM Modulator With Frequency-Agility
and Beamforming Diversity
K. Cho and H. Samueli*, CogNet MicroSystems,
Los Angeles, CA and *University of California, Los Angles, CA
Abstract :
A VLSI implementation of an all-digital frequency-agile single-chip
quadrature amplitude modulation (QAM) modulator is presented. The
proposed chip supports wide variety data rates with diversity in spatial
and frequency domain suitable for wireless modem. The QAM modulator
accepts either a parallel or serial bit stream input and assigns this to
various QAM symbol formats for transmission. An optimized architecture
for the variable modulator supports QAM symbol rates from 6kBaud to
8.75MBaud continuously and digitally-flexible IF frequencies up to 70
MHz with four channel beamforming diversity.
3.2 - 10:30am
Direct Digital Frequency Synthesis Of Low-Jitter Clocks
D. Calbaza and
Y. Savaria, Ecole Polytechnique de Montreal, Montreal, Canada
Abstract :
This paper describes a new phase correction technique used to reduce the
error given by a DDS phase accumulator. A chip using the proposed method
has been fabricated. The test results shows that this chip produces a
very low jitter audio clock by using the video clock in the digital
television.
3.3 - 10:55am
A 2-V 3.7-mW Delay Locked-Loop Using Recycling Integrator Correlators
for a 5-Mcps DS-CDMA Demodulator
Y. Fujimoto, S. Kawama, K. Iizuka, M.
Miyamoto and D. Senderowicz*, Sharp Corporation, Nara, Japan and
*SynchroDesign Inc., Berkeley, CA
Abstract :
A Delay Locked-Loop for a 5-Mcps DS-CDMA demodulator targeting IMT-2000
has been implemented consisting of 6 correlators, each one incorporating
a form of delta-sigma modulation called recycling integrator.
Fabricated in 0.35-um CMOS process, the chip occupies 2.28 mm2 and
dissipates 3.7 mW with a supply voltage of 2 V.
3.4 - 11:20am
A K=3, 2Mbps Low Power Turbo Decoder for 3rd Generation W-CDMA Systems
H. Suzuki, Z. Wang* and K. Parhi*, Kawasaki Steel Corporation, Chiba,
Japan and * University of Minnesota, Minneapolis, MN
Abstract :
A K=3, 2Mbps Turbo decoder chip targeted for 3rd generation W-CDMA
systems has been designed using a 0.25um CMOS technology. In this work,
finite precision effects on the decoder performance are analyzed and
optimal word-lengths are determined, and novel power-down techniques are
proposed. The core size is 2.32mm x 1.72mm and contains 300K transistors.
3.5 - 11:45am
High-Performance Flexible All-Digital Quadrature Up and Down Converter
Chip
R. Pasko, L. Rijnders, P. Schaumont, S. Vernalde and D.
Durackova*, IMEC, Leuven, Belgium and *Slovak Technical University,
Bratislava, Slovakia
Abstract :
We present the design of an all-digital quadrature up and down converter
with high accuracy and flexible IF settings. The signal
up/downconversion is achieved by interpolation/decimation combined with
a programmable anti-alias filter preserving the selected frequency band
during the sample rate conversion. This way a high-speed solution with
low-power consumption is achieved. We used a novel technique to
implement flexible IF settings. The resulting structure is capable of
handling signals up to 160 MSPS and is suitable for coaxial access
network modem applications.
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Session 4 - Device and Semiconductor-Process Integration for SOC
Chairman: Ranbir Singh
Co-Chairman David Sunderland
We are facing the end of traditional scaling to provide technology
advancement. The papers in this session explore the limits of scaling
and propose alternatives to address the diverse requirements of SOC.
10:00am - Introduction
4.1 - 10:05am
CMOS in the New Millennium (Invited)
T. Ning, IBM Thomas J. Watson
Research Center, Yorktown Heights, NY
Abstract :
As we approach the limits of CMOS scaling in the next few years, the
application of CMOS to RF will continue to grow while the performance of
digital CMOS will saturate. The properties and challenges of CMOS near
its limits, as well as opportunities beyond scaling CMOS, are discussed.
4.2 - 10:55am
Ultra Low-Power CMOS IC Using Partially-Depleted SOI Technology
A.
Ebina, T. Kadowaki, Y. Sato and M. Yamaguchi, Seiko Epson Corporation,
Nagano-ken, Japan
Abstract :
We developed the ultra low power IC for a wrist-watch application. The
realized operation current and voltage were 30nA and 0.42V respectively.
This extreme low power operation was achieved by taking full advantage
of body-floated devices with the partially-depleted SOI CMOS technology.
4.3 - 11:20am
A Fabrication Method for High Performance Embedded DRAM of 0.18um
Generation and Beyond
T. Yoshida, H. Takato, T. Sakurai, K. Kokubun,
K. Hiyama, A. Nomachi*, Y. Takasu*, M. Kishida*, H. Ohtsuka*, H.
Naruse*, Y. Morimasa*, N. Yanagiya*, T. Hashimoto*, T. Noguchi*, T.
Miyamae**, N. Iwabuchi***, M. Tanaka**, J. Kumagai and H. Ishiuchi, ULSI
Device Engineering Laboratory, *Toshiba Corporation, **Toshiba
Microelectronics Corporation and ***Toshiba Engineering Corporation,
Yokohama, Japan
Abstract :
A new fabrication method for 0.18um embedded DRAM is proposed, which
realizes full compatibility of LOGIC process such as Co salicide, dual
work function gate, small thermal budget and metalization, and
introduces Self-aligned Salicide Block (SSB) process. Fabricated embedded
DRAM shows excellent characteristics respecting both retention time and
MOSFET AC/DC performance.
4.4 - 11:45am
NV-SRAM: A Nonvolatile SRAM with Back-up Ferroelectric Capacitors
T.
Miwa, J. Yamada, H. Koike, H. Toyoshima, K. Amanuma, S. Kobayashi, T.
Tatsumi, Y. Maejima, H. Hada and T. Kunio, NEC Corporation, Kanagawa,
Japan
Abstract :
This paper demonstrates new circuit technologies that enable a 0.25-um
ASIC SRAM macro to be nonvolatile with only a 17% cell area overhead.
New capacitor-on-metal/via-stacked-plug process technologies make it
possible for a NV-SRAM cell to consist of a six-transistor ASIC SRAM
cell and two back-up ferroelectric capacitors stacked over the SRAM
portion.
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