CICC 1999 Papers and Presentations: IEEE Journal of Solid State Circuits Issue

The outstanding papers from CICC '98 are featured in the March, 1999, issue of the IEEE Journal of Solid State Circuits (JSSC).

Below you can find the editorial that leads off the issue.

CICC '98 - Introduction from the March '99 JSSC

The selected papers from the 1998 Custom Integrated Circuits Conference reflect the continuing drive towards higher performance, lower power and higher levels of integration. These papers are broadly categorized into two sections: analog/RF and digital. A total of 16 regular papers and 1 brief paper cover topics ranging from analog and RF design to architecture and algorithms.

The first two papers in this special issue address the increasing challenges and/or opportunities encountered by analog/RF designers working in deep-submicron CMOS processes. In the paper entitled "CMOS Technology Characterization for Analog and RF Design," Razavi describes the inadequacies of "digital" modeling and characterization methodologies as applied to analog and RF integrated circuit (IC) design. He then proposes a set of technology characterization methods that provide the basic information that is required for analog and RF IC design. The following paper by Manku is tutorial in nature and provides a qualitative understanding of the microwave properties of CMOS devices and related design issues. The network properties, frequency response, microwave noise properties, and microwave scaling rules for CMOS devices are discussed.

The next two papers present examples of the outstanding performance that can be achieved in RF integrated circuits. The first, by Tham et al., describes a dual-band (900MHz/1.9GHz) transceiver IC for digital wireless communications. The IC has been fabricated in a 25GHz ft silicon bipolar process, and includes receive, transmit, and local oscillator sections. The second by Huang et al. addresses the implementation of GSM transceiver front-end circuits in 0.25um CMOS. Particular attention is given to low noise and low power design. Low noise amplifiers with sub-2dB noise figures, a double balanced mixer with 12db SSB NF, as well as sub-25mA current consumption for the entire RF receiver front-end are achieved.

The critical real-world issues of design cycle time reduction and test of complex mixed signal IC's are addressed in the next two papers. An effective method of design cycle time reduction is the automation of strategic portions of the design flow. In their paper entitled "Automated Hierarchical CMOS Analog Circuit Stack Generation with Intra-Module Connectivity and Matching Considerations," Niaknaware and Fiez describe such an approach wherein the layout of CMOS transistors in precision analog circuits is automated. Transistor matching requirements are used as the primary constraint on the layout, however, parasitic capacitances, area considerations, and aspect-ratio constraints are also considered. The excellent results are demonstrated through several examples. Built-in Self-Test (BIST) is a way to reduce test complexity for mixed-signal ICs by incorporating all or some of the test circuitry on the IC to be tested. An important component of mixed-signal BIST is a precision analog signal generator for on-chip stimulation. In the next paper, Dufort and Roberts present a simple, low cost method for generating various types of precision analog signals for BIST. The technique consists of periodically reproducing short, optimized bitstreams recorded from the output of a sigma-delta modulator. Two different silicon implementations are presented and analyzed through experimental results.

The final three regular papers of the analog/RF portion of this special issue describe advances in A/D conversion and amplifier design. In their paper, Shui et al. present a technique for noise-shaping the error caused by static element mismatch in a continuous-time multi-bit D/A converter. The dynamic errors caused by frequent element switching in such a D/A converter are also addressed. The resulting mismatch shaping algorithm is then applied to yield a continuous-time sigma-delta D/A converter that is insensitive to both static and dynamic effects. Experimental results confirm the effectiveness of the proposed techniques. In the following paper, Ng et al. introduce a new multi-stage amplifier technique that requires only N-2 embedded compensation networks for N gain stages. In addition, the compensation circuits do not load the output stage, and non-inverting gain stages are not required. The proposed technique is applied to the design of a prototype three-stage amplifier that achieves 102db gain, 47MHz bandwidth, and 69V/us slew rate with a 40pF load. The amplifier was fabricated in a 0.6um CMOS process. The final analog/RF regular paper by Yang et al. describes the first viable Nyquist rate pixel level A/D converter for CMOS image sensors. The ADC uses successive comparisons to output one bit at a time simultaneously from all pixels. A CMOS 320x256 sensor using A/D converter is also described. It achieves 10um X 10um pixel size at 28% fill factor in 0.35um CMOS.

The second half of this special issue starts with two technology papers. The first paper by Iwai is entitled "CMOS Technology - Year 2010 and beyond." Even before the MOSFET reaches it fundamental limit, downsizing will face technological and economic problems. The difficulties that will be encountered as the feature size decreases from 0.1 to sub 0.1um technology are presented. The next paper by Chen et al., compares asymmetric and symmetric LDD NMOSFET devices from a reliability and performance perspective. The asymmetric devices can be operated at a lower Vdd while still maintaining a higher Idsat for the same hot-carrier lifetime. Ring oscillators with asymmetric NMOS devices can achieve 5% higher speed and 10% lower power.

A circuit technique eliminating clock skew is covered in the third paper entitled "A Direct Skew Detect Synchronous Mirror Delay for Application Specific Integrated Circuits" by Saeki et al. This is a non-feedback technique that can suppress clock-skew in only two clock cycles. Measurements have demonstrated that 2 to 3ns of clock skew can be eliminated for a clock operating at 200MHz.

The next three papers cover VLSI architectures and implementation of algorithms. The first in this set is "A Low-Power, High-Performance, 1024-point FFT processor" by Baas. He describes an energy efficient 1024-point FFT processor in a standard 0.7um CMOS process. The chip contains 460,000 transistors and operates at a supply voltage of 1.1V with an energy efficiency sixteen times better than previous known work. By raising the supply voltage to 3.3V, the chip operates at a clock rate 2.6 times greater than prior designs. The next paper in this series is "A New Scalable VLSI Architecture for REED Solomon Decoders" by Wilhelm. This chip combines a time sharing technique that allows a regular multiplexed architecture to be developed for performing finite field division. This approach also offers a smaller area in comparison to other previous work. The pipeline strategy allows data rates of 1.28Gb/s to be reached in 0.5um CMOS technology. The next paper is a 16 bit DSP Mobile Communication Accelerator by Kim et al. This is a fixed point DSP with an instruction set based on the GSM (Global System for Mobile Communications) standard. A hardware block of a Viterbi equalizer is used to accelerate key operations. This architecture allows a GSM baseband function typically requiring 53 MIPS (Million Instructions Per Second) to be executed using only 19MIPS. This chip has been fabricated in a 0.6um CMOS process.

The last regular paper is entitled "Reducing Switching Activity on Datapath Buses with Control-Signal Gating" by Kapadia et al. This paper describes a technique to reduce power dissipation by minimizing unnecessary switching activity in data paths. The modules that drive the bus are gated to prevent switching activity at its inputs from propagating to the bus when not required. A methodology for synthesizing the gated control signals is described. This technique has been applied to a 64-bit 2-way superscaler RISC microprocessor showing an average reduction of 26% in dynamic switching with no increase in critical path delay.

The final paper of this special issue is a brief paper by Menolfi and Huang wherein they describe a fully integrated CMOS instrumentation amplifier. The amplifier requires no trimming or external components and uses chopper modulation combined with a bandpass filter and a matching on-chip oscillator to achieve 77dB gain in a 600Hz bandwidth with input offset of 600nV, low frequency input noise of 8.5nV/root Hz, and low-frequency CMRR of greater than 150dB.

Doug Garrity
Thad Gabara
Guest editors