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Session 26 - Device and Substrate Analysis and Circuit Synthesis
Chairman: N.S. Nagaraj - Texas Instruments
Co-Chairman: Steffen Rochel - Simplex Solutions
1:30pm - Introduction
26.1 - 1:35pm
Wave Pipelining YADDs - A Feasibility Study
A. Mukherjee, M. Marek-Sadowska, S. Long, University of California,
Santa Barbara, CA
Abstract :
In this paper we study circuit structures obtained from direct mapping
to pass transistor logic (PTL) of Yet Another Decision Diagrams (YADDs).
These structures have almost equal delays along all the paths which
makes wave pipelining possible. We discuss the details of a complete
design, clocking and layout. In 0.5 micron CMOS technology, YADDs can be
clocked at a fixed rate of 715 MHz for any function. Our experimental
results suggest that 4 times increase of speed over standard cell design
is on the average possible for the price of similar area increase.
26.2 - 2:00pm
Design Impact of Positive Temperature Dependence of Drain Current in Sub
1V CMOS VLSIs
K. Kanda, K. Nose, H. Kawaguchi, T. Sakurai, University of Tokyo, Tokyo,
Japan
Abstract :
In low voltage CMOS designs, the on-state drain current of MOSFETs shows
positive temperature dependence. Together with the low threshold, a
possibility of temperature instability and speed variation increases.
The paper describes design implications in the low-voltage regime by
using circuit simulation environments incorporating temperature
variation in time and experiments using quarter micron MOSFETs and
32-bit adder.
26.3 - 2:25pm
ANACONDA: Robust Synthesis of Analog Circuits via Stochastic Pattern
Search
R. Phelps, M. Krasnicki, R. Rutenbar, L.R. Carley, J. Hellums*, Carnegie
Mellon University, Pittsburgh, PA, *Texas Instruments Inc., Dallas, TX
Abstract :
Analog synthesis tools have traditionally traded quality for speed,
substituting simplified circuit evaluation methods for full simulation
in order to accelerate the numerical search for solution candidates. In
this paper we develop a new numerical search algorithm efficient enough
to allow full circuit simulation of each circuit candidate, and robust
enough to find good solutions for difficult circuits. Comparison of
synthesized circuits against manual industrial designs demonstrates the
utility of the approach.
26.4 - 2:50pm
Circuit Partitioning by Quadratic Boolean Programming for Reconfigurable
Circuit Boards
Y. Choi, C. Rim, Sogang University, Seoul, Korea
Abstract :
We propose a new quadratic boolean programming problem formulation to
partition a circuit for FPGA based reconfigurable circuit boards in
which the routing topology among IC chips are predetermined. Nets
passing through IC chips in their interconnections are considered in the
formulation to complete their routing after implementing the circuits to
the system. We also describe a heuristic to efficiently solve the
problem. Experimental results show that our method generates the
partitions in which the average reduction of the I/O pins used are up to
18% compared to the previous method for all the benchmark circuits
tested.
26.5 - 3:15pm
Measurements and Analyses of Substrate Noise Waveform in Mixed Signal IC
Environment
M. Nagata, Y. Kashima, D. Tamura, T. Morie, A. Iwata, Hiroshima
University, Hiroshima, Japan
Abstract :
100ps time resolution measurements on a 0.4um CMOS transition
controllable noise source show peaks in the substrate voltage reflecting
logic transition frequencies have a width larger than the switching
time. Analyses with equivalent circuits clarify that this process
results from charge transfer between parasitic capacitance of entire
logic circuits and the external supply.
26.6 - 3:40pm
An Extended Bipolar Transistor Model for Substrate Crosstalk Analysis
M. Klemme, E. Barke, University of Hanover, Germany
Abstract :
100ps time resolution measurements on a 0.4um CMOS transition
controllable noise source show peaks in the substrate voltage reflecting
logic transition frequencies have a width larger than the switching
time. Analyses with equivalent circuits clarify that this process
results from charge transfer between parasitic capacitance of entire
logic circuits and the external supply.
26.7 - 4:05pm
Substrate Network Modeling for CMOS RF Circuit Simulation
S. Tin, K. Mayaram, Washington State University, Pullman, WA
Abstract :
The effect of the substrate network models for use in small-signal CMOS
RF circuit simulation is examined in conjunction with the BSIM3 MOSFET
model. It is shown that a simple, one resistance, substrate network
model provides sufficient accuracy for BSIM3 small-signal analyses up to
a frequency of 10 GHz in a 0.5um CMOS process.
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Session 27 - Custom Circuit Techniques for Communication Applications
Chairman: Tadahiro Kuroda - Toshiba
Co-Chairman: Koichiro Mashiko - Mitsubishi
1:30pm - Introduction
27.1 - 1:35pm
Low-Power Bit-Serial Viterbi Decoder for 3rd Generation W-CDMA Systems
H. Suzuki, Kawasaki Steel Corporation, Chiba, Japan, Y-N. Chang, K.
Parhi, University of Minnesota, Minneapolis, MN
Abstract :
A 256 states, rate 1/3, low-power Viterbi decoder for 3rd generation
W-CDMA Systems employs bit-serial arithmetic for the ACS
(Add-Compare-Select) operation. The core size is 2.46mm by 4.17mm in
0.5um 3-layer metal CMOS and it dissipates 9.8mW for 2Mbps operation at
1.8V.
27.2 - 2:00pm
A Low-Power Direct Digital Frequency Synthesizer Architecture for
Wireless Communications
A. Bellaouar, M. Obrecht, A. Fahim, M. Elmasry, University of Waterloo,
Waterloo, Ont., Canada
Abstract :
A novel low-power direct digital frequency synthesizer (DDFS)
architecture is presented. The sine and cosine functions are generated
by linearly interpolating between the sample points, reducing the size
of the ROM look-up table to 416 bits. The DDFS is implemented in 0.8um
CMOS technology and features 60dBc spectral purity, 48 Hz frequency
resolution, with only 9.5mW (@30MHz, 3.3V) power dissipation.
27.3 - 2:25pm
A Low-Power and Low-Noise CMOS Prescaler for 900 MHz to 1.9 GHz Wireless
Applications
W-H. Chang, D. Pehlke, R. Yu, Rockwell Science Center, Thousand Oaks, CA
Abstract :
A high-speed dual-modulus prescaler has been developed in 0.36-um CMOS.
The prescaler was designed for low-power frequency synthesizers for 900
MHz to 1.9 GHz wireless applications. It provides programmable division
ratio of 64, 65, 128, and 129. Power consumption was 2.9 mW with 1.9
GHz input frequency and 3.3 V power supply. The measured residual phase
noises were 142 dBc/Hz at 100 Hz offset and 166 dBc/Hz at 100 kHz
offset.
27.4 - 2:50pm
Giga Bit Per Second Per Pin Differential CMOS Circuits for Pseudo ECL
Signaling
H. Djahanshahi, F. Hansen*, C. Salama, University of Toronto, Ont.,
Canada, *Vitesse Semiconductor Corporation, Camarillo, CA
Abstract :
This paper presents high-speed differential CMOS circuits for giga bit
per second ECL-compatible serial data transmission. The circuits
include input and output (I/O) interfaces and a retiming flipflop. They
were implemented a 0.35um CMOS process and tested at 622Mb/s and
1.24Gb/s. The asynchronous performance of the I/O was tested at up to
2.5Gb/s.
27.5 - 3:15pm
A Cyclic CMOS Time-to-Digital Converter with Deep Sub-Nanosecond
Resolution
P. Chen, S-I. Liu, National Taiwan University, Taipei, Taiwan
Abstract :
A novel cyclic time-to-digital converter (TDC) is proposed in this
paper. The measured resolution can reach 68 picoseconds, and the
corresponding single-shot errors are around 1/2 LSB width. Under a
single 3.3V power supply, the operation current consumption is measured
to be 370 uA with 100 k/sec measurement rate.
27.6 - 3:40pm
Frequency Scalable Non-Linear Waveform Generator for Mixed-Signal
Power-Factor-Correction IC Controller
R. Zane, D. Maksimovic, University of Colorado, Boulder, CO
Abstract :
This paper derives a family of digital non-linear waveform generators
fundamental to the development of an adaptive mixed-signal IC controller
for power-factor-correction (PFC) of high-switching frequency AC-to-DC
converters with the objective of significantly lowering the cost of
rectifier design. The controller application is described along with
combined controller and power stage simulation results. Simple hardware
implementations of digital waveform generators are derived and verified
with experimental results from a 1.2um CMOS test chip.
27.7 - 4:05pm
A 1.5 GHz, Sub-2mW CMOS Dual-Modulus Prescaler
A. Benachour, S. Embabi, Texas A&M University, College-Station, TX, A.
Ali, Rockwell Semiconductor Systems, Newport Beach, CA
Abstract :
A 16/17 dual-modulus prescaler based on an improved phase switching
architecture has been designed. It will be shown that moving the
switching operation one stage closer to the input signal not only saves
a significant amount of power, but also results in a more robust
dual-modulus prescaler, which, further, has a greatly reduced
susceptibility to noise and spurious tones. With a 2.7V power supply,
measurements show that the prescaler draws less than 700uA while running
at 1.5GHz.
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Session 28 - SOC Core Integration and On-Chip Communication
Chairman: Scott Baker - Genesis Microchip Inc.
Co-Chairman: Jim Lipman - EDN Magazine
1:30pm - Introduction
28.1 - 1:35pm
VSIA Technical Challenges (invited)
H. Sachs*, M. Birnbaum, Fujitsu Microelectronics Inc., San Jose, CA and
*VSIA
Abstract :
The Virtual Socket Interface Alliance (VSIA) was formed to make
system-chip design a practical reality by enabling the mix and match of
virtual components from multiple sources on a single silicon chip. We
examine some of the technical challenges being dealt with by the seven
Development Working Groups of the VSIA.
28.2 - 2:25pm
An Efficient Bus Architecture for System-on-Chip Design
B. Cordan, Palmchip Corporation, Loveland, CO
Abstract :
This paper presents the issues confronted when integrating
system-on-chip (SOC) designs and offers solution through a detailed
description and examples of the CoreFrame system-on-chip bus
architecture that has dramatically reduce system design and verification
effort while enhancing the reusability and customizability of
system-on-chip application specific product developments.
28.3 - 2:50pm
A Bus Architecture Centric Configurable Processor System
S. Winegarden, Triscend Corporation, Mountain View, CA
Abstract :
A matrix of configurable logic is implemented with a dedicated internal
system bus extending throughout, linking user-designed slaves with an
embedded processor system. This complete, yet open, system on a chip is
designed for soft extension of the hardware by an application developer.
A structure was developed that provides a simple user interface yet
reliably delivers design performance after being integrated throughout
programmable logic.
28.4 - 3:15pm
Minimizing the Effect of the Host Bus on the Performance of a
Computational RAM Logic-in-Memory Parallel-Processing System
P. Nyasulu, R. Mason, W. Snelgrove, D. Elliott*, Carleton University,
Ottawa, Ont., Canada, *University of Alberta, Edmonton, Alberta, Canada
Abstract :
We describe system design techniques that have been employed to minimize
the effect of the host bus on the performance of a Computational RAM
logic-in-memory parallel-processing system. We show that because of the
performance-enhancement features of the controller, the transfer
characteristics of the host bus has very little effect on the
performance of a CRAM system. This allows the implementation of CRAM
systems on a variety of platforms, including those with slow external
buses.
28.5 - 3:40pm
The uPP ASIC: Design, Methodologies and Tools for a Pay Phone
System-on-a-Chip Based on an ARM Core and Design Reuse
J. Riesco, J. Diaz, P. Plaza, Telefonica Investigacion y Desarrollo,
Madrid, Spain
Abstract :
This paper describes the uPP (Microcontroller for Pay Phones) ASIC, a
system-on-a-chip solution based on the present Spanish pay phone system.
The design integrates an ARM embedded microprocessor, several third
party blocks and new custom modules developed in house, using ARM's
Advanced Microprocessors Bus Architecture (AMBA). The system has been
designed for low power consumption and management. Design reuse, aided
by the use of new management tools, and co-design, allowed an important
reduction in global design time.
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Session 29 - RF Building Blocks for Wireless Communications
Chairman: Lawrence Larson - University of California, San Diego
Co-Chairman: Vincent von Kaenel - Compaq
1:30pm - Introduction
29.1 - 1:35pm
Design of High-Q Varactors for Low-Power Wireless Applications using a
Standard CMOS Process
M. Porret, T. Melly, C. Enz*, Swiss Federal Institute of Technology,
Lausanne, Switzerland, *Rockwell Semiconductor Systems, Newport Beach,
CA
Abstract :
The power consumption of an LC-tank oscillator is strongly affected by
the varactor quality factor. This paper proposes a new solution to
realize high-Q on-chip varactors in a standard CMOS process, achieving a
quality factor higher than 100 at 1GHz, for a tuning ratio of 2 in a
0.5um CMOS process. Other solutions are described and measured while
their advantages are compared.
29.2 - 2:00pm
A 1.3GHz CMOS VCO with 28% Frequency Tuning
F. Svelto*, S. Deantoni**, R. Castello**, *Universita di Bergamo,
Dalmine, Italy, **Universita di Pavia, Pavia, Italy
Abstract :
A 2V, 6mA, 1.3GHz LC-tank CMOS VCO is presented. The tank is made of a
Metal-Oxide-Silicon varactor and the series of a bondwire and a spiral
inductor. This solution allows to tune all components variations, while
gain is mantained constant within +/-20% of the central value. Measured
phase noise at 600kHz from 1.3GHz is -119dbc/Hz.
29.3 - 2:25pm
A Quarter-Micron CMOS, 1GHz VCO/Prescaler-Set for Very Low Power
Applications
D. Pfaff, Q. Huang, Swiss Federal Institute of Technology, Zurich,
Switzerland
Abstract :
A VCO and a prescaler designed for wireless applications with very low
power consumption requirements are presented. The VCO has a phase noise
of -111dBc/Hz at 100kHz offset from a 1GHz carrier and a tuning range of
18% while consuming only 250uA from a 2.5V supply. The 64/65 dual
modulus prescaler operates at the same frequency with only 0.9mW.
29.4 - 2:50pm
Fully Integrated Low Phase-Noise PLLs Using Closed-Loop
Voltage-to-Frequency Converter Architectures
A. Hafez, M. Elmasry, University of Waterloo, Waterloo, Ont., Canada
Abstract :
A VCO is configured in a wide-bandwidth voltage-locked feedback loop
that suppresses the VCO phase-noise. By configuring this architecture in
a PLL, low phase-noise frequency synthesis is possible using integrated
VCOs. The proposed architecture is designed in a 0.8um BiCMOS technology
and achieves up to 20dB reduction in the integrated VCO phase-noise.
29.5 - 3:15pm
A Wideband Quadrature LO Generator in Digital CMOS
J. Harrison, N. Weste, Macquarie University, Sydney, Australia
Abstract :
A quadrature LO generator using only CMOS transistors produces
quadrature outputs with a phase error of less than 2 degrees over 200MHz
to 950MHz from a single phase input. The circuit uses a novel
multiple-stage topology with inverters as phase delay elements.
29.6 - 3:40pm
A 900-MHz, 0.8-um CMOS Low Noise Amplifier with 1.2-dB Noise Figure
B. Floyd, J. Mehta, C. Gamero, K. O, University of Florida, Gainesville,
FL
Abstract :
A 900-MHz single-stage low noise amplifier (LNA) has been implemented in
a standard digital 0.8um CMOS technology. At 30 mW and VDD=3.0 V, the
LNA has a noise figure of 1.2 dB, a power gain of 14.5 dB, and an IIP3
of -1 dBm. At 6.2 mW and VDD=2.7 V, the LNA has a noise figure of 2 dB,
a power gain of 9.4 dB, and an IIP3 of -3.8 dBm.
29.7 - 4:05pm
A 1V 900MHz Image-Reject Downconverter in 0.5um CMOS
J. Long, University of Toronto, Toronto, Ont., Canada, M. Maliepaard,
Nortel Networks, Ottawa, Ont., Canada
Abstract :
A monolithic image-reject downconverter consisting of preamplifier and
dual doubly-balanced mixers realizes an image-rejection of 44dB in a
0.5um CMOS technology. The measured input third-order intercept (IIP3)
is -4.7dBm, conversion gain is 13dB, and the noise figure is 9.3dB (SSB
50Ohm) at 900MHz. The IC consumes 21mW from a 1V supply.
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